arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a8";
  24                         reg = <0x0>;
  25                 };
  26         };
  27
  28         memory {
  29                 reg = <0x40000000 0x80000000>;
  30         };
  31
  32         clocks {
  33                 #address-cells = <1>;
  34                 #size-cells = <1>;
  35                 ranges;
  36
  37                 /*
  38                  * This is a dummy clock, to be used as placeholder on
  39                  * other mux clocks when a specific parent clock is not
  40                  * yet implemented. It should be dropped when the driver
  41                  * is complete.
  42                  */
  43                 dummy: dummy {
  44                         #clock-cells = <0>;
  45                         compatible = "fixed-clock";
  46                         clock-frequency = <0>;
  47                 };
  48
  49                 osc24M: osc24M@01c20050 {
  50                         #clock-cells = <0>;
  51                         compatible = "allwinner,sun4i-osc-clk";
  52                         reg = <0x01c20050 0x4>;
  53                         clock-frequency = <24000000>;
  54                 };
  55
  56                 osc32k: osc32k {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 pll1: pll1@01c20000 {
  63                         #clock-cells = <0>;
  64                         compatible = "allwinner,sun4i-pll1-clk";
  65                         reg = <0x01c20000 0x4>;
  66                         clocks = <&osc24M>;
  67                 };
  68
  69                 /* dummy is 200M */
  70                 cpu: cpu@01c20054 {
  71                         #clock-cells = <0>;
  72                         compatible = "allwinner,sun4i-cpu-clk";
  73                         reg = <0x01c20054 0x4>;
  74                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  75                 };
  76
  77                 axi: axi@01c20054 {
  78                         #clock-cells = <0>;
  79                         compatible = "allwinner,sun4i-axi-clk";
  80                         reg = <0x01c20054 0x4>;
  81                         clocks = <&cpu>;
  82                 };
  83
  84                 axi_gates: axi_gates@01c2005c {
  85                         #clock-cells = <1>;
  86                         compatible = "allwinner,sun4i-axi-gates-clk";
  87                         reg = <0x01c2005c 0x4>;
  88                         clocks = <&axi>;
  89                         clock-output-names = "axi_dram";
  90                 };
  91
  92                 ahb: ahb@01c20054 {
  93                         #clock-cells = <0>;
  94                         compatible = "allwinner,sun4i-ahb-clk";
  95                         reg = <0x01c20054 0x4>;
  96                         clocks = <&axi>;
  97                 };
  98
  99                 ahb_gates: ahb_gates@01c20060 {
 100                         #clock-cells = <1>;
 101                         compatible = "allwinner,sun4i-ahb-gates-clk";
 102                         reg = <0x01c20060 0x8>;
 103                         clocks = <&ahb>;
 104                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 105                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 106                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 107                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 108                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 109                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 110                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 111                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 112                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 113                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 114                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 115                 };
 116
 117                 apb0: apb0@01c20054 {
 118                         #clock-cells = <0>;
 119                         compatible = "allwinner,sun4i-apb0-clk";
 120                         reg = <0x01c20054 0x4>;
 121                         clocks = <&ahb>;
 122                 };
 123
 124                 apb0_gates: apb0_gates@01c20068 {
 125                         #clock-cells = <1>;
 126                         compatible = "allwinner,sun4i-apb0-gates-clk";
 127                         reg = <0x01c20068 0x4>;
 128                         clocks = <&apb0>;
 129                         clock-output-names = "apb0_codec", "apb0_spdif",
 130                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 131                                 "apb0_ir1", "apb0_keypad";
 132                 };
 133
 134                 /* dummy is pll62 */
 135                 apb1_mux: apb1_mux@01c20058 {
 136                         #clock-cells = <0>;
 137                         compatible = "allwinner,sun4i-apb1-mux-clk";
 138                         reg = <0x01c20058 0x4>;
 139                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 140                 };
 141
 142                 apb1: apb1@01c20058 {
 143                         #clock-cells = <0>;
 144                         compatible = "allwinner,sun4i-apb1-clk";
 145                         reg = <0x01c20058 0x4>;
 146                         clocks = <&apb1_mux>;
 147                 };
 148
 149                 apb1_gates: apb1_gates@01c2006c {
 150                         #clock-cells = <1>;
 151                         compatible = "allwinner,sun4i-apb1-gates-clk";
 152                         reg = <0x01c2006c 0x4>;
 153                         clocks = <&apb1>;
 154                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 155                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 156                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 157                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 158                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 159                                 "apb1_uart7";
 160                 };
 161         };
 162
 163         soc@01c00000 {
 164                 compatible = "simple-bus";
 165                 #address-cells = <1>;
 166                 #size-cells = <1>;
 167                 ranges;
 168
 169                 emac: ethernet@01c0b000 {
 170                         compatible = "allwinner,sun4i-emac";
 171                         reg = <0x01c0b000 0x1000>;
 172                         interrupts = <55>;
 173                         clocks = <&ahb_gates 17>;
 174                         status = "disabled";
 175                 };
 176
 177                 mdio@01c0b080 {
 178                         compatible = "allwinner,sun4i-mdio";
 179                         reg = <0x01c0b080 0x14>;
 180                         status = "disabled";
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                 };
 184
 185                 intc: interrupt-controller@01c20400 {
 186                         compatible = "allwinner,sun4i-ic";
 187                         reg = <0x01c20400 0x400>;
 188                         interrupt-controller;
 189                         #interrupt-cells = <1>;
 190                 };
 191
 192                 pio: pinctrl@01c20800 {
 193                         compatible = "allwinner,sun4i-a10-pinctrl";
 194                         reg = <0x01c20800 0x400>;
 195                         interrupts = <28>;
 196                         clocks = <&apb0_gates 5>;
 197                         gpio-controller;
 198                         interrupt-controller;
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         #gpio-cells = <3>;
 202
 203                         uart0_pins_a: uart0@0 {
 204                                 allwinner,pins = "PB22", "PB23";
 205                                 allwinner,function = "uart0";
 206                                 allwinner,drive = <0>;
 207                                 allwinner,pull = <0>;
 208                         };
 209
 210                         uart0_pins_b: uart0@1 {
 211                                 allwinner,pins = "PF2", "PF4";
 212                                 allwinner,function = "uart0";
 213                                 allwinner,drive = <0>;
 214                                 allwinner,pull = <0>;
 215                         };
 216
 217                         uart1_pins_a: uart1@0 {
 218                                 allwinner,pins = "PA10", "PA11";
 219                                 allwinner,function = "uart1";
 220                                 allwinner,drive = <0>;
 221                                 allwinner,pull = <0>;
 222                         };
 223
 224                         i2c0_pins_a: i2c0@0 {
 225                                 allwinner,pins = "PB0", "PB1";
 226                                 allwinner,function = "i2c0";
 227                                 allwinner,drive = <0>;
 228                                 allwinner,pull = <0>;
 229                         };
 230
 231                         i2c1_pins_a: i2c1@0 {
 232                                 allwinner,pins = "PB18", "PB19";
 233                                 allwinner,function = "i2c1";
 234                                 allwinner,drive = <0>;
 235                                 allwinner,pull = <0>;
 236                         };
 237
 238                         i2c2_pins_a: i2c2@0 {
 239                                 allwinner,pins = "PB20", "PB21";
 240                                 allwinner,function = "i2c2";
 241                                 allwinner,drive = <0>;
 242                                 allwinner,pull = <0>;
 243                         };
 244
 245                         emac_pins_a: emac0@0 {
 246                                 allwinner,pins = "PA0", "PA1", "PA2",
 247                                                 "PA3", "PA4", "PA5", "PA6",
 248                                                 "PA7", "PA8", "PA9", "PA10",
 249                                                 "PA11", "PA12", "PA13", "PA14",
 250                                                 "PA15", "PA16";
 251                                 allwinner,function = "emac";
 252                                 allwinner,drive = <0>;
 253                                 allwinner,pull = <0>;
 254                         };
 255                 };
 256
 257                 timer@01c20c00 {
 258                         compatible = "allwinner,sun4i-timer";
 259                         reg = <0x01c20c00 0x90>;
 260                         interrupts = <22>;
 261                         clocks = <&osc24M>;
 262                 };
 263
 264                 wdt: watchdog@01c20c90 {
 265                         compatible = "allwinner,sun4i-wdt";
 266                         reg = <0x01c20c90 0x10>;
 267                 };
 268
 269                 sid: eeprom@01c23800 {
 270                         compatible = "allwinner,sun4i-sid";
 271                         reg = <0x01c23800 0x10>;
 272                 };
 273
 274                 uart0: serial@01c28000 {
 275                         compatible = "snps,dw-apb-uart";
 276                         reg = <0x01c28000 0x400>;
 277                         interrupts = <1>;
 278                         reg-shift = <2>;
 279                         reg-io-width = <4>;
 280                         clocks = <&apb1_gates 16>;
 281                         status = "disabled";
 282                 };
 283
 284                 uart1: serial@01c28400 {
 285                         compatible = "snps,dw-apb-uart";
 286                         reg = <0x01c28400 0x400>;
 287                         interrupts = <2>;
 288                         reg-shift = <2>;
 289                         reg-io-width = <4>;
 290                         clocks = <&apb1_gates 17>;
 291                         status = "disabled";
 292                 };
 293
 294                 uart2: serial@01c28800 {
 295                         compatible = "snps,dw-apb-uart";
 296                         reg = <0x01c28800 0x400>;
 297                         interrupts = <3>;
 298                         reg-shift = <2>;
 299                         reg-io-width = <4>;
 300                         clocks = <&apb1_gates 18>;
 301                         status = "disabled";
 302                 };
 303
 304                 uart3: serial@01c28c00 {
 305                         compatible = "snps,dw-apb-uart";
 306                         reg = <0x01c28c00 0x400>;
 307                         interrupts = <4>;
 308                         reg-shift = <2>;
 309                         reg-io-width = <4>;
 310                         clocks = <&apb1_gates 19>;
 311                         status = "disabled";
 312                 };
 313
 314                 uart4: serial@01c29000 {
 315                         compatible = "snps,dw-apb-uart";
 316                         reg = <0x01c29000 0x400>;
 317                         interrupts = <17>;
 318                         reg-shift = <2>;
 319                         reg-io-width = <4>;
 320                         clocks = <&apb1_gates 20>;
 321                         status = "disabled";
 322                 };
 323
 324                 uart5: serial@01c29400 {
 325                         compatible = "snps,dw-apb-uart";
 326                         reg = <0x01c29400 0x400>;
 327                         interrupts = <18>;
 328                         reg-shift = <2>;
 329                         reg-io-width = <4>;
 330                         clocks = <&apb1_gates 21>;
 331                         status = "disabled";
 332                 };
 333
 334                 uart6: serial@01c29800 {
 335                         compatible = "snps,dw-apb-uart";
 336                         reg = <0x01c29800 0x400>;
 337                         interrupts = <19>;
 338                         reg-shift = <2>;
 339                         reg-io-width = <4>;
 340                         clocks = <&apb1_gates 22>;
 341                         status = "disabled";
 342                 };
 343
 344                 uart7: serial@01c29c00 {
 345                         compatible = "snps,dw-apb-uart";
 346                         reg = <0x01c29c00 0x400>;
 347                         interrupts = <20>;
 348                         reg-shift = <2>;
 349                         reg-io-width = <4>;
 350                         clocks = <&apb1_gates 23>;
 351                         status = "disabled";
 352                 };
 353
 354                 i2c0: i2c@01c2ac00 {
 355                         compatible = "allwinner,sun4i-i2c";
 356                         reg = <0x01c2ac00 0x400>;
 357                         interrupts = <7>;
 358                         clocks = <&apb1_gates 0>;
 359                         clock-frequency = <100000>;
 360                         status = "disabled";
 361                 };
 362
 363                 i2c1: i2c@01c2b000 {
 364                         compatible = "allwinner,sun4i-i2c";
 365                         reg = <0x01c2b000 0x400>;
 366                         interrupts = <8>;
 367                         clocks = <&apb1_gates 1>;
 368                         clock-frequency = <100000>;
 369                         status = "disabled";
 370                 };
 371
 372                 i2c2: i2c@01c2b400 {
 373                         compatible = "allwinner,sun4i-i2c";
 374                         reg = <0x01c2b400 0x400>;
 375                         interrupts = <9>;
 376                         clocks = <&apb1_gates 2>;
 377                         clock-frequency = <100000>;
 378                         status = "disabled";
 379                 };
 380         };
 381 };