arch/arm/boot/dts/ste-dbx5x0.dtsi

   1 /*
   2  * Copyright 2012 Linaro Ltd
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/mfd/dbx500-prcmu.h>
  14 #include <dt-bindings/arm/ux500_pm_domains.h>
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         soc {
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 compatible = "stericsson,db8500";
  22                 interrupt-parent = <&intc>;
  23                 ranges;
  24
  25                 cpus {
  26                         #address-cells = <1>;
  27                         #size-cells = <0>;
  28
  29                         cpu-map {
  30                                 cluster0 {
  31                                         core0 {
  32                                                 cpu = <&CPU0>;
  33                                         };
  34                                         core1 {
  35                                                 cpu = <&CPU1>;
  36                                         };
  37                                 };
  38                         };
  39                         CPU0: cpu@0 {
  40                                 device_type = "cpu";
  41                                 compatible = "arm,cortex-a9";
  42                                 reg = <0>;
  43                         };
  44                         CPU1: cpu@1 {
  45                                 device_type = "cpu";
  46                                 compatible = "arm,cortex-a9";
  47                                 reg = <1>;
  48                         };
  49                 };
  50
  51                 ptm@801ae000 {
  52                         compatible = "arm,coresight-etm3x", "arm,primecell";
  53                         reg = <0x801ae000 0x1000>;
  54
  55                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  56                         clock-names = "apb_pclk", "atclk";
  57                         cpu = <&CPU0>;
  58                         port {
  59                                 ptm0_out_port: endpoint {
  60                                         remote-endpoint = <&funnel_in_port0>;
  61                                 };
  62                         };
  63                 };
  64
  65                 ptm@801af000 {
  66                         compatible = "arm,coresight-etm3x", "arm,primecell";
  67                         reg = <0x801af000 0x1000>;
  68
  69                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  70                         clock-names = "apb_pclk", "atclk";
  71                         cpu = <&CPU1>;
  72                         port {
  73                                 ptm1_out_port: endpoint {
  74                                         remote-endpoint = <&funnel_in_port1>;
  75                                 };
  76                         };
  77                 };
  78
  79                 funnel@801a6000 {
  80                         compatible = "arm,coresight-funnel", "arm,primecell";
  81                         reg = <0x801a6000 0x1000>;
  82
  83                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
  84                         clock-names = "apb_pclk", "atclk";
  85                         ports {
  86                                 #address-cells = <1>;
  87                                 #size-cells = <0>;
  88
  89                                 /* funnel output ports */
  90                                 port@0 {
  91                                         reg = <0>;
  92                                         funnel_out_port: endpoint {
  93                                                 remote-endpoint =
  94                                                         <&replicator_in_port0>;
  95                                         };
  96                                 };
  97
  98                                 /* funnel input ports */
  99                                 port@1 {
 100                                         reg = <0>;
 101                                         funnel_in_port0: endpoint {
 102                                                 slave-mode;
 103                                                 remote-endpoint = <&ptm0_out_port>;
 104                                         };
 105                                 };
 106
 107                                 port@2 {
 108                                         reg = <1>;
 109                                         funnel_in_port1: endpoint {
 110                                                 slave-mode;
 111                                                 remote-endpoint = <&ptm1_out_port>;
 112                                         };
 113                                 };
 114                         };
 115                 };
 116
 117                 replicator {
 118                         compatible = "arm,coresight-replicator";
 119                         clocks = <&prcmu_clk PRCMU_APEATCLK>;
 120                         clock-names = "atclk";
 121
 122                         ports {
 123                                 #address-cells = <1>;
 124                                 #size-cells = <0>;
 125
 126                                 /* replicator output ports */
 127                                 port@0 {
 128                                         reg = <0>;
 129                                         replicator_out_port0: endpoint {
 130                                                 remote-endpoint = <&tpiu_in_port>;
 131                                         };
 132                                 };
 133                                 port@1 {
 134                                         reg = <1>;
 135                                         replicator_out_port1: endpoint {
 136                                                 remote-endpoint = <&etb_in_port>;
 137                                         };
 138                                 };
 139
 140                                 /* replicator input port */
 141                                 port@2 {
 142                                         reg = <0>;
 143                                         replicator_in_port0: endpoint {
 144                                                 slave-mode;
 145                                                 remote-endpoint = <&funnel_out_port>;
 146                                         };
 147                                 };
 148                         };
 149                 };
 150
 151                 tpiu@80190000 {
 152                         compatible = "arm,coresight-tpiu", "arm,primecell";
 153                         reg = <0x80190000 0x1000>;
 154
 155                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 156                         clock-names = "apb_pclk", "atclk";
 157                         port {
 158                                 tpiu_in_port: endpoint {
 159                                         slave-mode;
 160                                         remote-endpoint = <&replicator_out_port0>;
 161                                 };
 162                         };
 163                 };
 164
 165                 etb@801a4000 {
 166                         compatible = "arm,coresight-etb10", "arm,primecell";
 167                         reg = <0x801a4000 0x1000>;
 168
 169                         clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
 170                         clock-names = "apb_pclk", "atclk";
 171                         port {
 172                                 etb_in_port: endpoint {
 173                                         slave-mode;
 174                                         remote-endpoint = <&replicator_out_port1>;
 175                                 };
 176                         };
 177                 };
 178
 179                 intc: interrupt-controller@a0411000 {
 180                         compatible = "arm,cortex-a9-gic";
 181                         #interrupt-cells = <3>;
 182                         #address-cells = <1>;
 183                         interrupt-controller;
 184                         reg = <0xa0411000 0x1000>,
 185                               <0xa0410100 0x100>;
 186                 };
 187
 188                 scu@a04100000 {
 189                         compatible = "arm,cortex-a9-scu";
 190                         reg = <0xa0410000 0x100>;
 191                 };
 192
 193                 /*
 194                  * The backup RAM is used for retention during sleep
 195                  * and various things like spin tables
 196                  */
 197                 backupram@80150000 {
 198                         compatible = "ste,dbx500-backupram";
 199                         reg = <0x80150000 0x2000>;
 200                 };
 201
 202                 L2: l2-cache {
 203                         compatible = "arm,pl310-cache";
 204                         reg = <0xa0412000 0x1000>;
 205                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 206                         cache-unified;
 207                         cache-level = <2>;
 208                 };
 209
 210                 pmu {
 211                         compatible = "arm,cortex-a9-pmu";
 212                         interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 213                 };
 214
 215                 pm_domains: pm_domains0 {
 216                         compatible = "stericsson,ux500-pm-domains";
 217                         #power-domain-cells = <1>;
 218                 };
 219
 220                 clocks {
 221                         compatible = "stericsson,u8500-clks";
 222
 223                         prcmu_clk: prcmu-clock {
 224                                 #clock-cells = <1>;
 225                         };
 226
 227                         prcc_pclk: prcc-periph-clock {
 228                                 #clock-cells = <2>;
 229                         };
 230
 231                         prcc_kclk: prcc-kernel-clock {
 232                                 #clock-cells = <2>;
 233                         };
 234
 235                         rtc_clk: rtc32k-clock {
 236                                 #clock-cells = <0>;
 237                         };
 238
 239                         smp_twd_clk: smp-twd-clock {
 240                                 #clock-cells = <0>;
 241                         };
 242                 };
 243
 244                 mtu@a03c6000 {
 245                         /* Nomadik System Timer */
 246                         compatible = "st,nomadik-mtu";
 247                         reg = <0xa03c6000 0x1000>;
 248                         interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 249
 250                         clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
 251                         clock-names = "timclk", "apb_pclk";
 252                 };
 253
 254                 timer@a0410600 {
 255                         compatible = "arm,cortex-a9-twd-timer";
 256                         reg = <0xa0410600 0x20>;
 257                         interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
 258
 259                         clocks = <&smp_twd_clk>;
 260                 };
 261
 262                 watchdog@a0410620 {
 263                         compatible = "arm,cortex-a9-twd-wdt";
 264                         reg = <0xa0410620 0x20>;
 265                         interrupts = <1 14 0x304>;
 266                         clocks = <&smp_twd_clk>;
 267                 };
 268
 269                 rtc@80154000 {
 270                         compatible = "arm,rtc-pl031", "arm,primecell";
 271                         reg = <0x80154000 0x1000>;
 272                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 273
 274                         clocks = <&rtc_clk>;
 275                         clock-names = "apb_pclk";
 276                 };
 277
 278                 gpio0: gpio@8012e000 {
 279                         compatible = "stericsson,db8500-gpio",
 280                                 "st,nomadik-gpio";
 281                         reg =  <0x8012e000 0x80>;
 282                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 283                         interrupt-controller;
 284                         #interrupt-cells = <2>;
 285                         st,supports-sleepmode;
 286                         gpio-controller;
 287                         #gpio-cells = <2>;
 288                         gpio-bank = <0>;
 289
 290                         clocks = <&prcc_pclk 1 9>;
 291                 };
 292
 293                 gpio1: gpio@8012e080 {
 294                         compatible = "stericsson,db8500-gpio",
 295                                 "st,nomadik-gpio";
 296                         reg =  <0x8012e080 0x80>;
 297                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 298                         interrupt-controller;
 299                         #interrupt-cells = <2>;
 300                         st,supports-sleepmode;
 301                         gpio-controller;
 302                         #gpio-cells = <2>;
 303                         gpio-bank = <1>;
 304
 305                         clocks = <&prcc_pclk 1 9>;
 306                 };
 307
 308                 gpio2: gpio@8000e000 {
 309                         compatible = "stericsson,db8500-gpio",
 310                                 "st,nomadik-gpio";
 311                         reg =  <0x8000e000 0x80>;
 312                         interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
 313                         interrupt-controller;
 314                         #interrupt-cells = <2>;
 315                         st,supports-sleepmode;
 316                         gpio-controller;
 317                         #gpio-cells = <2>;
 318                         gpio-bank = <2>;
 319
 320                         clocks = <&prcc_pclk 3 8>;
 321                 };
 322
 323                 gpio3: gpio@8000e080 {
 324                         compatible = "stericsson,db8500-gpio",
 325                                 "st,nomadik-gpio";
 326                         reg =  <0x8000e080 0x80>;
 327                         interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
 328                         interrupt-controller;
 329                         #interrupt-cells = <2>;
 330                         st,supports-sleepmode;
 331                         gpio-controller;
 332                         #gpio-cells = <2>;
 333                         gpio-bank = <3>;
 334
 335                         clocks = <&prcc_pclk 3 8>;
 336                 };
 337
 338                 gpio4: gpio@8000e100 {
 339                         compatible = "stericsson,db8500-gpio",
 340                                 "st,nomadik-gpio";
 341                         reg =  <0x8000e100 0x80>;
 342                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
 343                         interrupt-controller;
 344                         #interrupt-cells = <2>;
 345                         st,supports-sleepmode;
 346                         gpio-controller;
 347                         #gpio-cells = <2>;
 348                         gpio-bank = <4>;
 349
 350                         clocks = <&prcc_pclk 3 8>;
 351                 };
 352
 353                 gpio5: gpio@8000e180 {
 354                         compatible = "stericsson,db8500-gpio",
 355                                 "st,nomadik-gpio";
 356                         reg =  <0x8000e180 0x80>;
 357                         interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
 358                         interrupt-controller;
 359                         #interrupt-cells = <2>;
 360                         st,supports-sleepmode;
 361                         gpio-controller;
 362                         #gpio-cells = <2>;
 363                         gpio-bank = <5>;
 364
 365                         clocks = <&prcc_pclk 3 8>;
 366                 };
 367
 368                 gpio6: gpio@8011e000 {
 369                         compatible = "stericsson,db8500-gpio",
 370                                 "st,nomadik-gpio";
 371                         reg =  <0x8011e000 0x80>;
 372                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                         st,supports-sleepmode;
 376                         gpio-controller;
 377                         #gpio-cells = <2>;
 378                         gpio-bank = <6>;
 379
 380                         clocks = <&prcc_pclk 2 11>;
 381                 };
 382
 383                 gpio7: gpio@8011e080 {
 384                         compatible = "stericsson,db8500-gpio",
 385                                 "st,nomadik-gpio";
 386                         reg =  <0x8011e080 0x80>;
 387                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <2>;
 390                         st,supports-sleepmode;
 391                         gpio-controller;
 392                         #gpio-cells = <2>;
 393                         gpio-bank = <7>;
 394
 395                         clocks = <&prcc_pclk 2 11>;
 396                 };
 397
 398                 gpio8: gpio@a03fe000 {
 399                         compatible = "stericsson,db8500-gpio",
 400                                 "st,nomadik-gpio";
 401                         reg =  <0xa03fe000 0x80>;
 402                         interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
 403                         interrupt-controller;
 404                         #interrupt-cells = <2>;
 405                         st,supports-sleepmode;
 406                         gpio-controller;
 407                         #gpio-cells = <2>;
 408                         gpio-bank = <8>;
 409
 410                         clocks = <&prcc_pclk 5 1>;
 411                 };
 412
 413                 pinctrl {
 414                         compatible = "stericsson,db8500-pinctrl";
 415                         prcm = <&prcmu>;
 416                 };
 417
 418                 usb_per5@a03e0000 {
 419                         compatible = "stericsson,db8500-musb";
 420                         reg = <0xa03e0000 0x10000>;
 421                         interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 422                         interrupt-names = "mc";
 423
 424                         dr_mode = "otg";
 425
 426                         dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
 427                                <&dma 38 0 0x0>, /* Logical - MemToDev */
 428                                <&dma 37 0 0x2>, /* Logical - DevToMem */
 429                                <&dma 37 0 0x0>, /* Logical - MemToDev */
 430                                <&dma 36 0 0x2>, /* Logical - DevToMem */
 431                                <&dma 36 0 0x0>, /* Logical - MemToDev */
 432                                <&dma 19 0 0x2>, /* Logical - DevToMem */
 433                                <&dma 19 0 0x0>, /* Logical - MemToDev */
 434                                <&dma 18 0 0x2>, /* Logical - DevToMem */
 435                                <&dma 18 0 0x0>, /* Logical - MemToDev */
 436                                <&dma 17 0 0x2>, /* Logical - DevToMem */
 437                                <&dma 17 0 0x0>, /* Logical - MemToDev */
 438                                <&dma 16 0 0x2>, /* Logical - DevToMem */
 439                                <&dma 16 0 0x0>, /* Logical - MemToDev */
 440                                <&dma 39 0 0x2>, /* Logical - DevToMem */
 441                                <&dma 39 0 0x0>; /* Logical - MemToDev */
 442
 443                         dma-names = "iep_1_9",  "oep_1_9",
 444                                     "iep_2_10", "oep_2_10",
 445                                     "iep_3_11", "oep_3_11",
 446                                     "iep_4_12", "oep_4_12",
 447                                     "iep_5_13", "oep_5_13",
 448                                     "iep_6_14", "oep_6_14",
 449                                     "iep_7_15", "oep_7_15",
 450                                     "iep_8",    "oep_8";
 451
 452                         clocks = <&prcc_pclk 5 0>;
 453                 };
 454
 455                 dma: dma-controller@801C0000 {
 456                         compatible = "stericsson,db8500-dma40", "stericsson,dma40";
 457                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
 458                         reg-names = "base", "lcpa";
 459                         interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 460
 461                         #dma-cells = <3>;
 462                         memcpy-channels = <56 57 58 59 60>;
 463
 464                         clocks = <&prcmu_clk PRCMU_DMACLK>;
 465                 };
 466
 467                 prcmu: prcmu@80157000 {
 468                         compatible = "stericsson,db8500-prcmu";
 469                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
 470                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
 471                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 472                         #address-cells = <1>;
 473                         #size-cells = <1>;
 474                         interrupt-controller;
 475                         #interrupt-cells = <2>;
 476                         ranges;
 477
 478                         prcmu-timer-4@80157450 {
 479                                 compatible = "stericsson,db8500-prcmu-timer-4";
 480                                 reg = <0x80157450 0xC>;
 481                         };
 482
 483                         cpufreq {
 484                                 compatible = "stericsson,cpufreq-ux500";
 485                                 clocks = <&prcmu_clk PRCMU_ARMSS>;
 486                                 clock-names = "armss";
 487                                 status = "disabled";
 488                         };
 489
 490                         thermal@801573c0 {
 491                                 compatible = "stericsson,db8500-thermal";
 492                                 reg = <0x801573c0 0x40>;
 493                                 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
 494                                              <22 IRQ_TYPE_LEVEL_HIGH>;
 495                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
 496                                 status = "disabled";
 497                         };
 498
 499                         db8500-prcmu-regulators {
 500                                 compatible = "stericsson,db8500-prcmu-regulator";
 501
 502                                 // DB8500_REGULATOR_VAPE
 503                                 db8500_vape_reg: db8500_vape {
 504                                         regulator-compatible = "db8500_vape";
 505                                         regulator-always-on;
 506                                 };
 507
 508                                 // DB8500_REGULATOR_VARM
 509                                 db8500_varm_reg: db8500_varm {
 510                                         regulator-compatible = "db8500_varm";
 511                                 };
 512
 513                                 // DB8500_REGULATOR_VMODEM
 514                                 db8500_vmodem_reg: db8500_vmodem {
 515                                         regulator-compatible = "db8500_vmodem";
 516                                 };
 517
 518                                 // DB8500_REGULATOR_VPLL
 519                                 db8500_vpll_reg: db8500_vpll {
 520                                         regulator-compatible = "db8500_vpll";
 521                                 };
 522
 523                                 // DB8500_REGULATOR_VSMPS1
 524                                 db8500_vsmps1_reg: db8500_vsmps1 {
 525                                         regulator-compatible = "db8500_vsmps1";
 526                                 };
 527
 528                                 // DB8500_REGULATOR_VSMPS2
 529                                 db8500_vsmps2_reg: db8500_vsmps2 {
 530                                         regulator-compatible = "db8500_vsmps2";
 531                                 };
 532
 533                                 // DB8500_REGULATOR_VSMPS3
 534                                 db8500_vsmps3_reg: db8500_vsmps3 {
 535                                         regulator-compatible = "db8500_vsmps3";
 536                                 };
 537
 538                                 // DB8500_REGULATOR_VRF1
 539                                 db8500_vrf1_reg: db8500_vrf1 {
 540                                         regulator-compatible = "db8500_vrf1";
 541                                 };
 542
 543                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
 544                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
 545                                         regulator-compatible = "db8500_sva_mmdsp";
 546                                 };
 547
 548                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
 549                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
 550                                         regulator-compatible = "db8500_sva_mmdsp_ret";
 551                                 };
 552
 553                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
 554                                 db8500_sva_pipe_reg: db8500_sva_pipe {
 555                                         regulator-compatible = "db8500_sva_pipe";
 556                                 };
 557
 558                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
 559                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
 560                                         regulator-compatible = "db8500_sia_mmdsp";
 561                                 };
 562
 563                                 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
 564                                 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
 565                                 };
 566
 567                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
 568                                 db8500_sia_pipe_reg: db8500_sia_pipe {
 569                                         regulator-compatible = "db8500_sia_pipe";
 570                                 };
 571
 572                                 // DB8500_REGULATOR_SWITCH_SGA
 573                                 db8500_sga_reg: db8500_sga {
 574                                         regulator-compatible = "db8500_sga";
 575                                         vin-supply = <&db8500_vape_reg>;
 576                                 };
 577
 578                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
 579                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
 580                                         regulator-compatible = "db8500_b2r2_mcde";
 581                                         vin-supply = <&db8500_vape_reg>;
 582                                 };
 583
 584                                 // DB8500_REGULATOR_SWITCH_ESRAM12
 585                                 db8500_esram12_reg: db8500_esram12 {
 586                                         regulator-compatible = "db8500_esram12";
 587                                 };
 588
 589                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
 590                                 db8500_esram12_ret_reg: db8500_esram12_ret {
 591                                         regulator-compatible = "db8500_esram12_ret";
 592                                 };
 593
 594                                 // DB8500_REGULATOR_SWITCH_ESRAM34
 595                                 db8500_esram34_reg: db8500_esram34 {
 596                                         regulator-compatible = "db8500_esram34";
 597                                 };
 598
 599                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
 600                                 db8500_esram34_ret_reg: db8500_esram34_ret {
 601                                         regulator-compatible = "db8500_esram34_ret";
 602                                 };
 603                         };
 604
 605                         ab8500 {
 606                                 compatible = "stericsson,ab8500";
 607                                 interrupt-parent = <&intc>;
 608                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 609                                 interrupt-controller;
 610                                 #interrupt-cells = <2>;
 611
 612                                 ab8500_gpio: ab8500-gpio {
 613                                         gpio-controller;
 614                                         #gpio-cells = <2>;
 615                                 };
 616
 617                                 ab8500-rtc {
 618                                         compatible = "stericsson,ab8500-rtc";
 619                                         interrupts = <17 IRQ_TYPE_LEVEL_HIGH
 620                                                       18 IRQ_TYPE_LEVEL_HIGH>;
 621                                         interrupt-names = "60S", "ALARM";
 622                                 };
 623
 624                                 ab8500-gpadc {
 625                                         compatible = "stericsson,ab8500-gpadc";
 626                                         interrupts = <32 IRQ_TYPE_LEVEL_HIGH
 627                                                       39 IRQ_TYPE_LEVEL_HIGH>;
 628                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
 629                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
 630                                 };
 631
 632                                 ab8500_battery: ab8500_battery {
 633                                         stericsson,battery-type = "LIPO";
 634                                         thermistor-on-batctrl;
 635                                 };
 636
 637                                 ab8500_fg {
 638                                         compatible = "stericsson,ab8500-fg";
 639                                         battery    = <&ab8500_battery>;
 640                                 };
 641
 642                                 ab8500_btemp {
 643                                         compatible = "stericsson,ab8500-btemp";
 644                                         battery    = <&ab8500_battery>;
 645                                 };
 646
 647                                 ab8500_charger {
 648                                         compatible      = "stericsson,ab8500-charger";
 649                                         battery         = <&ab8500_battery>;
 650                                         vddadc-supply   = <&ab8500_ldo_tvout_reg>;
 651                                 };
 652
 653                                 ab8500_chargalg {
 654                                         compatible      = "stericsson,ab8500-chargalg";
 655                                         battery         = <&ab8500_battery>;
 656                                 };
 657
 658                                 ab8500_usb {
 659                                         compatible = "stericsson,ab8500-usb";
 660                                         interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
 661                                                        96 IRQ_TYPE_LEVEL_HIGH
 662                                                        14 IRQ_TYPE_LEVEL_HIGH
 663                                                        15 IRQ_TYPE_LEVEL_HIGH
 664                                                        79 IRQ_TYPE_LEVEL_HIGH
 665                                                        74 IRQ_TYPE_LEVEL_HIGH
 666                                                        75 IRQ_TYPE_LEVEL_HIGH>;
 667                                         interrupt-names = "ID_WAKEUP_R",
 668                                                           "ID_WAKEUP_F",
 669                                                           "VBUS_DET_F",
 670                                                           "VBUS_DET_R",
 671                                                           "USB_LINK_STATUS",
 672                                                           "USB_ADP_PROBE_PLUG",
 673                                                           "USB_ADP_PROBE_UNPLUG";
 674                                         vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
 675                                         v-ape-supply = <&db8500_vape_reg>;
 676                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
 677                                 };
 678
 679                                 ab8500-ponkey {
 680                                         compatible = "stericsson,ab8500-poweron-key";
 681                                         interrupts = <6 IRQ_TYPE_LEVEL_HIGH
 682                                                       7 IRQ_TYPE_LEVEL_HIGH>;
 683                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
 684                                 };
 685
 686                                 ab8500-sysctrl {
 687                                         compatible = "stericsson,ab8500-sysctrl";
 688                                 };
 689
 690                                 ab8500-pwm {
 691                                         compatible = "stericsson,ab8500-pwm";
 692                                 };
 693
 694                                 ab8500-debugfs {
 695                                         compatible = "stericsson,ab8500-debug";
 696                                 };
 697
 698                                 codec: ab8500-codec {
 699                                         compatible = "stericsson,ab8500-codec";
 700
 701                                         V-AUD-supply = <&ab8500_ldo_audio_reg>;
 702                                         V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
 703                                         V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
 704                                         V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
 705
 706                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
 707                                 };
 708
 709                                 ext_regulators: ab8500-ext-regulators {
 710                                         compatible = "stericsson,ab8500-ext-regulator";
 711
 712                                         ab8500_ext1_reg: ab8500_ext1 {
 713                                                 regulator-compatible = "ab8500_ext1";
 714                                                 regulator-min-microvolt = <1800000>;
 715                                                 regulator-max-microvolt = <1800000>;
 716                                                 regulator-boot-on;
 717                                                 regulator-always-on;
 718                                         };
 719
 720                                         ab8500_ext2_reg: ab8500_ext2 {
 721                                                 regulator-compatible = "ab8500_ext2";
 722                                                 regulator-min-microvolt = <1360000>;
 723                                                 regulator-max-microvolt = <1360000>;
 724                                                 regulator-boot-on;
 725                                                 regulator-always-on;
 726                                         };
 727
 728                                         ab8500_ext3_reg: ab8500_ext3 {
 729                                                 regulator-compatible = "ab8500_ext3";
 730                                                 regulator-min-microvolt = <3400000>;
 731                                                 regulator-max-microvolt = <3400000>;
 732                                                 regulator-boot-on;
 733                                         };
 734                                 };
 735
 736                                 ab8500-regulators {
 737                                         compatible = "stericsson,ab8500-regulator";
 738                                         vin-supply = <&ab8500_ext3_reg>;
 739
 740                                         // supplies to the display/camera
 741                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
 742                                                 regulator-compatible = "ab8500_ldo_aux1";
 743                                                 regulator-min-microvolt = <2500000>;
 744                                                 regulator-max-microvolt = <2900000>;
 745                                                 regulator-boot-on;
 746                                                 /* BUG: If turned off MMC will be affected. */
 747                                                 regulator-always-on;
 748                                         };
 749
 750                                         // supplies to the on-board eMMC
 751                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
 752                                                 regulator-compatible = "ab8500_ldo_aux2";
 753                                                 regulator-min-microvolt = <1100000>;
 754                                                 regulator-max-microvolt = <3300000>;
 755                                         };
 756
 757                                         // supply for VAUX3; SDcard slots
 758                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
 759                                                 regulator-compatible = "ab8500_ldo_aux3";
 760                                                 regulator-min-microvolt = <1100000>;
 761                                                 regulator-max-microvolt = <3300000>;
 762                                         };
 763
 764                                         // supply for v-intcore12; VINTCORE12 LDO
 765                                         ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
 766                                                 regulator-compatible = "ab8500_ldo_intcore";
 767                                         };
 768
 769                                         // supply for tvout; gpadc; TVOUT LDO
 770                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
 771                                                 regulator-compatible = "ab8500_ldo_tvout";
 772                                         };
 773
 774                                         // supply for ab8500-usb; USB LDO
 775                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
 776                                                 regulator-compatible = "ab8500_ldo_usb";
 777                                         };
 778
 779                                         // supply for ab8500-vaudio; VAUDIO LDO
 780                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
 781                                                 regulator-compatible = "ab8500_ldo_audio";
 782                                         };
 783
 784                                         // supply for v-anamic1 VAMIC1 LDO
 785                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
 786                                                 regulator-compatible = "ab8500_ldo_anamic1";
 787                                         };
 788
 789                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
 790                                         ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
 791                                                 regulator-compatible = "ab8500_ldo_anamic2";
 792                                         };
 793
 794                                         // supply for v-dmic; VDMIC LDO
 795                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
 796                                                 regulator-compatible = "ab8500_ldo_dmic";
 797                                         };
 798
 799                                         // supply for U8500 CSI/DSI; VANA LDO
 800                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
 801                                                 regulator-compatible = "ab8500_ldo_ana";
 802                                         };
 803                                 };
 804                         };
 805                 };
 806
 807                 i2c@80004000 {
 808                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 809                         reg = <0x80004000 0x1000>;
 810                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 811
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814                         v-i2c-supply = <&db8500_vape_reg>;
 815
 816                         clock-frequency = <400000>;
 817                         clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
 818                         clock-names = "i2cclk", "apb_pclk";
 819                         power-domains = <&pm_domains DOMAIN_VAPE>;
 820                 };
 821
 822                 i2c@80122000 {
 823                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 824                         reg = <0x80122000 0x1000>;
 825                         interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 826
 827                         #address-cells = <1>;
 828                         #size-cells = <0>;
 829                         v-i2c-supply = <&db8500_vape_reg>;
 830
 831                         clock-frequency = <400000>;
 832
 833                         clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
 834                         clock-names = "i2cclk", "apb_pclk";
 835                         power-domains = <&pm_domains DOMAIN_VAPE>;
 836                 };
 837
 838                 i2c@80128000 {
 839                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 840                         reg = <0x80128000 0x1000>;
 841                         interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 842
 843                         #address-cells = <1>;
 844                         #size-cells = <0>;
 845                         v-i2c-supply = <&db8500_vape_reg>;
 846
 847                         clock-frequency = <400000>;
 848
 849                         clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
 850                         clock-names = "i2cclk", "apb_pclk";
 851                         power-domains = <&pm_domains DOMAIN_VAPE>;
 852                 };
 853
 854                 i2c@80110000 {
 855                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 856                         reg = <0x80110000 0x1000>;
 857                         interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
 858
 859                         #address-cells = <1>;
 860                         #size-cells = <0>;
 861                         v-i2c-supply = <&db8500_vape_reg>;
 862
 863                         clock-frequency = <400000>;
 864
 865                         clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
 866                         clock-names = "i2cclk", "apb_pclk";
 867                         power-domains = <&pm_domains DOMAIN_VAPE>;
 868                 };
 869
 870                 i2c@8012a000 {
 871                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
 872                         reg = <0x8012a000 0x1000>;
 873                         interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
 874
 875                         #address-cells = <1>;
 876                         #size-cells = <0>;
 877                         v-i2c-supply = <&db8500_vape_reg>;
 878
 879                         clock-frequency = <400000>;
 880
 881                         clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
 882                         clock-names = "i2cclk", "apb_pclk";
 883                         power-domains = <&pm_domains DOMAIN_VAPE>;
 884                 };
 885
 886                 ssp@80002000 {
 887                         compatible = "arm,pl022", "arm,primecell";
 888                         reg = <0x80002000 0x1000>;
 889                         interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 890                         #address-cells = <1>;
 891                         #size-cells = <0>;
 892                         clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
 893                         clock-names = "SSPCLK", "apb_pclk";
 894                         dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
 895                                <&dma 8 0 0x0>; /* Logical - MemToDev */
 896                         dma-names = "rx", "tx";
 897                         power-domains = <&pm_domains DOMAIN_VAPE>;
 898                 };
 899
 900                 ssp@80003000 {
 901                         compatible = "arm,pl022", "arm,primecell";
 902                         reg = <0x80003000 0x1000>;
 903                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 904                         #address-cells = <1>;
 905                         #size-cells = <0>;
 906                         clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
 907                         clock-names = "SSPCLK", "apb_pclk";
 908                         dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
 909                                <&dma 9 0 0x0>; /* Logical - MemToDev */
 910                         dma-names = "rx", "tx";
 911                         power-domains = <&pm_domains DOMAIN_VAPE>;
 912                 };
 913
 914                 spi@8011a000 {
 915                         compatible = "arm,pl022", "arm,primecell";
 916                         reg = <0x8011a000 0x1000>;
 917                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 918                         #address-cells = <1>;
 919                         #size-cells = <0>;
 920                         /* Same clock wired to kernel and pclk */
 921                         clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
 922                         clock-names = "SSPCLK", "apb_pclk";
 923                         dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
 924                                <&dma 0 0 0x0>; /* Logical - MemToDev */
 925                         dma-names = "rx", "tx";
 926                         power-domains = <&pm_domains DOMAIN_VAPE>;
 927                 };
 928
 929                 spi@80112000 {
 930                         compatible = "arm,pl022", "arm,primecell";
 931                         reg = <0x80112000 0x1000>;
 932                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 933                         #address-cells = <1>;
 934                         #size-cells = <0>;
 935                         /* Same clock wired to kernel and pclk */
 936                         clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
 937                         clock-names = "SSPCLK", "apb_pclk";
 938                         dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
 939                                <&dma 35 0 0x0>; /* Logical - MemToDev */
 940                         dma-names = "rx", "tx";
 941                         power-domains = <&pm_domains DOMAIN_VAPE>;
 942                 };
 943
 944                 spi@80111000 {
 945                         compatible = "arm,pl022", "arm,primecell";
 946                         reg = <0x80111000 0x1000>;
 947                         interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 948                         #address-cells = <1>;
 949                         #size-cells = <0>;
 950                         /* Same clock wired to kernel and pclk */
 951                         clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
 952                         clock-names = "SSPCLK", "apb_pclk";
 953                         dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
 954                                <&dma 33 0 0x0>; /* Logical - MemToDev */
 955                         dma-names = "rx", "tx";
 956                         power-domains = <&pm_domains DOMAIN_VAPE>;
 957                 };
 958
 959                 spi@80129000 {
 960                         compatible = "arm,pl022", "arm,primecell";
 961                         reg = <0x80129000 0x1000>;
 962                         interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
 963                         #address-cells = <1>;
 964                         #size-cells = <0>;
 965                         /* Same clock wired to kernel and pclk */
 966                         clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
 967                         clock-names = "SSPCLK", "apb_pclk";
 968                         dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
 969                                <&dma 40 0 0x0>; /* Logical - MemToDev */
 970                         dma-names = "rx", "tx";
 971                         power-domains = <&pm_domains DOMAIN_VAPE>;
 972                 };
 973
 974                 ux500_serial0: uart@80120000 {
 975                         compatible = "arm,pl011", "arm,primecell";
 976                         reg = <0x80120000 0x1000>;
 977                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 978
 979                         dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
 980                                <&dma 13 0 0x0>; /* Logical - MemToDev */
 981                         dma-names = "rx", "tx";
 982
 983                         clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
 984                         clock-names = "uart", "apb_pclk";
 985
 986                         status = "disabled";
 987                 };
 988
 989                 ux500_serial1: uart@80121000 {
 990                         compatible = "arm,pl011", "arm,primecell";
 991                         reg = <0x80121000 0x1000>;
 992                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 993
 994                         dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
 995                                <&dma 12 0 0x0>; /* Logical - MemToDev */
 996                         dma-names = "rx", "tx";
 997
 998                         clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
 999                         clock-names = "uart", "apb_pclk";
1000
1001                         status = "disabled";
1002                 };
1003
1004                 ux500_serial2: uart@80007000 {
1005                         compatible = "arm,pl011", "arm,primecell";
1006                         reg = <0x80007000 0x1000>;
1007                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
1008
1009                         dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1010                                <&dma 11 0 0x0>; /* Logical - MemToDev */
1011                         dma-names = "rx", "tx";
1012
1013                         clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1014                         clock-names = "uart", "apb_pclk";
1015
1016                         status = "disabled";
1017                 };
1018
1019                 sdi0_per1@80126000 {
1020                         compatible = "arm,pl18x", "arm,primecell";
1021                         reg = <0x80126000 0x1000>;
1022                         interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
1023
1024                         dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1025                                <&dma 29 0 0x0>; /* Logical - MemToDev */
1026                         dma-names = "rx", "tx";
1027
1028                         clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1029                         clock-names = "sdi", "apb_pclk";
1030                         power-domains = <&pm_domains DOMAIN_VAPE>;
1031
1032                         status = "disabled";
1033                 };
1034
1035                 sdi1_per2@80118000 {
1036                         compatible = "arm,pl18x", "arm,primecell";
1037                         reg = <0x80118000 0x1000>;
1038                         interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
1039
1040                         dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1041                                <&dma 32 0 0x0>; /* Logical - MemToDev */
1042                         dma-names = "rx", "tx";
1043
1044                         clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1045                         clock-names = "sdi", "apb_pclk";
1046                         power-domains = <&pm_domains DOMAIN_VAPE>;
1047
1048                         status = "disabled";
1049                 };
1050
1051                 sdi2_per3@80005000 {
1052                         compatible = "arm,pl18x", "arm,primecell";
1053                         reg = <0x80005000 0x1000>;
1054                         interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1055
1056                         dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1057                                <&dma 28 0 0x0>; /* Logical - MemToDev */
1058                         dma-names = "rx", "tx";
1059
1060                         clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1061                         clock-names = "sdi", "apb_pclk";
1062                         power-domains = <&pm_domains DOMAIN_VAPE>;
1063
1064                         status = "disabled";
1065                 };
1066
1067                 sdi3_per2@80119000 {
1068                         compatible = "arm,pl18x", "arm,primecell";
1069                         reg = <0x80119000 0x1000>;
1070                         interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
1071
1072                         dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1073                                <&dma 41 0 0x0>; /* Logical - MemToDev */
1074                         dma-names = "rx", "tx";
1075
1076                         clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1077                         clock-names = "sdi", "apb_pclk";
1078                         power-domains = <&pm_domains DOMAIN_VAPE>;
1079
1080                         status = "disabled";
1081                 };
1082
1083                 sdi4_per2@80114000 {
1084                         compatible = "arm,pl18x", "arm,primecell";
1085                         reg = <0x80114000 0x1000>;
1086                         interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1087
1088                         dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1089                                <&dma 42 0 0x0>; /* Logical - MemToDev */
1090                         dma-names = "rx", "tx";
1091
1092                         clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1093                         clock-names = "sdi", "apb_pclk";
1094                         power-domains = <&pm_domains DOMAIN_VAPE>;
1095
1096                         status = "disabled";
1097                 };
1098
1099                 sdi5_per3@80008000 {
1100                         compatible = "arm,pl18x", "arm,primecell";
1101                         reg = <0x80008000 0x1000>;
1102                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
1103
1104                         dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1105                                <&dma 43 0 0x0>; /* Logical - MemToDev */
1106                         dma-names = "rx", "tx";
1107
1108                         clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1109                         clock-names = "sdi", "apb_pclk";
1110                         power-domains = <&pm_domains DOMAIN_VAPE>;
1111
1112                         status = "disabled";
1113                 };
1114
1115                 msp0: msp@80123000 {
1116                         compatible = "stericsson,ux500-msp-i2s";
1117                         reg = <0x80123000 0x1000>;
1118                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
1119                         v-ape-supply = <&db8500_vape_reg>;
1120
1121                         dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1122                                <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1123                         dma-names = "rx", "tx";
1124
1125                         clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1126                         clock-names = "msp", "apb_pclk";
1127
1128                         status = "disabled";
1129                 };
1130
1131                 msp1: msp@80124000 {
1132                         compatible = "stericsson,ux500-msp-i2s";
1133                         reg = <0x80124000 0x1000>;
1134                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1135                         v-ape-supply = <&db8500_vape_reg>;
1136
1137                         /* This DMA channel only exist on DB8500 v1 */
1138                         dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1139                         dma-names = "tx";
1140
1141                         clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1142                         clock-names = "msp", "apb_pclk";
1143
1144                         status = "disabled";
1145                 };
1146
1147                 // HDMI sound
1148                 msp2: msp@80117000 {
1149                         compatible = "stericsson,ux500-msp-i2s";
1150                         reg = <0x80117000 0x1000>;
1151                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1152                         v-ape-supply = <&db8500_vape_reg>;
1153
1154                         dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
1155                                <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1156                                                     HighPrio - Fixed */
1157                         dma-names = "rx", "tx";
1158
1159                         clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1160                         clock-names = "msp", "apb_pclk";
1161
1162                         status = "disabled";
1163                 };
1164
1165                 msp3: msp@80125000 {
1166                         compatible = "stericsson,ux500-msp-i2s";
1167                         reg = <0x80125000 0x1000>;
1168                         interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
1169                         v-ape-supply = <&db8500_vape_reg>;
1170
1171                         /* This DMA channel only exist on DB8500 v2 */
1172                         dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1173                         dma-names = "rx";
1174
1175                         clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1176                         clock-names = "msp", "apb_pclk";
1177
1178                         status = "disabled";
1179                 };
1180
1181                 external-bus@50000000 {
1182                         compatible = "simple-bus";
1183                         reg = <0x50000000 0x4000000>;
1184                         #address-cells = <1>;
1185                         #size-cells = <1>;
1186                         ranges = <0 0x50000000 0x4000000>;
1187                         status = "disabled";
1188                 };
1189
1190                 cpufreq-cooling {
1191                         compatible = "stericsson,db8500-cpufreq-cooling";
1192                         status = "disabled";
1193                 };
1194
1195                 mcde@a0350000 {
1196                         compatible = "stericsson,mcde";
1197                         reg = <0xa0350000 0x1000>, /* MCDE */
1198                               <0xa0351000 0x1000>, /* DSI link 1 */
1199                               <0xa0352000 0x1000>, /* DSI link 2 */
1200                               <0xa0353000 0x1000>; /* DSI link 3 */
1201                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1202                         clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1203                                  <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1204                                  <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1205                                  <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1206                                  <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1207                                  <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1208                                  <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1209                                  <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1210                 };
1211
1212                 cryp@a03cb000 {
1213                         compatible = "stericsson,ux500-cryp";
1214                         reg = <0xa03cb000 0x1000>;
1215                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
1216
1217                         v-ape-supply = <&db8500_vape_reg>;
1218                         clocks = <&prcc_pclk 6 1>;
1219                 };
1220
1221                 hash@a03c2000 {
1222                         compatible = "stericsson,ux500-hash";
1223                         reg = <0xa03c2000 0x1000>;
1224
1225                         v-ape-supply = <&db8500_vape_reg>;
1226                         clocks = <&prcc_pclk 6 2>;
1227                 };
1228         };
1229 };