arch/arm/boot/dts/spear1310.dtsi

   1 /*
   2  * DTS file for all SPEAr1310 SoCs
   3  *
   4  * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "spear13xx.dtsi"
  15
  16 / {
  17         compatible = "st,spear1310";
  18
  19         ahb {
  20                 spics: spics@e0700000{
  21                         compatible = "st,spear-spics-gpio";
  22                         reg = <0xe0700000 0x1000>;
  23                         st-spics,peripcfg-reg = <0x3b0>;
  24                         st-spics,sw-enable-bit = <12>;
  25                         st-spics,cs-value-bit = <11>;
  26                         st-spics,cs-enable-mask = <3>;
  27                         st-spics,cs-enable-shift = <8>;
  28                         gpio-controller;
  29                         #gpio-cells = <2>;
  30                 };
  31
  32                 miphy0: miphy@eb800000 {
  33                         compatible = "st,spear1310-miphy";
  34                         reg = <0xeb800000 0x4000>;
  35                         misc = <&misc>;
  36                         phy-id = <0>;
  37                         #phy-cells = <1>;
  38                         status = "disabled";
  39                 };
  40
  41                 miphy1: miphy@eb804000 {
  42                         compatible = "st,spear1310-miphy";
  43                         reg = <0xeb804000 0x4000>;
  44                         misc = <&misc>;
  45                         phy-id = <1>;
  46                         #phy-cells = <1>;
  47                         status = "disabled";
  48                 };
  49
  50                 miphy2: miphy@eb808000 {
  51                         compatible = "st,spear1310-miphy";
  52                         reg = <0xeb808000 0x4000>;
  53                         misc = <&misc>;
  54                         phy-id = <2>;
  55                         #phy-cells = <1>;
  56                         status = "disabled";
  57                 };
  58
  59                 ahci0: ahci@b1000000 {
  60                         compatible = "snps,spear-ahci";
  61                         reg = <0xb1000000 0x10000>;
  62                         interrupts = <0 68 0x4>;
  63                         phys = <&miphy0 0>;
  64                         phy-names = "sata-phy";
  65                         status = "disabled";
  66                 };
  67
  68                 ahci1: ahci@b1800000 {
  69                         compatible = "snps,spear-ahci";
  70                         reg = <0xb1800000 0x10000>;
  71                         interrupts = <0 69 0x4>;
  72                         phys = <&miphy1 0>;
  73                         phy-names = "sata-phy";
  74                         status = "disabled";
  75                 };
  76
  77                 ahci2: ahci@b4000000 {
  78                         compatible = "snps,spear-ahci";
  79                         reg = <0xb4000000 0x10000>;
  80                         interrupts = <0 70 0x4>;
  81                         phys = <&miphy2 0>;
  82                         phy-names = "sata-phy";
  83                         status = "disabled";
  84                 };
  85
  86                 pcie0: pcie@b1000000 {
  87                         compatible = "st,spear1340-pcie", "snps,dw-pcie";
  88                         reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
  89                         reg-names = "dbi", "config";
  90                         interrupts = <0 68 0x4>;
  91                         interrupt-map-mask = <0 0 0 0>;
  92                         interrupt-map = <0x0 0 &gic 0 68 0x4>;
  93                         num-lanes = <1>;
  94                         phys = <&miphy0 1>;
  95                         phy-names = "pcie-phy";
  96                         #address-cells = <3>;
  97                         #size-cells = <2>;
  98                         device_type = "pci";
  99                         ranges = <0x81000000 0 0         0x80020000 0 0x00010000   /* downstream I/O */
 100                                 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
 101                         status = "disabled";
 102                 };
 103
 104                 pcie1: pcie@b1800000 {
 105                         compatible = "st,spear1340-pcie", "snps,dw-pcie";
 106                         reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
 107                         reg-names = "dbi", "config";
 108                         interrupts = <0 69 0x4>;
 109                         interrupt-map-mask = <0 0 0 0>;
 110                         interrupt-map = <0x0 0 &gic 0 69 0x4>;
 111                         num-lanes = <1>;
 112                         phys = <&miphy1 1>;
 113                         phy-names = "pcie-phy";
 114                         #address-cells = <3>;
 115                         #size-cells = <2>;
 116                         device_type = "pci";
 117                         ranges = <0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
 118                                 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
 119                         status = "disabled";
 120                 };
 121
 122                 pcie2: pcie@b4000000 {
 123                         compatible = "st,spear1340-pcie", "snps,dw-pcie";
 124                         reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
 125                         reg-names = "dbi", "config";
 126                         interrupts = <0 70 0x4>;
 127                         interrupt-map-mask = <0 0 0 0>;
 128                         interrupt-map = <0x0 0 &gic 0 70 0x4>;
 129                         num-lanes = <1>;
 130                         phys = <&miphy2 1>;
 131                         phy-names = "pcie-phy";
 132                         #address-cells = <3>;
 133                         #size-cells = <2>;
 134                         device_type = "pci";
 135                         ranges = <0x81000000 0 0         0xc0020000 0 0x00010000   /* downstream I/O */
 136                                 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
 137                         status = "disabled";
 138                 };
 139
 140                 gmac1: eth@5c400000 {
 141                         compatible = "st,spear600-gmac";
 142                         reg = <0x5c400000 0x8000>;
 143                         interrupts = <0 95 0x4>;
 144                         interrupt-names = "macirq";
 145                         phy-mode = "mii";
 146                         status = "disabled";
 147                 };
 148
 149                 gmac2: eth@5c500000 {
 150                         compatible = "st,spear600-gmac";
 151                         reg = <0x5c500000 0x8000>;
 152                         interrupts = <0 96 0x4>;
 153                         interrupt-names = "macirq";
 154                         phy-mode = "mii";
 155                         status = "disabled";
 156                 };
 157
 158                 gmac3: eth@5c600000 {
 159                         compatible = "st,spear600-gmac";
 160                         reg = <0x5c600000 0x8000>;
 161                         interrupts = <0 97 0x4>;
 162                         interrupt-names = "macirq";
 163                         phy-mode = "rmii";
 164                         status = "disabled";
 165                 };
 166
 167                 gmac4: eth@5c700000 {
 168                         compatible = "st,spear600-gmac";
 169                         reg = <0x5c700000 0x8000>;
 170                         interrupts = <0 98 0x4>;
 171                         interrupt-names = "macirq";
 172                         phy-mode = "rgmii";
 173                         status = "disabled";
 174                 };
 175
 176                 pinmux: pinmux@e0700000 {
 177                         compatible = "st,spear1310-pinmux";
 178                         reg = <0xe0700000 0x1000>;
 179                         #gpio-range-cells = <3>;
 180                 };
 181
 182                 apb {
 183                         i2c1: i2c@5cd00000 {
 184                                 #address-cells = <1>;
 185                                 #size-cells = <0>;
 186                                 compatible = "snps,designware-i2c";
 187                                 reg = <0x5cd00000 0x1000>;
 188                                 interrupts = <0 87 0x4>;
 189                                 status = "disabled";
 190                         };
 191
 192                         i2c2: i2c@5ce00000 {
 193                                 #address-cells = <1>;
 194                                 #size-cells = <0>;
 195                                 compatible = "snps,designware-i2c";
 196                                 reg = <0x5ce00000 0x1000>;
 197                                 interrupts = <0 88 0x4>;
 198                                 status = "disabled";
 199                         };
 200
 201                         i2c3: i2c@5cf00000 {
 202                                 #address-cells = <1>;
 203                                 #size-cells = <0>;
 204                                 compatible = "snps,designware-i2c";
 205                                 reg = <0x5cf00000 0x1000>;
 206                                 interrupts = <0 89 0x4>;
 207                                 status = "disabled";
 208                         };
 209
 210                         i2c4: i2c@5d000000 {
 211                                 #address-cells = <1>;
 212                                 #size-cells = <0>;
 213                                 compatible = "snps,designware-i2c";
 214                                 reg = <0x5d000000 0x1000>;
 215                                 interrupts = <0 90 0x4>;
 216                                 status = "disabled";
 217                         };
 218
 219                         i2c5: i2c@5d100000 {
 220                                 #address-cells = <1>;
 221                                 #size-cells = <0>;
 222                                 compatible = "snps,designware-i2c";
 223                                 reg = <0x5d100000 0x1000>;
 224                                 interrupts = <0 91 0x4>;
 225                                 status = "disabled";
 226                         };
 227
 228                         i2c6: i2c@5d200000 {
 229                                 #address-cells = <1>;
 230                                 #size-cells = <0>;
 231                                 compatible = "snps,designware-i2c";
 232                                 reg = <0x5d200000 0x1000>;
 233                                 interrupts = <0 92 0x4>;
 234                                 status = "disabled";
 235                         };
 236
 237                         i2c7: i2c@5d300000 {
 238                                 #address-cells = <1>;
 239                                 #size-cells = <0>;
 240                                 compatible = "snps,designware-i2c";
 241                                 reg = <0x5d300000 0x1000>;
 242                                 interrupts = <0 93 0x4>;
 243                                 status = "disabled";
 244                         };
 245
 246                         spi1: spi@5d400000 {
 247                                 compatible = "arm,pl022", "arm,primecell";
 248                                 reg = <0x5d400000 0x1000>;
 249                                 interrupts = <0 99 0x4>;
 250                                 #address-cells = <1>;
 251                                 #size-cells = <0>;
 252                                 status = "disabled";
 253                         };
 254
 255                         serial@5c800000 {
 256                                 compatible = "arm,pl011", "arm,primecell";
 257                                 reg = <0x5c800000 0x1000>;
 258                                 interrupts = <0 82 0x4>;
 259                                 status = "disabled";
 260                         };
 261
 262                         serial@5c900000 {
 263                                 compatible = "arm,pl011", "arm,primecell";
 264                                 reg = <0x5c900000 0x1000>;
 265                                 interrupts = <0 83 0x4>;
 266                                 status = "disabled";
 267                         };
 268
 269                         serial@5ca00000 {
 270                                 compatible = "arm,pl011", "arm,primecell";
 271                                 reg = <0x5ca00000 0x1000>;
 272                                 interrupts = <0 84 0x4>;
 273                                 status = "disabled";
 274                         };
 275
 276                         serial@5cb00000 {
 277                                 compatible = "arm,pl011", "arm,primecell";
 278                                 reg = <0x5cb00000 0x1000>;
 279                                 interrupts = <0 85 0x4>;
 280                                 status = "disabled";
 281                         };
 282
 283                         serial@5cc00000 {
 284                                 compatible = "arm,pl011", "arm,primecell";
 285                                 reg = <0x5cc00000 0x1000>;
 286                                 interrupts = <0 86 0x4>;
 287                                 status = "disabled";
 288                         };
 289
 290                         thermal@e07008c4 {
 291                                 st,thermal-flags = <0x7000>;
 292                         };
 293
 294                         gpiopinctrl: gpio@d8400000 {
 295                                 compatible = "st,spear-plgpio";
 296                                 reg = <0xd8400000 0x1000>;
 297                                 interrupts = <0 100 0x4>;
 298                                 #interrupt-cells = <1>;
 299                                 interrupt-controller;
 300                                 gpio-controller;
 301                                 #gpio-cells = <2>;
 302                                 gpio-ranges = <&pinmux 0 0 246>;
 303                                 status = "disabled";
 304
 305                                 st-plgpio,ngpio = <246>;
 306                                 st-plgpio,enb-reg = <0xd0>;
 307                                 st-plgpio,wdata-reg = <0x90>;
 308                                 st-plgpio,dir-reg = <0xb0>;
 309                                 st-plgpio,ie-reg = <0x30>;
 310                                 st-plgpio,rdata-reg = <0x70>;
 311                                 st-plgpio,mis-reg = <0x10>;
 312                                 st-plgpio,eit-reg = <0x50>;
 313                         };
 314                 };
 315         };
 316 };