2 * Copyright (C) 2012 Altera <www.altera.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 /include/ "skeleton.dtsi"
40 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
46 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
57 reg = <0xfffed000 0x1000>,
64 compatible = "simple-bus";
66 interrupt-parent = <&intc>;
70 compatible = "arm,amba-bus";
76 compatible = "arm,pl330", "arm,primecell";
77 reg = <0xffe01000 0x1000>;
78 interrupts = <0 180 4>;
86 compatible = "altr,clk-mgr";
87 reg = <0xffd04000 0x1000>;
95 compatible = "fixed-clock";
98 f2s_periph_ref_clk: f2s_periph_ref_clk {
100 compatible = "fixed-clock";
101 clock-frequency = <10000000>;
105 #address-cells = <1>;
108 compatible = "altr,socfpga-pll-clock";
114 compatible = "altr,socfpga-perip-clk";
115 clocks = <&main_pll>;
122 compatible = "altr,socfpga-perip-clk";
123 clocks = <&main_pll>;
128 dbg_base_clk: dbg_base_clk {
130 compatible = "altr,socfpga-perip-clk";
131 clocks = <&main_pll>;
136 main_qspi_clk: main_qspi_clk {
138 compatible = "altr,socfpga-perip-clk";
139 clocks = <&main_pll>;
143 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
145 compatible = "altr,socfpga-perip-clk";
146 clocks = <&main_pll>;
150 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
152 compatible = "altr,socfpga-perip-clk";
153 clocks = <&main_pll>;
158 periph_pll: periph_pll {
159 #address-cells = <1>;
162 compatible = "altr,socfpga-pll-clock";
166 emac0_clk: emac0_clk {
168 compatible = "altr,socfpga-perip-clk";
169 clocks = <&periph_pll>;
173 emac1_clk: emac1_clk {
175 compatible = "altr,socfpga-perip-clk";
176 clocks = <&periph_pll>;
180 per_qspi_clk: per_qsi_clk {
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&periph_pll>;
187 per_nand_mmc_clk: per_nand_mmc_clk {
189 compatible = "altr,socfpga-perip-clk";
190 clocks = <&periph_pll>;
194 per_base_clk: per_base_clk {
196 compatible = "altr,socfpga-perip-clk";
197 clocks = <&periph_pll>;
201 h2f_usr1_clk: h2f_usr1_clk {
203 compatible = "altr,socfpga-perip-clk";
204 clocks = <&periph_pll>;
209 sdram_pll: sdram_pll {
210 #address-cells = <1>;
213 compatible = "altr,socfpga-pll-clock";
217 ddr_dqs_clk: ddr_dqs_clk {
219 compatible = "altr,socfpga-perip-clk";
220 clocks = <&sdram_pll>;
224 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
226 compatible = "altr,socfpga-perip-clk";
227 clocks = <&sdram_pll>;
231 ddr_dq_clk: ddr_dq_clk {
233 compatible = "altr,socfpga-perip-clk";
234 clocks = <&sdram_pll>;
238 h2f_usr2_clk: h2f_usr2_clk {
240 compatible = "altr,socfpga-perip-clk";
241 clocks = <&sdram_pll>;
246 mpu_periph_clk: mpu_periph_clk {
248 compatible = "altr,socfpga-perip-clk";
253 mpu_l2_ram_clk: mpu_l2_ram_clk {
255 compatible = "altr,socfpga-perip-clk";
260 l4_main_clk: l4_main_clk {
262 compatible = "altr,socfpga-gate-clk";
267 l3_main_clk: l3_main_clk {
269 compatible = "altr,socfpga-perip-clk";
274 l3_mp_clk: l3_mp_clk {
276 compatible = "altr,socfpga-gate-clk";
278 div-reg = <0x64 0 2>;
282 l3_sp_clk: l3_sp_clk {
284 compatible = "altr,socfpga-gate-clk";
286 div-reg = <0x64 2 2>;
289 l4_mp_clk: l4_mp_clk {
291 compatible = "altr,socfpga-gate-clk";
292 clocks = <&mainclk>, <&per_base_clk>;
293 div-reg = <0x64 4 3>;
297 l4_sp_clk: l4_sp_clk {
299 compatible = "altr,socfpga-gate-clk";
300 clocks = <&mainclk>, <&per_base_clk>;
301 div-reg = <0x64 7 3>;
305 dbg_at_clk: dbg_at_clk {
307 compatible = "altr,socfpga-gate-clk";
308 clocks = <&dbg_base_clk>;
309 div-reg = <0x68 0 2>;
315 compatible = "altr,socfpga-gate-clk";
316 clocks = <&dbg_base_clk>;
317 div-reg = <0x68 2 2>;
321 dbg_trace_clk: dbg_trace_clk {
323 compatible = "altr,socfpga-gate-clk";
324 clocks = <&dbg_base_clk>;
325 div-reg = <0x6C 0 3>;
329 dbg_timer_clk: dbg_timer_clk {
331 compatible = "altr,socfpga-gate-clk";
332 clocks = <&dbg_base_clk>;
338 compatible = "altr,socfpga-gate-clk";
339 clocks = <&cfg_h2f_usr0_clk>;
343 h2f_user0_clk: h2f_user0_clk {
345 compatible = "altr,socfpga-gate-clk";
346 clocks = <&cfg_h2f_usr0_clk>;
350 emac_0_clk: emac_0_clk {
352 compatible = "altr,socfpga-gate-clk";
353 clocks = <&emac0_clk>;
357 emac_1_clk: emac_1_clk {
359 compatible = "altr,socfpga-gate-clk";
360 clocks = <&emac1_clk>;
364 usb_mp_clk: usb_mp_clk {
366 compatible = "altr,socfpga-gate-clk";
367 clocks = <&per_base_clk>;
369 div-reg = <0xa4 0 3>;
372 spi_m_clk: spi_m_clk {
374 compatible = "altr,socfpga-gate-clk";
375 clocks = <&per_base_clk>;
377 div-reg = <0xa4 3 3>;
382 compatible = "altr,socfpga-gate-clk";
383 clocks = <&per_base_clk>;
385 div-reg = <0xa4 6 3>;
390 compatible = "altr,socfpga-gate-clk";
391 clocks = <&per_base_clk>;
393 div-reg = <0xa4 9 3>;
396 gpio_db_clk: gpio_db_clk {
398 compatible = "altr,socfpga-gate-clk";
399 clocks = <&per_base_clk>;
401 div-reg = <0xa8 0 24>;
404 h2f_user1_clk: h2f_user1_clk {
406 compatible = "altr,socfpga-gate-clk";
407 clocks = <&h2f_usr1_clk>;
411 sdmmc_clk: sdmmc_clk {
413 compatible = "altr,socfpga-gate-clk";
414 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
418 nand_x_clk: nand_x_clk {
420 compatible = "altr,socfpga-gate-clk";
421 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
427 compatible = "altr,socfpga-gate-clk";
428 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
429 clk-gate = <0xa0 10>;
435 compatible = "altr,socfpga-gate-clk";
436 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
437 clk-gate = <0xa0 11>;
442 gmac0: ethernet@ff700000 {
443 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
444 reg = <0xff700000 0x2000>;
445 interrupts = <0 115 4>;
446 interrupt-names = "macirq";
447 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
448 clocks = <&emac0_clk>;
449 clock-names = "stmmaceth";
453 gmac1: ethernet@ff702000 {
454 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
455 reg = <0xff702000 0x2000>;
456 interrupts = <0 120 4>;
457 interrupt-names = "macirq";
458 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
459 clocks = <&emac1_clk>;
460 clock-names = "stmmaceth";
464 L2: l2-cache@fffef000 {
465 compatible = "arm,pl310-cache";
466 reg = <0xfffef000 0x1000>;
467 interrupts = <0 38 0x04>;
474 compatible = "arm,cortex-a9-twd-timer";
475 reg = <0xfffec600 0x100>;
476 interrupts = <1 13 0xf04>;
477 clocks = <&mpu_periph_clk>;
480 timer0: timer0@ffc08000 {
481 compatible = "snps,dw-apb-timer";
482 interrupts = <0 167 4>;
483 reg = <0xffc08000 0x1000>;
486 timer1: timer1@ffc09000 {
487 compatible = "snps,dw-apb-timer";
488 interrupts = <0 168 4>;
489 reg = <0xffc09000 0x1000>;
492 timer2: timer2@ffd00000 {
493 compatible = "snps,dw-apb-timer";
494 interrupts = <0 169 4>;
495 reg = <0xffd00000 0x1000>;
498 timer3: timer3@ffd01000 {
499 compatible = "snps,dw-apb-timer";
500 interrupts = <0 170 4>;
501 reg = <0xffd01000 0x1000>;
504 uart0: serial0@ffc02000 {
505 compatible = "snps,dw-apb-uart";
506 reg = <0xffc02000 0x1000>;
507 interrupts = <0 162 4>;
512 uart1: serial1@ffc03000 {
513 compatible = "snps,dw-apb-uart";
514 reg = <0xffc03000 0x1000>;
515 interrupts = <0 163 4>;
521 compatible = "altr,rst-mgr";
522 reg = <0xffd05000 0x1000>;
526 compatible = "altr,sys-mgr";
527 reg = <0xffd08000 0x4000>;