arch/arm/boot/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 ethernet0 = &gmac0;
  26                 ethernet1 = &gmac1;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 timer0 = &timer0;
  30                 timer1 = &timer1;
  31                 timer2 = &timer2;
  32                 timer3 = &timer3;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         compatible = "arm,cortex-a9";
  41                         device_type = "cpu";
  42                         reg = <0>;
  43                         next-level-cache = <&L2>;
  44                 };
  45                 cpu@1 {
  46                         compatible = "arm,cortex-a9";
  47                         device_type = "cpu";
  48                         reg = <1>;
  49                         next-level-cache = <&L2>;
  50                 };
  51         };
  52
  53         intc: intc@fffed000 {
  54                 compatible = "arm,cortex-a9-gic";
  55                 #interrupt-cells = <3>;
  56                 interrupt-controller;
  57                 reg = <0xfffed000 0x1000>,
  58                       <0xfffec100 0x100>;
  59         };
  60
  61         soc {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 compatible = "simple-bus";
  65                 device_type = "soc";
  66                 interrupt-parent = <&intc>;
  67                 ranges;
  68
  69                 amba {
  70                         compatible = "arm,amba-bus";
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         ranges;
  74
  75                         pdma: pdma@ffe01000 {
  76                                 compatible = "arm,pl330", "arm,primecell";
  77                                 reg = <0xffe01000 0x1000>;
  78                                 interrupts = <0 180 4>;
  79                                 #dma-cells = <1>;
  80                                 #dma-channels = <8>;
  81                                 #dma-requests = <32>;
  82                         };
  83                 };
  84
  85                 clkmgr@ffd04000 {
  86                                 compatible = "altr,clk-mgr";
  87                                 reg = <0xffd04000 0x1000>;
  88
  89                                 clocks {
  90                                         #address-cells = <1>;
  91                                         #size-cells = <0>;
  92
  93                                         osc: osc1 {
  94                                                 #clock-cells = <0>;
  95                                                 compatible = "fixed-clock";
  96                                         };
  97
  98                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
  99                                                 #clock-cells = <0>;
 100                                                 compatible = "fixed-clock";
 101                                                 clock-frequency = <10000000>;
 102                                         };
 103
 104                                         main_pll: main_pll {
 105                                                 #address-cells = <1>;
 106                                                 #size-cells = <0>;
 107                                                 #clock-cells = <0>;
 108                                                 compatible = "altr,socfpga-pll-clock";
 109                                                 clocks = <&osc>;
 110                                                 reg = <0x40>;
 111
 112                                                 mpuclk: mpuclk {
 113                                                         #clock-cells = <0>;
 114                                                         compatible = "altr,socfpga-perip-clk";
 115                                                         clocks = <&main_pll>;
 116                                                         fixed-divider = <2>;
 117                                                         reg = <0x48>;
 118                                                 };
 119
 120                                                 mainclk: mainclk {
 121                                                         #clock-cells = <0>;
 122                                                         compatible = "altr,socfpga-perip-clk";
 123                                                         clocks = <&main_pll>;
 124                                                         fixed-divider = <4>;
 125                                                         reg = <0x4C>;
 126                                                 };
 127
 128                                                 dbg_base_clk: dbg_base_clk {
 129                                                         #clock-cells = <0>;
 130                                                         compatible = "altr,socfpga-perip-clk";
 131                                                         clocks = <&main_pll>;
 132                                                         fixed-divider = <4>;
 133                                                         reg = <0x50>;
 134                                                 };
 135
 136                                                 main_qspi_clk: main_qspi_clk {
 137                                                         #clock-cells = <0>;
 138                                                         compatible = "altr,socfpga-perip-clk";
 139                                                         clocks = <&main_pll>;
 140                                                         reg = <0x54>;
 141                                                 };
 142
 143                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
 144                                                         #clock-cells = <0>;
 145                                                         compatible = "altr,socfpga-perip-clk";
 146                                                         clocks = <&main_pll>;
 147                                                         reg = <0x58>;
 148                                                 };
 149
 150                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
 151                                                         #clock-cells = <0>;
 152                                                         compatible = "altr,socfpga-perip-clk";
 153                                                         clocks = <&main_pll>;
 154                                                         reg = <0x5C>;
 155                                                 };
 156                                         };
 157
 158                                         periph_pll: periph_pll {
 159                                                 #address-cells = <1>;
 160                                                 #size-cells = <0>;
 161                                                 #clock-cells = <0>;
 162                                                 compatible = "altr,socfpga-pll-clock";
 163                                                 clocks = <&osc>;
 164                                                 reg = <0x80>;
 165
 166                                                 emac0_clk: emac0_clk {
 167                                                         #clock-cells = <0>;
 168                                                         compatible = "altr,socfpga-perip-clk";
 169                                                         clocks = <&periph_pll>;
 170                                                         reg = <0x88>;
 171                                                 };
 172
 173                                                 emac1_clk: emac1_clk {
 174                                                         #clock-cells = <0>;
 175                                                         compatible = "altr,socfpga-perip-clk";
 176                                                         clocks = <&periph_pll>;
 177                                                         reg = <0x8C>;
 178                                                 };
 179
 180                                                 per_qspi_clk: per_qsi_clk {
 181                                                         #clock-cells = <0>;
 182                                                         compatible = "altr,socfpga-perip-clk";
 183                                                         clocks = <&periph_pll>;
 184                                                         reg = <0x90>;
 185                                                 };
 186
 187                                                 per_nand_mmc_clk: per_nand_mmc_clk {
 188                                                         #clock-cells = <0>;
 189                                                         compatible = "altr,socfpga-perip-clk";
 190                                                         clocks = <&periph_pll>;
 191                                                         reg = <0x94>;
 192                                                 };
 193
 194                                                 per_base_clk: per_base_clk {
 195                                                         #clock-cells = <0>;
 196                                                         compatible = "altr,socfpga-perip-clk";
 197                                                         clocks = <&periph_pll>;
 198                                                         reg = <0x98>;
 199                                                 };
 200
 201                                                 h2f_usr1_clk: h2f_usr1_clk {
 202                                                         #clock-cells = <0>;
 203                                                         compatible = "altr,socfpga-perip-clk";
 204                                                         clocks = <&periph_pll>;
 205                                                         reg = <0x9C>;
 206                                                 };
 207                                         };
 208
 209                                         sdram_pll: sdram_pll {
 210                                                 #address-cells = <1>;
 211                                                 #size-cells = <0>;
 212                                                 #clock-cells = <0>;
 213                                                 compatible = "altr,socfpga-pll-clock";
 214                                                 clocks = <&osc>;
 215                                                 reg = <0xC0>;
 216
 217                                                 ddr_dqs_clk: ddr_dqs_clk {
 218                                                         #clock-cells = <0>;
 219                                                         compatible = "altr,socfpga-perip-clk";
 220                                                         clocks = <&sdram_pll>;
 221                                                         reg = <0xC8>;
 222                                                 };
 223
 224                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
 225                                                         #clock-cells = <0>;
 226                                                         compatible = "altr,socfpga-perip-clk";
 227                                                         clocks = <&sdram_pll>;
 228                                                         reg = <0xCC>;
 229                                                 };
 230
 231                                                 ddr_dq_clk: ddr_dq_clk {
 232                                                         #clock-cells = <0>;
 233                                                         compatible = "altr,socfpga-perip-clk";
 234                                                         clocks = <&sdram_pll>;
 235                                                         reg = <0xD0>;
 236                                                 };
 237
 238                                                 h2f_usr2_clk: h2f_usr2_clk {
 239                                                         #clock-cells = <0>;
 240                                                         compatible = "altr,socfpga-perip-clk";
 241                                                         clocks = <&sdram_pll>;
 242                                                         reg = <0xD4>;
 243                                                 };
 244                                         };
 245
 246                                         mpu_periph_clk: mpu_periph_clk {
 247                                                 #clock-cells = <0>;
 248                                                 compatible = "altr,socfpga-gate-clk";
 249                                                 clocks = <&mpuclk>;
 250                                                 fixed-divider = <4>;
 251                                         };
 252
 253                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 254                                                 #clock-cells = <0>;
 255                                                 compatible = "altr,socfpga-gate-clk";
 256                                                 clocks = <&mpuclk>;
 257                                                 fixed-divider = <2>;
 258                                         };
 259
 260                                         l4_main_clk: l4_main_clk {
 261                                                 #clock-cells = <0>;
 262                                                 compatible = "altr,socfpga-gate-clk";
 263                                                 clocks = <&mainclk>;
 264                                                 clk-gate = <0x60 0>;
 265                                         };
 266
 267                                         l3_main_clk: l3_main_clk {
 268                                                 #clock-cells = <0>;
 269                                                 compatible = "altr,socfpga-gate-clk";
 270                                                 clocks = <&mainclk>;
 271                                         };
 272
 273                                         l3_mp_clk: l3_mp_clk {
 274                                                 #clock-cells = <0>;
 275                                                 compatible = "altr,socfpga-gate-clk";
 276                                                 clocks = <&mainclk>;
 277                                                 div-reg = <0x64 0 2>;
 278                                                 clk-gate = <0x60 1>;
 279                                         };
 280
 281                                         l3_sp_clk: l3_sp_clk {
 282                                                 #clock-cells = <0>;
 283                                                 compatible = "altr,socfpga-gate-clk";
 284                                                 clocks = <&mainclk>;
 285                                                 div-reg = <0x64 2 2>;
 286                                         };
 287
 288                                         l4_mp_clk: l4_mp_clk {
 289                                                 #clock-cells = <0>;
 290                                                 compatible = "altr,socfpga-gate-clk";
 291                                                 clocks = <&mainclk>, <&per_base_clk>;
 292                                                 div-reg = <0x64 4 3>;
 293                                                 clk-gate = <0x60 2>;
 294                                         };
 295
 296                                         l4_sp_clk: l4_sp_clk {
 297                                                 #clock-cells = <0>;
 298                                                 compatible = "altr,socfpga-gate-clk";
 299                                                 clocks = <&mainclk>, <&per_base_clk>;
 300                                                 div-reg = <0x64 7 3>;
 301                                                 clk-gate = <0x60 3>;
 302                                         };
 303
 304                                         dbg_at_clk: dbg_at_clk {
 305                                                 #clock-cells = <0>;
 306                                                 compatible = "altr,socfpga-gate-clk";
 307                                                 clocks = <&dbg_base_clk>;
 308                                                 div-reg = <0x68 0 2>;
 309                                                 clk-gate = <0x60 4>;
 310                                         };
 311
 312                                         dbg_clk: dbg_clk {
 313                                                 #clock-cells = <0>;
 314                                                 compatible = "altr,socfpga-gate-clk";
 315                                                 clocks = <&dbg_base_clk>;
 316                                                 div-reg = <0x68 2 2>;
 317                                                 clk-gate = <0x60 5>;
 318                                         };
 319
 320                                         dbg_trace_clk: dbg_trace_clk {
 321                                                 #clock-cells = <0>;
 322                                                 compatible = "altr,socfpga-gate-clk";
 323                                                 clocks = <&dbg_base_clk>;
 324                                                 div-reg = <0x6C 0 3>;
 325                                                 clk-gate = <0x60 6>;
 326                                         };
 327
 328                                         dbg_timer_clk: dbg_timer_clk {
 329                                                 #clock-cells = <0>;
 330                                                 compatible = "altr,socfpga-gate-clk";
 331                                                 clocks = <&dbg_base_clk>;
 332                                                 clk-gate = <0x60 7>;
 333                                         };
 334
 335                                         cfg_clk: cfg_clk {
 336                                                 #clock-cells = <0>;
 337                                                 compatible = "altr,socfpga-gate-clk";
 338                                                 clocks = <&cfg_h2f_usr0_clk>;
 339                                                 clk-gate = <0x60 8>;
 340                                         };
 341
 342                                         h2f_user0_clk: h2f_user0_clk {
 343                                                 #clock-cells = <0>;
 344                                                 compatible = "altr,socfpga-gate-clk";
 345                                                 clocks = <&cfg_h2f_usr0_clk>;
 346                                                 clk-gate = <0x60 9>;
 347                                         };
 348
 349                                         emac_0_clk: emac_0_clk {
 350                                                 #clock-cells = <0>;
 351                                                 compatible = "altr,socfpga-gate-clk";
 352                                                 clocks = <&emac0_clk>;
 353                                                 clk-gate = <0xa0 0>;
 354                                         };
 355
 356                                         emac_1_clk: emac_1_clk {
 357                                                 #clock-cells = <0>;
 358                                                 compatible = "altr,socfpga-gate-clk";
 359                                                 clocks = <&emac1_clk>;
 360                                                 clk-gate = <0xa0 1>;
 361                                         };
 362
 363                                         usb_mp_clk: usb_mp_clk {
 364                                                 #clock-cells = <0>;
 365                                                 compatible = "altr,socfpga-gate-clk";
 366                                                 clocks = <&per_base_clk>;
 367                                                 clk-gate = <0xa0 2>;
 368                                                 div-reg = <0xa4 0 3>;
 369                                         };
 370
 371                                         spi_m_clk: spi_m_clk {
 372                                                 #clock-cells = <0>;
 373                                                 compatible = "altr,socfpga-gate-clk";
 374                                                 clocks = <&per_base_clk>;
 375                                                 clk-gate = <0xa0 3>;
 376                                                 div-reg = <0xa4 3 3>;
 377                                         };
 378
 379                                         can0_clk: can0_clk {
 380                                                 #clock-cells = <0>;
 381                                                 compatible = "altr,socfpga-gate-clk";
 382                                                 clocks = <&per_base_clk>;
 383                                                 clk-gate = <0xa0 4>;
 384                                                 div-reg = <0xa4 6 3>;
 385                                         };
 386
 387                                         can1_clk: can1_clk {
 388                                                 #clock-cells = <0>;
 389                                                 compatible = "altr,socfpga-gate-clk";
 390                                                 clocks = <&per_base_clk>;
 391                                                 clk-gate = <0xa0 5>;
 392                                                 div-reg = <0xa4 9 3>;
 393                                         };
 394
 395                                         gpio_db_clk: gpio_db_clk {
 396                                                 #clock-cells = <0>;
 397                                                 compatible = "altr,socfpga-gate-clk";
 398                                                 clocks = <&per_base_clk>;
 399                                                 clk-gate = <0xa0 6>;
 400                                                 div-reg = <0xa8 0 24>;
 401                                         };
 402
 403                                         h2f_user1_clk: h2f_user1_clk {
 404                                                 #clock-cells = <0>;
 405                                                 compatible = "altr,socfpga-gate-clk";
 406                                                 clocks = <&h2f_usr1_clk>;
 407                                                 clk-gate = <0xa0 7>;
 408                                         };
 409
 410                                         sdmmc_clk: sdmmc_clk {
 411                                                 #clock-cells = <0>;
 412                                                 compatible = "altr,socfpga-gate-clk";
 413                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 414                                                 clk-gate = <0xa0 8>;
 415                                         };
 416
 417                                         nand_x_clk: nand_x_clk {
 418                                                 #clock-cells = <0>;
 419                                                 compatible = "altr,socfpga-gate-clk";
 420                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 421                                                 clk-gate = <0xa0 9>;
 422                                         };
 423
 424                                         nand_clk: nand_clk {
 425                                                 #clock-cells = <0>;
 426                                                 compatible = "altr,socfpga-gate-clk";
 427                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 428                                                 clk-gate = <0xa0 10>;
 429                                                 fixed-divider = <4>;
 430                                         };
 431
 432                                         qspi_clk: qspi_clk {
 433                                                 #clock-cells = <0>;
 434                                                 compatible = "altr,socfpga-gate-clk";
 435                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 436                                                 clk-gate = <0xa0 11>;
 437                                         };
 438                                 };
 439                         };
 440
 441                 gmac0: ethernet@ff700000 {
 442                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 443                         reg = <0xff700000 0x2000>;
 444                         interrupts = <0 115 4>;
 445                         interrupt-names = "macirq";
 446                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 447                         clocks = <&emac0_clk>;
 448                         clock-names = "stmmaceth";
 449                         status = "disabled";
 450                 };
 451
 452                 gmac1: ethernet@ff702000 {
 453                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 454                         reg = <0xff702000 0x2000>;
 455                         interrupts = <0 120 4>;
 456                         interrupt-names = "macirq";
 457                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 458                         clocks = <&emac1_clk>;
 459                         clock-names = "stmmaceth";
 460                         status = "disabled";
 461                 };
 462
 463                 L2: l2-cache@fffef000 {
 464                         compatible = "arm,pl310-cache";
 465                         reg = <0xfffef000 0x1000>;
 466                         interrupts = <0 38 0x04>;
 467                         cache-unified;
 468                         cache-level = <2>;
 469                 };
 470
 471                 /* Local timer */
 472                 timer@fffec600 {
 473                         compatible = "arm,cortex-a9-twd-timer";
 474                         reg = <0xfffec600 0x100>;
 475                         interrupts = <1 13 0xf04>;
 476                         clocks = <&mpu_periph_clk>;
 477                 };
 478
 479                 timer0: timer0@ffc08000 {
 480                         compatible = "snps,dw-apb-timer";
 481                         interrupts = <0 167 4>;
 482                         reg = <0xffc08000 0x1000>;
 483                 };
 484
 485                 timer1: timer1@ffc09000 {
 486                         compatible = "snps,dw-apb-timer";
 487                         interrupts = <0 168 4>;
 488                         reg = <0xffc09000 0x1000>;
 489                 };
 490
 491                 timer2: timer2@ffd00000 {
 492                         compatible = "snps,dw-apb-timer";
 493                         interrupts = <0 169 4>;
 494                         reg = <0xffd00000 0x1000>;
 495                 };
 496
 497                 timer3: timer3@ffd01000 {
 498                         compatible = "snps,dw-apb-timer";
 499                         interrupts = <0 170 4>;
 500                         reg = <0xffd01000 0x1000>;
 501                 };
 502
 503                 uart0: serial0@ffc02000 {
 504                         compatible = "snps,dw-apb-uart";
 505                         reg = <0xffc02000 0x1000>;
 506                         interrupts = <0 162 4>;
 507                         reg-shift = <2>;
 508                         reg-io-width = <4>;
 509                 };
 510
 511                 uart1: serial1@ffc03000 {
 512                         compatible = "snps,dw-apb-uart";
 513                         reg = <0xffc03000 0x1000>;
 514                         interrupts = <0 163 4>;
 515                         reg-shift = <2>;
 516                         reg-io-width = <4>;
 517                 };
 518
 519                 rstmgr@ffd05000 {
 520                         compatible = "altr,rst-mgr";
 521                         reg = <0xffd05000 0x1000>;
 522                 };
 523
 524                 sysmgr@ffd08000 {
 525                                 compatible = "altr,sys-mgr";
 526                                 reg = <0xffd08000 0x4000>;
 527                         };
 528         };
 529 };