arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include "rk3xxx.dtsi"
  19 #include "rk3066a-clocks.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3066a";
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         next-level-cache = <&L2>;
  32                         reg = <0x0>;
  33                 };
  34                 cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a9";
  37                         next-level-cache = <&L2>;
  38                         reg = <0x1>;
  39                 };
  40         };
  41
  42         soc {
  43                 timer@20038000 {
  44                         compatible = "snps,dw-apb-timer-osc";
  45                         reg = <0x20038000 0x100>;
  46                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  47                         clocks = <&clk_gates1 0>, <&clk_gates7 7>;
  48                         clock-names = "timer", "pclk";
  49                 };
  50
  51                 timer@2003a000 {
  52                         compatible = "snps,dw-apb-timer-osc";
  53                         reg = <0x2003a000 0x100>;
  54                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  55                         clocks = <&clk_gates1 1>, <&clk_gates7 8>;
  56                         clock-names = "timer", "pclk";
  57                 };
  58
  59                 timer@2000e000 {
  60                         compatible = "snps,dw-apb-timer-osc";
  61                         reg = <0x2000e000 0x100>;
  62                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  63                         clocks = <&clk_gates1 2>, <&clk_gates7 9>;
  64                         clock-names = "timer", "pclk";
  65                 };
  66
  67                 pinctrl@20008000 {
  68                         compatible = "rockchip,rk3066a-pinctrl";
  69                         reg = <0x20008000 0x150>;
  70                         #address-cells = <1>;
  71                         #size-cells = <1>;
  72                         ranges;
  73
  74                         gpio0: gpio0@20034000 {
  75                                 compatible = "rockchip,gpio-bank";
  76                                 reg = <0x20034000 0x100>;
  77                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  78                                 clocks = <&clk_gates8 9>;
  79
  80                                 gpio-controller;
  81                                 #gpio-cells = <2>;
  82
  83                                 interrupt-controller;
  84                                 #interrupt-cells = <2>;
  85                         };
  86
  87                         gpio1: gpio1@2003c000 {
  88                                 compatible = "rockchip,gpio-bank";
  89                                 reg = <0x2003c000 0x100>;
  90                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  91                                 clocks = <&clk_gates8 10>;
  92
  93                                 gpio-controller;
  94                                 #gpio-cells = <2>;
  95
  96                                 interrupt-controller;
  97                                 #interrupt-cells = <2>;
  98                         };
  99
 100                         gpio2: gpio2@2003e000 {
 101                                 compatible = "rockchip,gpio-bank";
 102                                 reg = <0x2003e000 0x100>;
 103                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 104                                 clocks = <&clk_gates8 11>;
 105
 106                                 gpio-controller;
 107                                 #gpio-cells = <2>;
 108
 109                                 interrupt-controller;
 110                                 #interrupt-cells = <2>;
 111                         };
 112
 113                         gpio3: gpio3@20080000 {
 114                                 compatible = "rockchip,gpio-bank";
 115                                 reg = <0x20080000 0x100>;
 116                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 117                                 clocks = <&clk_gates8 12>;
 118
 119                                 gpio-controller;
 120                                 #gpio-cells = <2>;
 121
 122                                 interrupt-controller;
 123                                 #interrupt-cells = <2>;
 124                         };
 125
 126                         gpio4: gpio4@20084000 {
 127                                 compatible = "rockchip,gpio-bank";
 128                                 reg = <0x20084000 0x100>;
 129                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 130                                 clocks = <&clk_gates8 13>;
 131
 132                                 gpio-controller;
 133                                 #gpio-cells = <2>;
 134
 135                                 interrupt-controller;
 136                                 #interrupt-cells = <2>;
 137                         };
 138
 139                         gpio6: gpio6@2000a000 {
 140                                 compatible = "rockchip,gpio-bank";
 141                                 reg = <0x2000a000 0x100>;
 142                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 143                                 clocks = <&clk_gates8 15>;
 144
 145                                 gpio-controller;
 146                                 #gpio-cells = <2>;
 147
 148                                 interrupt-controller;
 149                                 #interrupt-cells = <2>;
 150                         };
 151
 152                         pcfg_pull_default: pcfg_pull_default {
 153                                 bias-pull-pin-default;
 154                         };
 155
 156                         pcfg_pull_none: pcfg_pull_none {
 157                                 bias-disable;
 158                         };
 159
 160                         uart0 {
 161                                 uart0_xfer: uart0-xfer {
 162                                         rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 163                                                         <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 164                                 };
 165
 166                                 uart0_cts: uart0-cts {
 167                                         rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 168                                 };
 169
 170                                 uart0_rts: uart0-rts {
 171                                         rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 172                                 };
 173                         };
 174
 175                         uart1 {
 176                                 uart1_xfer: uart1-xfer {
 177                                         rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 178                                                         <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 179                                 };
 180
 181                                 uart1_cts: uart1-cts {
 182                                         rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 183                                 };
 184
 185                                 uart1_rts: uart1-rts {
 186                                         rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 187                                 };
 188                         };
 189
 190                         uart2 {
 191                                 uart2_xfer: uart2-xfer {
 192                                         rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 193                                                         <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 194                                 };
 195                                 /* no rts / cts for uart2 */
 196                         };
 197
 198                         uart3 {
 199                                 uart3_xfer: uart3-xfer {
 200                                         rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 201                                                         <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 202                                 };
 203
 204                                 uart3_cts: uart3-cts {
 205                                         rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 206                                 };
 207
 208                                 uart3_rts: uart3-rts {
 209                                         rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 210                                 };
 211                         };
 212
 213                         sd0 {
 214                                 sd0_clk: sd0-clk {
 215                                         rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 216                                 };
 217
 218                                 sd0_cmd: sd0-cmd {
 219                                         rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 220                                 };
 221
 222                                 sd0_cd: sd0-cd {
 223                                         rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 224                                 };
 225
 226                                 sd0_wp: sd0-wp {
 227                                         rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 228                                 };
 229
 230                                 sd0_bus1: sd0-bus-width1 {
 231                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 232                                 };
 233
 234                                 sd0_bus4: sd0-bus-width4 {
 235                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 236                                                         <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 237                                                         <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 238                                                         <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 239                                 };
 240                         };
 241
 242                         sd1 {
 243                                 sd1_clk: sd1-clk {
 244                                         rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 245                                 };
 246
 247                                 sd1_cmd: sd1-cmd {
 248                                         rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 249                                 };
 250
 251                                 sd1_cd: sd1-cd {
 252                                         rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 253                                 };
 254
 255                                 sd1_wp: sd1-wp {
 256                                         rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 257                                 };
 258
 259                                 sd1_bus1: sd1-bus-width1 {
 260                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 261                                 };
 262
 263                                 sd1_bus4: sd1-bus-width4 {
 264                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 265                                                         <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 266                                                         <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 267                                                         <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 268                                 };
 269                         };
 270                 };
 271         };
 272 };