arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0x0>;
  24                         d-cache-line-size = <32>;
  25                         i-cache-line-size = <32>;
  26                         d-cache-size = <32768>;
  27                         i-cache-size = <32768>;
  28                         /* from bootloader */
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                 };
  33         };
  34
  35         axi {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges = <0x40000000 0x40000000 0x80000000>;
  40
  41                 l2-cache-controller@80040000 {
  42                         compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
  43                         reg = <0x80040000 0x1000>;
  44                         interrupts = <59>;
  45                         arm,tag-latency = <1 1 1>;
  46                         arm,data-latency = <1 1 1>;
  47                         arm,filter-ranges = <0 0x40000000>;
  48                 };
  49
  50                 intc: interrupt-controller@80020000 {
  51                         #interrupt-cells = <1>;
  52                         interrupt-controller;
  53                         compatible = "sirf,prima2-intc";
  54                         reg = <0x80020000 0x1000>;
  55                 };
  56
  57                 sys-iobg {
  58                         compatible = "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges = <0x88000000 0x88000000 0x40000>;
  62
  63                         clks: clock-controller@88000000 {
  64                                 compatible = "sirf,prima2-clkc";
  65                                 reg = <0x88000000 0x1000>;
  66                                 interrupts = <3>;
  67                                 #clock-cells = <1>;
  68                         };
  69
  70                         reset-controller@88010000 {
  71                                 compatible = "sirf,prima2-rstc";
  72                                 reg = <0x88010000 0x1000>;
  73                         };
  74
  75                         rsc-controller@88020000 {
  76                                 compatible = "sirf,prima2-rsc";
  77                                 reg = <0x88020000 0x1000>;
  78                         };
  79
  80                         cphifbg@88030000 {
  81                                 compatible = "sirf,prima2-cphifbg";
  82                                 reg = <0x88030000 0x1000>;
  83                         };
  84                 };
  85
  86                 mem-iobg {
  87                         compatible = "simple-bus";
  88                         #address-cells = <1>;
  89                         #size-cells = <1>;
  90                         ranges = <0x90000000 0x90000000 0x10000>;
  91
  92                         memory-controller@90000000 {
  93                                 compatible = "sirf,prima2-memc";
  94                                 reg = <0x90000000 0x2000>;
  95                                 interrupts = <27>;
  96                                 clocks = <&clks 5>;
  97                         };
  98
  99                         memc-monitor {
 100                                 compatible = "sirf,prima2-memcmon";
 101                                 reg = <0x90002000 0x200>;
 102                                 interrupts = <4>;
 103                                 clocks = <&clks 32>;
 104                         };
 105                 };
 106
 107                 disp-iobg {
 108                         compatible = "simple-bus";
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111                         ranges = <0x90010000 0x90010000 0x30000>;
 112
 113                         display@90010000 {
 114                                 compatible = "sirf,prima2-lcd";
 115                                 reg = <0x90010000 0x20000>;
 116                                 interrupts = <30>;
 117                         };
 118
 119                         vpp@90020000 {
 120                                 compatible = "sirf,prima2-vpp";
 121                                 reg = <0x90020000 0x10000>;
 122                                 interrupts = <31>;
 123                                 clocks = <&clks 35>;
 124                         };
 125                 };
 126
 127                 graphics-iobg {
 128                         compatible = "simple-bus";
 129                         #address-cells = <1>;
 130                         #size-cells = <1>;
 131                         ranges = <0x98000000 0x98000000 0x8000000>;
 132
 133                         graphics@98000000 {
 134                                 compatible = "powervr,sgx531";
 135                                 reg = <0x98000000 0x8000000>;
 136                                 interrupts = <6>;
 137                                 clocks = <&clks 32>;
 138                         };
 139                 };
 140
 141                 multimedia-iobg {
 142                         compatible = "simple-bus";
 143                         #address-cells = <1>;
 144                         #size-cells = <1>;
 145                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 146
 147                         multimedia@a0000000 {
 148                                 compatible = "sirf,prima2-video-codec";
 149                                 reg = <0xa0000000 0x8000000>;
 150                                 interrupts = <5>;
 151                                 clocks = <&clks 33>;
 152                         };
 153                 };
 154
 155                 dsp-iobg {
 156                         compatible = "simple-bus";
 157                         #address-cells = <1>;
 158                         #size-cells = <1>;
 159                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 160
 161                         dspif@a8000000 {
 162                                 compatible = "sirf,prima2-dspif";
 163                                 reg = <0xa8000000 0x10000>;
 164                                 interrupts = <9>;
 165                         };
 166
 167                         gps@a8010000 {
 168                                 compatible = "sirf,prima2-gps";
 169                                 reg = <0xa8010000 0x10000>;
 170                                 interrupts = <7>;
 171                                 clocks = <&clks 9>;
 172                         };
 173
 174                         dsp@a9000000 {
 175                                 compatible = "sirf,prima2-dsp";
 176                                 reg = <0xa9000000 0x1000000>;
 177                                 interrupts = <8>;
 178                                 clocks = <&clks 8>;
 179                         };
 180                 };
 181
 182                 peri-iobg {
 183                         compatible = "simple-bus";
 184                         #address-cells = <1>;
 185                         #size-cells = <1>;
 186                         ranges = <0xb0000000 0xb0000000 0x180000>,
 187                                <0x56000000 0x56000000 0x1b00000>;
 188
 189                         timer@b0020000 {
 190                                 compatible = "sirf,prima2-tick";
 191                                 reg = <0xb0020000 0x1000>;
 192                                 interrupts = <0>;
 193                         };
 194
 195                         nand@b0030000 {
 196                                 compatible = "sirf,prima2-nand";
 197                                 reg = <0xb0030000 0x10000>;
 198                                 interrupts = <41>;
 199                                 clocks = <&clks 26>;
 200                         };
 201
 202                         audio@b0040000 {
 203                                 compatible = "sirf,prima2-audio";
 204                                 reg = <0xb0040000 0x10000>;
 205                                 interrupts = <35>;
 206                                 clocks = <&clks 27>;
 207                         };
 208
 209                         uart0: uart@b0050000 {
 210                                 cell-index = <0>;
 211                                 compatible = "sirf,prima2-uart";
 212                                 reg = <0xb0050000 0x1000>;
 213                                 interrupts = <17>;
 214                                 fifosize = <128>;
 215                                 clocks = <&clks 13>;
 216                                 sirf,uart-dma-rx-channel = <21>;
 217                                 sirf,uart-dma-tx-channel = <2>;
 218                         };
 219
 220                         uart1: uart@b0060000 {
 221                                 cell-index = <1>;
 222                                 compatible = "sirf,prima2-uart";
 223                                 reg = <0xb0060000 0x1000>;
 224                                 interrupts = <18>;
 225                                 fifosize = <32>;
 226                                 clocks = <&clks 14>;
 227                         };
 228
 229                         uart2: uart@b0070000 {
 230                                 cell-index = <2>;
 231                                 compatible = "sirf,prima2-uart";
 232                                 reg = <0xb0070000 0x1000>;
 233                                 interrupts = <19>;
 234                                 fifosize = <128>;
 235                                 clocks = <&clks 15>;
 236                                 sirf,uart-dma-rx-channel = <6>;
 237                                 sirf,uart-dma-tx-channel = <7>;
 238                         };
 239
 240                         usp0: usp@b0080000 {
 241                                 cell-index = <0>;
 242                                 compatible = "sirf,prima2-usp";
 243                                 reg = <0xb0080000 0x10000>;
 244                                 interrupts = <20>;
 245                                 fifosize = <128>;
 246                                 clocks = <&clks 28>;
 247                                 sirf,usp-dma-rx-channel = <17>;
 248                                 sirf,usp-dma-tx-channel = <18>;
 249                         };
 250
 251                         usp1: usp@b0090000 {
 252                                 cell-index = <1>;
 253                                 compatible = "sirf,prima2-usp";
 254                                 reg = <0xb0090000 0x10000>;
 255                                 interrupts = <21>;
 256                                 fifosize = <128>;
 257                                 clocks = <&clks 29>;
 258                                 sirf,usp-dma-rx-channel = <14>;
 259                                 sirf,usp-dma-tx-channel = <15>;
 260                         };
 261
 262                         usp2: usp@b00a0000 {
 263                                 cell-index = <2>;
 264                                 compatible = "sirf,prima2-usp";
 265                                 reg = <0xb00a0000 0x10000>;
 266                                 interrupts = <22>;
 267                                 fifosize = <128>;
 268                                 clocks = <&clks 30>;
 269                                 sirf,usp-dma-rx-channel = <10>;
 270                                 sirf,usp-dma-tx-channel = <11>;
 271                         };
 272
 273                         dmac0: dma-controller@b00b0000 {
 274                                 cell-index = <0>;
 275                                 compatible = "sirf,prima2-dmac";
 276                                 reg = <0xb00b0000 0x10000>;
 277                                 interrupts = <12>;
 278                                 clocks = <&clks 24>;
 279                         };
 280
 281                         dmac1: dma-controller@b0160000 {
 282                                 cell-index = <1>;
 283                                 compatible = "sirf,prima2-dmac";
 284                                 reg = <0xb0160000 0x10000>;
 285                                 interrupts = <13>;
 286                                 clocks = <&clks 25>;
 287                         };
 288
 289                         vip@b00C0000 {
 290                                 compatible = "sirf,prima2-vip";
 291                                 reg = <0xb00C0000 0x10000>;
 292                                 clocks = <&clks 31>;
 293                                 interrupts = <14>;
 294                                 sirf,vip-dma-rx-channel = <16>;
 295                         };
 296
 297                         spi0: spi@b00d0000 {
 298                                 cell-index = <0>;
 299                                 compatible = "sirf,prima2-spi";
 300                                 reg = <0xb00d0000 0x10000>;
 301                                 interrupts = <15>;
 302                                 sirf,spi-num-chipselects = <1>;
 303                                 sirf,spi-dma-rx-channel = <25>;
 304                                 sirf,spi-dma-tx-channel = <20>;
 305                                 #address-cells = <1>;
 306                                 #size-cells = <0>;
 307                                 clocks = <&clks 19>;
 308                                 status = "disabled";
 309                         };
 310
 311                         spi1: spi@b0170000 {
 312                                 cell-index = <1>;
 313                                 compatible = "sirf,prima2-spi";
 314                                 reg = <0xb0170000 0x10000>;
 315                                 interrupts = <16>;
 316                                 sirf,spi-num-chipselects = <1>;
 317                                 sirf,spi-dma-rx-channel = <12>;
 318                                 sirf,spi-dma-tx-channel = <13>;
 319                                 #address-cells = <1>;
 320                                 #size-cells = <0>;
 321                                 clocks = <&clks 20>;
 322                                 status = "disabled";
 323                         };
 324
 325                         i2c0: i2c@b00e0000 {
 326                                 cell-index = <0>;
 327                                 compatible = "sirf,prima2-i2c";
 328                                 reg = <0xb00e0000 0x10000>;
 329                                 interrupts = <24>;
 330                                 clocks = <&clks 17>;
 331                                 #address-cells = <1>;
 332                                 #size-cells = <0>;
 333                         };
 334
 335                         i2c1: i2c@b00f0000 {
 336                                 cell-index = <1>;
 337                                 compatible = "sirf,prima2-i2c";
 338                                 reg = <0xb00f0000 0x10000>;
 339                                 interrupts = <25>;
 340                                 clocks = <&clks 18>;
 341                                 #address-cells = <1>;
 342                                 #size-cells = <0>;
 343                         };
 344
 345                         tsc@b0110000 {
 346                                 compatible = "sirf,prima2-tsc";
 347                                 reg = <0xb0110000 0x10000>;
 348                                 interrupts = <33>;
 349                                 clocks = <&clks 16>;
 350                         };
 351
 352                         gpio: pinctrl@b0120000 {
 353                                 #gpio-cells = <2>;
 354                                 #interrupt-cells = <2>;
 355                                 compatible = "sirf,prima2-pinctrl";
 356                                 reg = <0xb0120000 0x10000>;
 357                                 interrupts = <43 44 45 46 47>;
 358                                 gpio-controller;
 359                                 interrupt-controller;
 360
 361                                 lcd_16pins_a: lcd0@0 {
 362                                         lcd {
 363                                                 sirf,pins = "lcd_16bitsgrp";
 364                                                 sirf,function = "lcd_16bits";
 365                                         };
 366                                 };
 367                                 lcd_18pins_a: lcd0@1 {
 368                                         lcd {
 369                                                 sirf,pins = "lcd_18bitsgrp";
 370                                                 sirf,function = "lcd_18bits";
 371                                         };
 372                                 };
 373                                 lcd_24pins_a: lcd0@2 {
 374                                         lcd {
 375                                                 sirf,pins = "lcd_24bitsgrp";
 376                                                 sirf,function = "lcd_24bits";
 377                                         };
 378                                 };
 379                                 lcdrom_pins_a: lcdrom0@0 {
 380                                         lcd {
 381                                                 sirf,pins = "lcdromgrp";
 382                                                 sirf,function = "lcdrom";
 383                                         };
 384                                 };
 385                                 uart0_pins_a: uart0@0 {
 386                                         uart {
 387                                                 sirf,pins = "uart0grp";
 388                                                 sirf,function = "uart0";
 389                                         };
 390                                 };
 391                                 uart0_noflow_pins_a: uart0@1 {
 392                                         uart {
 393                                                 sirf,pins = "uart0_nostreamctrlgrp";
 394                                                 sirf,function = "uart0_nostreamctrl";
 395                                         };
 396                                 };
 397                                 uart1_pins_a: uart1@0 {
 398                                         uart {
 399                                                 sirf,pins = "uart1grp";
 400                                                 sirf,function = "uart1";
 401                                         };
 402                                 };
 403                                 uart2_pins_a: uart2@0 {
 404                                         uart {
 405                                                 sirf,pins = "uart2grp";
 406                                                 sirf,function = "uart2";
 407                                         };
 408                                 };
 409                                 uart2_noflow_pins_a: uart2@1 {
 410                                         uart {
 411                                                 sirf,pins = "uart2_nostreamctrlgrp";
 412                                                 sirf,function = "uart2_nostreamctrl";
 413                                         };
 414                                 };
 415                                 spi0_pins_a: spi0@0 {
 416                                         spi {
 417                                                 sirf,pins = "spi0grp";
 418                                                 sirf,function = "spi0";
 419                                         };
 420                                 };
 421                                 spi1_pins_a: spi1@0 {
 422                                         spi {
 423                                                 sirf,pins = "spi1grp";
 424                                                 sirf,function = "spi1";
 425                                         };
 426                                 };
 427                                 i2c0_pins_a: i2c0@0 {
 428                                         i2c {
 429                                                 sirf,pins = "i2c0grp";
 430                                                 sirf,function = "i2c0";
 431                                         };
 432                                 };
 433                                 i2c1_pins_a: i2c1@0 {
 434                                         i2c {
 435                                                 sirf,pins = "i2c1grp";
 436                                                 sirf,function = "i2c1";
 437                                         };
 438                                 };
 439                                 pwm0_pins_a: pwm0@0 {
 440                                         pwm {
 441                                                 sirf,pins = "pwm0grp";
 442                                                 sirf,function = "pwm0";
 443                                         };
 444                                 };
 445                                 pwm1_pins_a: pwm1@0 {
 446                                         pwm {
 447                                                 sirf,pins = "pwm1grp";
 448                                                 sirf,function = "pwm1";
 449                                         };
 450                                 };
 451                                 pwm2_pins_a: pwm2@0 {
 452                                         pwm {
 453                                                 sirf,pins = "pwm2grp";
 454                                                 sirf,function = "pwm2";
 455                                         };
 456                                 };
 457                                 pwm3_pins_a: pwm3@0 {
 458                                         pwm {
 459                                                 sirf,pins = "pwm3grp";
 460                                                 sirf,function = "pwm3";
 461                                         };
 462                                 };
 463                                 gps_pins_a: gps@0 {
 464                                         gps {
 465                                                 sirf,pins = "gpsgrp";
 466                                                 sirf,function = "gps";
 467                                         };
 468                                 };
 469                                 vip_pins_a: vip@0 {
 470                                         vip {
 471                                                 sirf,pins = "vipgrp";
 472                                                 sirf,function = "vip";
 473                                         };
 474                                 };
 475                                 sdmmc0_pins_a: sdmmc0@0 {
 476                                         sdmmc0 {
 477                                                 sirf,pins = "sdmmc0grp";
 478                                                 sirf,function = "sdmmc0";
 479                                         };
 480                                 };
 481                                 sdmmc1_pins_a: sdmmc1@0 {
 482                                         sdmmc1 {
 483                                                 sirf,pins = "sdmmc1grp";
 484                                                 sirf,function = "sdmmc1";
 485                                         };
 486                                 };
 487                                 sdmmc2_pins_a: sdmmc2@0 {
 488                                         sdmmc2 {
 489                                                 sirf,pins = "sdmmc2grp";
 490                                                 sirf,function = "sdmmc2";
 491                                         };
 492                                 };
 493                                 sdmmc3_pins_a: sdmmc3@0 {
 494                                         sdmmc3 {
 495                                                 sirf,pins = "sdmmc3grp";
 496                                                 sirf,function = "sdmmc3";
 497                                         };
 498                                 };
 499                                 sdmmc4_pins_a: sdmmc4@0 {
 500                                         sdmmc4 {
 501                                                 sirf,pins = "sdmmc4grp";
 502                                                 sirf,function = "sdmmc4";
 503                                         };
 504                                 };
 505                                 sdmmc5_pins_a: sdmmc5@0 {
 506                                         sdmmc5 {
 507                                                 sirf,pins = "sdmmc5grp";
 508                                                 sirf,function = "sdmmc5";
 509                                         };
 510                                 };
 511                                 i2s_pins_a: i2s@0 {
 512                                         i2s {
 513                                                 sirf,pins = "i2sgrp";
 514                                                 sirf,function = "i2s";
 515                                         };
 516                                 };
 517                                 ac97_pins_a: ac97@0 {
 518                                         ac97 {
 519                                                 sirf,pins = "ac97grp";
 520                                                 sirf,function = "ac97";
 521                                         };
 522                                 };
 523                                 nand_pins_a: nand@0 {
 524                                         nand {
 525                                                 sirf,pins = "nandgrp";
 526                                                 sirf,function = "nand";
 527                                         };
 528                                 };
 529                                 usp0_pins_a: usp0@0 {
 530                                         usp0 {
 531                                                 sirf,pins = "usp0grp";
 532                                                 sirf,function = "usp0";
 533                                         };
 534                                 };
 535                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 536                                         usp0 {
 537                                                 sirf,pins =
 538                                                         "usp0_uart_nostreamctrl_grp";
 539                                                 sirf,function =
 540                                                         "usp0_uart_nostreamctrl";
 541                                         };
 542                                 };
 543                                 usp1_pins_a: usp1@0 {
 544                                         usp1 {
 545                                                 sirf,pins = "usp1grp";
 546                                                 sirf,function = "usp1";
 547                                         };
 548                                 };
 549                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
 550                                         usp1 {
 551                                                 sirf,pins =
 552                                                         "usp1_uart_nostreamctrl_grp";
 553                                                 sirf,function =
 554                                                         "usp1_uart_nostreamctrl";
 555                                         };
 556                                 };
 557                                 usp2_pins_a: usp2@0 {
 558                                         usp2 {
 559                                                 sirf,pins = "usp2grp";
 560                                                 sirf,function = "usp2";
 561                                         };
 562                                 };
 563                                 usp2_uart_nostreamctrl_pins_a: usp2@1 {
 564                                         usp2 {
 565                                                 sirf,pins =
 566                                                         "usp2_uart_nostreamctrl_grp";
 567                                                 sirf,function =
 568                                                         "usp2_uart_nostreamctrl";
 569                                         };
 570                                 };
 571                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 572                                         usb0_utmi_drvbus {
 573                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 574                                                 sirf,function = "usb0_utmi_drvbus";
 575                                         };
 576                                 };
 577                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 578                                         usb1_utmi_drvbus {
 579                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 580                                                 sirf,function = "usb1_utmi_drvbus";
 581                                         };
 582                                 };
 583                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 584                                         usb1_dp_dn {
 585                                                 sirf,pins = "usb1_dp_dngrp";
 586                                                 sirf,function = "usb1_dp_dn";
 587                                         };
 588                                 };
 589                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 590                                         uart1_route_io_usb1 {
 591                                                 sirf,pins = "uart1_route_io_usb1grp";
 592                                                 sirf,function = "uart1_route_io_usb1";
 593                                         };
 594                                 };
 595                                 warm_rst_pins_a: warm_rst@0 {
 596                                         warm_rst {
 597                                                 sirf,pins = "warm_rstgrp";
 598                                                 sirf,function = "warm_rst";
 599                                         };
 600                                 };
 601                                 pulse_count_pins_a: pulse_count@0 {
 602                                         pulse_count {
 603                                                 sirf,pins = "pulse_countgrp";
 604                                                 sirf,function = "pulse_count";
 605                                         };
 606                                 };
 607                                 cko0_pins_a: cko0@0 {
 608                                         cko0 {
 609                                                 sirf,pins = "cko0grp";
 610                                                 sirf,function = "cko0";
 611                                         };
 612                                 };
 613                                 cko1_pins_a: cko1@0 {
 614                                         cko1 {
 615                                                 sirf,pins = "cko1grp";
 616                                                 sirf,function = "cko1";
 617                                         };
 618                                 };
 619                         };
 620
 621                         pwm@b0130000 {
 622                                 compatible = "sirf,prima2-pwm";
 623                                 reg = <0xb0130000 0x10000>;
 624                                 clocks = <&clks 21>;
 625                         };
 626
 627                         efusesys@b0140000 {
 628                                 compatible = "sirf,prima2-efuse";
 629                                 reg = <0xb0140000 0x10000>;
 630                                 clocks = <&clks 22>;
 631                         };
 632
 633                         pulsec@b0150000 {
 634                                 compatible = "sirf,prima2-pulsec";
 635                                 reg = <0xb0150000 0x10000>;
 636                                 interrupts = <48>;
 637                                 clocks = <&clks 23>;
 638                         };
 639
 640                         pci-iobg {
 641                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 642                                 #address-cells = <1>;
 643                                 #size-cells = <1>;
 644                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 645
 646                                 sd0: sdhci@56000000 {
 647                                         cell-index = <0>;
 648                                         compatible = "sirf,prima2-sdhc";
 649                                         reg = <0x56000000 0x100000>;
 650                                         interrupts = <38>;
 651                                 };
 652
 653                                 sd1: sdhci@56100000 {
 654                                         cell-index = <1>;
 655                                         compatible = "sirf,prima2-sdhc";
 656                                         reg = <0x56100000 0x100000>;
 657                                         interrupts = <38>;
 658                                 };
 659
 660                                 sd2: sdhci@56200000 {
 661                                         cell-index = <2>;
 662                                         compatible = "sirf,prima2-sdhc";
 663                                         reg = <0x56200000 0x100000>;
 664                                         interrupts = <23>;
 665                                 };
 666
 667                                 sd3: sdhci@56300000 {
 668                                         cell-index = <3>;
 669                                         compatible = "sirf,prima2-sdhc";
 670                                         reg = <0x56300000 0x100000>;
 671                                         interrupts = <23>;
 672                                 };
 673
 674                                 sd4: sdhci@56400000 {
 675                                         cell-index = <4>;
 676                                         compatible = "sirf,prima2-sdhc";
 677                                         reg = <0x56400000 0x100000>;
 678                                         interrupts = <39>;
 679                                 };
 680
 681                                 sd5: sdhci@56500000 {
 682                                         cell-index = <5>;
 683                                         compatible = "sirf,prima2-sdhc";
 684                                         reg = <0x56500000 0x100000>;
 685                                         interrupts = <39>;
 686                                 };
 687
 688                                 pci-copy@57900000 {
 689                                         compatible = "sirf,prima2-pcicp";
 690                                         reg = <0x57900000 0x100000>;
 691                                         interrupts = <40>;
 692                                 };
 693
 694                                 rom-interface@57a00000 {
 695                                         compatible = "sirf,prima2-romif";
 696                                         reg = <0x57a00000 0x100000>;
 697                                 };
 698                         };
 699                 };
 700
 701                 rtc-iobg {
 702                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 703                         #address-cells = <1>;
 704                         #size-cells = <1>;
 705                         reg = <0x80030000 0x10000>;
 706
 707                         gpsrtc@1000 {
 708                                 compatible = "sirf,prima2-gpsrtc";
 709                                 reg = <0x1000 0x1000>;
 710                                 interrupts = <55 56 57>;
 711                         };
 712
 713                         sysrtc@2000 {
 714                                 compatible = "sirf,prima2-sysrtc";
 715                                 reg = <0x2000 0x1000>;
 716                                 interrupts = <52 53 54>;
 717                         };
 718
 719                         pwrc@3000 {
 720                                 compatible = "sirf,prima2-pwrc";
 721                                 reg = <0x3000 0x1000>;
 722                                 interrupts = <32>;
 723                         };
 724                 };
 725
 726                 uus-iobg {
 727                         compatible = "simple-bus";
 728                         #address-cells = <1>;
 729                         #size-cells = <1>;
 730                         ranges = <0xb8000000 0xb8000000 0x40000>;
 731
 732                         usb0: usb@b00e0000 {
 733                                 compatible = "chipidea,ci13611a-prima2";
 734                                 reg = <0xb8000000 0x10000>;
 735                                 interrupts = <10>;
 736                                 clocks = <&clks 40>;
 737                         };
 738
 739                         usb1: usb@b00f0000 {
 740                                 compatible = "chipidea,ci13611a-prima2";
 741                                 reg = <0xb8010000 0x10000>;
 742                                 interrupts = <11>;
 743                                 clocks = <&clks 41>;
 744                         };
 745
 746                         sata@b00f0000 {
 747                                 compatible = "synopsys,dwc-ahsata";
 748                                 reg = <0xb8020000 0x10000>;
 749                                 interrupts = <37>;
 750                         };
 751
 752                         security@b00f0000 {
 753                                 compatible = "sirf,prima2-security";
 754                                 reg = <0xb8030000 0x10000>;
 755                                 interrupts = <42>;
 756                                 clocks = <&clks 7>;
 757                         };
 758                 };
 759         };
 760 };