arch/arm/boot/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "ti,omap3430", "ti,omap3";
  19         interrupt-parent = <&intc>;
  20
  21         aliases {
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 serial0 = &uart1;
  26                 serial1 = &uart2;
  27                 serial2 = &uart3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a8";
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38
  39                         clocks = <&dpll1_ck>;
  40                         clock-names = "cpu";
  41
  42                         clock-latency = <300000>; /* From omap-cpufreq driver */
  43                 };
  44         };
  45
  46         pmu {
  47                 compatible = "arm,cortex-a8-pmu";
  48                 reg = <0x54000000 0x800000>;
  49                 interrupts = <3>;
  50                 ti,hwmods = "debugss";
  51         };
  52
  53         /*
  54          * The soc node represents the soc top level view. It is used for IPs
  55          * that are not memory mapped in the MPU view or for the MPU itself.
  56          */
  57         soc {
  58                 compatible = "ti,omap-infra";
  59                 mpu {
  60                         compatible = "ti,omap3-mpu";
  61                         ti,hwmods = "mpu";
  62                 };
  63
  64                 iva: iva {
  65                         compatible = "ti,iva2.2";
  66                         ti,hwmods = "iva";
  67
  68                         dsp {
  69                                 compatible = "ti,omap3-c64";
  70                         };
  71                 };
  72         };
  73
  74         /*
  75          * XXX: Use a flat representation of the OMAP3 interconnect.
  76          * The real OMAP interconnect network is quite complex.
  77          * Since it will not bring real advantage to represent that in DT for
  78          * the moment, just use a fake OCP bus entry to represent the whole bus
  79          * hierarchy.
  80          */
  81         ocp {
  82                 compatible = "ti,omap3-l3-smx", "simple-bus";
  83                 reg = <0x68000000 0x10000>;
  84                 interrupts = <9 10>;
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 ranges;
  88                 ti,hwmods = "l3_main";
  89
  90                 l4_core: l4@48000000 {
  91                         compatible = "ti,omap3-l4-core", "simple-bus";
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         ranges = <0 0x48000000 0x1000000>;
  95
  96                         scm: scm@2000 {
  97                                 compatible = "ti,omap3-scm", "simple-bus";
  98                                 reg = <0x2000 0x2000>;
  99                                 #address-cells = <1>;
 100                                 #size-cells = <1>;
 101                                 ranges = <0 0x2000 0x2000>;
 102
 103                                 omap3_pmx_core: pinmux@30 {
 104                                         compatible = "ti,omap3-padconf",
 105                                                      "pinctrl-single";
 106                                         reg = <0x30 0x238>;
 107                                         #address-cells = <1>;
 108                                         #size-cells = <0>;
 109                                         #interrupt-cells = <1>;
 110                                         interrupt-controller;
 111                                         pinctrl-single,register-width = <16>;
 112                                         pinctrl-single,function-mask = <0xff1f>;
 113                                 };
 114
 115                                 scm_conf: scm_conf@270 {
 116                                         compatible = "syscon";
 117                                         reg = <0x270 0x330>;
 118                                         #address-cells = <1>;
 119                                         #size-cells = <1>;
 120
 121                                         scm_clocks: clocks {
 122                                                 #address-cells = <1>;
 123                                                 #size-cells = <0>;
 124                                         };
 125                                 };
 126
 127                                 scm_clockdomains: clockdomains {
 128                                 };
 129
 130                                 omap3_pmx_wkup: pinmux@a00 {
 131                                         compatible = "ti,omap3-padconf",
 132                                                      "pinctrl-single";
 133                                         reg = <0xa00 0x5c>;
 134                                         #address-cells = <1>;
 135                                         #size-cells = <0>;
 136                                         #interrupt-cells = <1>;
 137                                         interrupt-controller;
 138                                         pinctrl-single,register-width = <16>;
 139                                         pinctrl-single,function-mask = <0xff1f>;
 140                                 };
 141                         };
 142                 };
 143
 144                 aes: aes@480c5000 {
 145                         compatible = "ti,omap3-aes";
 146                         ti,hwmods = "aes";
 147                         reg = <0x480c5000 0x50>;
 148                         interrupts = <0>;
 149                         dmas = <&sdma 65 &sdma 66>;
 150                         dma-names = "tx", "rx";
 151                 };
 152
 153                 prm: prm@48306000 {
 154                         compatible = "ti,omap3-prm";
 155                         reg = <0x48306000 0x4000>;
 156                         interrupts = <11>;
 157
 158                         prm_clocks: clocks {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <0>;
 161                         };
 162
 163                         prm_clockdomains: clockdomains {
 164                         };
 165                 };
 166
 167                 cm: cm@48004000 {
 168                         compatible = "ti,omap3-cm";
 169                         reg = <0x48004000 0x4000>;
 170
 171                         cm_clocks: clocks {
 172                                 #address-cells = <1>;
 173                                 #size-cells = <0>;
 174                         };
 175
 176                         cm_clockdomains: clockdomains {
 177                         };
 178                 };
 179
 180                 counter32k: counter@48320000 {
 181                         compatible = "ti,omap-counter32k";
 182                         reg = <0x48320000 0x20>;
 183                         ti,hwmods = "counter_32k";
 184                 };
 185
 186                 intc: interrupt-controller@48200000 {
 187                         compatible = "ti,omap3-intc";
 188                         interrupt-controller;
 189                         #interrupt-cells = <1>;
 190                         reg = <0x48200000 0x1000>;
 191                 };
 192
 193                 sdma: dma-controller@48056000 {
 194                         compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
 195                         reg = <0x48056000 0x1000>;
 196                         interrupts = <12>,
 197                                      <13>,
 198                                      <14>,
 199                                      <15>;
 200                         #dma-cells = <1>;
 201                         dma-channels = <32>;
 202                         dma-requests = <96>;
 203                 };
 204
 205                 pbias_regulator: pbias_regulator {
 206                         compatible = "ti,pbias-omap";
 207                         reg = <0x2b0 0x4>;
 208                         syscon = <&scm_conf>;
 209                         pbias_mmc_reg: pbias_mmc_omap2430 {
 210                                 regulator-name = "pbias_mmc_omap2430";
 211                                 regulator-min-microvolt = <1800000>;
 212                                 regulator-max-microvolt = <3000000>;
 213                         };
 214                 };
 215
 216                 gpio1: gpio@48310000 {
 217                         compatible = "ti,omap3-gpio";
 218                         reg = <0x48310000 0x200>;
 219                         interrupts = <29>;
 220                         ti,hwmods = "gpio1";
 221                         ti,gpio-always-on;
 222                         gpio-controller;
 223                         #gpio-cells = <2>;
 224                         interrupt-controller;
 225                         #interrupt-cells = <2>;
 226                 };
 227
 228                 gpio2: gpio@49050000 {
 229                         compatible = "ti,omap3-gpio";
 230                         reg = <0x49050000 0x200>;
 231                         interrupts = <30>;
 232                         ti,hwmods = "gpio2";
 233                         gpio-controller;
 234                         #gpio-cells = <2>;
 235                         interrupt-controller;
 236                         #interrupt-cells = <2>;
 237                 };
 238
 239                 gpio3: gpio@49052000 {
 240                         compatible = "ti,omap3-gpio";
 241                         reg = <0x49052000 0x200>;
 242                         interrupts = <31>;
 243                         ti,hwmods = "gpio3";
 244                         gpio-controller;
 245                         #gpio-cells = <2>;
 246                         interrupt-controller;
 247                         #interrupt-cells = <2>;
 248                 };
 249
 250                 gpio4: gpio@49054000 {
 251                         compatible = "ti,omap3-gpio";
 252                         reg = <0x49054000 0x200>;
 253                         interrupts = <32>;
 254                         ti,hwmods = "gpio4";
 255                         gpio-controller;
 256                         #gpio-cells = <2>;
 257                         interrupt-controller;
 258                         #interrupt-cells = <2>;
 259                 };
 260
 261                 gpio5: gpio@49056000 {
 262                         compatible = "ti,omap3-gpio";
 263                         reg = <0x49056000 0x200>;
 264                         interrupts = <33>;
 265                         ti,hwmods = "gpio5";
 266                         gpio-controller;
 267                         #gpio-cells = <2>;
 268                         interrupt-controller;
 269                         #interrupt-cells = <2>;
 270                 };
 271
 272                 gpio6: gpio@49058000 {
 273                         compatible = "ti,omap3-gpio";
 274                         reg = <0x49058000 0x200>;
 275                         interrupts = <34>;
 276                         ti,hwmods = "gpio6";
 277                         gpio-controller;
 278                         #gpio-cells = <2>;
 279                         interrupt-controller;
 280                         #interrupt-cells = <2>;
 281                 };
 282
 283                 uart1: serial@4806a000 {
 284                         compatible = "ti,omap3-uart";
 285                         reg = <0x4806a000 0x2000>;
 286                         interrupts-extended = <&intc 72>;
 287                         dmas = <&sdma 49 &sdma 50>;
 288                         dma-names = "tx", "rx";
 289                         ti,hwmods = "uart1";
 290                         clock-frequency = <48000000>;
 291                 };
 292
 293                 uart2: serial@4806c000 {
 294                         compatible = "ti,omap3-uart";
 295                         reg = <0x4806c000 0x400>;
 296                         interrupts-extended = <&intc 73>;
 297                         dmas = <&sdma 51 &sdma 52>;
 298                         dma-names = "tx", "rx";
 299                         ti,hwmods = "uart2";
 300                         clock-frequency = <48000000>;
 301                 };
 302
 303                 uart3: serial@49020000 {
 304                         compatible = "ti,omap3-uart";
 305                         reg = <0x49020000 0x400>;
 306                         interrupts-extended = <&intc 74>;
 307                         dmas = <&sdma 53 &sdma 54>;
 308                         dma-names = "tx", "rx";
 309                         ti,hwmods = "uart3";
 310                         clock-frequency = <48000000>;
 311                 };
 312
 313                 i2c1: i2c@48070000 {
 314                         compatible = "ti,omap3-i2c";
 315                         reg = <0x48070000 0x80>;
 316                         interrupts = <56>;
 317                         dmas = <&sdma 27 &sdma 28>;
 318                         dma-names = "tx", "rx";
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         ti,hwmods = "i2c1";
 322                 };
 323
 324                 i2c2: i2c@48072000 {
 325                         compatible = "ti,omap3-i2c";
 326                         reg = <0x48072000 0x80>;
 327                         interrupts = <57>;
 328                         dmas = <&sdma 29 &sdma 30>;
 329                         dma-names = "tx", "rx";
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         ti,hwmods = "i2c2";
 333                 };
 334
 335                 i2c3: i2c@48060000 {
 336                         compatible = "ti,omap3-i2c";
 337                         reg = <0x48060000 0x80>;
 338                         interrupts = <61>;
 339                         dmas = <&sdma 25 &sdma 26>;
 340                         dma-names = "tx", "rx";
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         ti,hwmods = "i2c3";
 344                 };
 345
 346                 mailbox: mailbox@48094000 {
 347                         compatible = "ti,omap3-mailbox";
 348                         ti,hwmods = "mailbox";
 349                         reg = <0x48094000 0x200>;
 350                         interrupts = <26>;
 351                         #mbox-cells = <1>;
 352                         ti,mbox-num-users = <2>;
 353                         ti,mbox-num-fifos = <2>;
 354                         mbox_dsp: dsp {
 355                                 ti,mbox-tx = <0 0 0>;
 356                                 ti,mbox-rx = <1 0 0>;
 357                         };
 358                 };
 359
 360                 mcspi1: spi@48098000 {
 361                         compatible = "ti,omap2-mcspi";
 362                         reg = <0x48098000 0x100>;
 363                         interrupts = <65>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         ti,hwmods = "mcspi1";
 367                         ti,spi-num-cs = <4>;
 368                         dmas = <&sdma 35>,
 369                                <&sdma 36>,
 370                                <&sdma 37>,
 371                                <&sdma 38>,
 372                                <&sdma 39>,
 373                                <&sdma 40>,
 374                                <&sdma 41>,
 375                                <&sdma 42>;
 376                         dma-names = "tx0", "rx0", "tx1", "rx1",
 377                                     "tx2", "rx2", "tx3", "rx3";
 378                 };
 379
 380                 mcspi2: spi@4809a000 {
 381                         compatible = "ti,omap2-mcspi";
 382                         reg = <0x4809a000 0x100>;
 383                         interrupts = <66>;
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         ti,hwmods = "mcspi2";
 387                         ti,spi-num-cs = <2>;
 388                         dmas = <&sdma 43>,
 389                                <&sdma 44>,
 390                                <&sdma 45>,
 391                                <&sdma 46>;
 392                         dma-names = "tx0", "rx0", "tx1", "rx1";
 393                 };
 394
 395                 mcspi3: spi@480b8000 {
 396                         compatible = "ti,omap2-mcspi";
 397                         reg = <0x480b8000 0x100>;
 398                         interrupts = <91>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         ti,hwmods = "mcspi3";
 402                         ti,spi-num-cs = <2>;
 403                         dmas = <&sdma 15>,
 404                                <&sdma 16>,
 405                                <&sdma 23>,
 406                                <&sdma 24>;
 407                         dma-names = "tx0", "rx0", "tx1", "rx1";
 408                 };
 409
 410                 mcspi4: spi@480ba000 {
 411                         compatible = "ti,omap2-mcspi";
 412                         reg = <0x480ba000 0x100>;
 413                         interrupts = <48>;
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         ti,hwmods = "mcspi4";
 417                         ti,spi-num-cs = <1>;
 418                         dmas = <&sdma 70>, <&sdma 71>;
 419                         dma-names = "tx0", "rx0";
 420                 };
 421
 422                 hdqw1w: 1w@480b2000 {
 423                         compatible = "ti,omap3-1w";
 424                         reg = <0x480b2000 0x1000>;
 425                         interrupts = <58>;
 426                         ti,hwmods = "hdq1w";
 427                 };
 428
 429                 mmc1: mmc@4809c000 {
 430                         compatible = "ti,omap3-hsmmc";
 431                         reg = <0x4809c000 0x200>;
 432                         interrupts = <83>;
 433                         ti,hwmods = "mmc1";
 434                         ti,dual-volt;
 435                         dmas = <&sdma 61>, <&sdma 62>;
 436                         dma-names = "tx", "rx";
 437                         pbias-supply = <&pbias_mmc_reg>;
 438                 };
 439
 440                 mmc2: mmc@480b4000 {
 441                         compatible = "ti,omap3-hsmmc";
 442                         reg = <0x480b4000 0x200>;
 443                         interrupts = <86>;
 444                         ti,hwmods = "mmc2";
 445                         dmas = <&sdma 47>, <&sdma 48>;
 446                         dma-names = "tx", "rx";
 447                 };
 448
 449                 mmc3: mmc@480ad000 {
 450                         compatible = "ti,omap3-hsmmc";
 451                         reg = <0x480ad000 0x200>;
 452                         interrupts = <94>;
 453                         ti,hwmods = "mmc3";
 454                         dmas = <&sdma 77>, <&sdma 78>;
 455                         dma-names = "tx", "rx";
 456                 };
 457
 458                 mmu_isp: mmu@480bd400 {
 459                         #iommu-cells = <0>;
 460                         compatible = "ti,omap2-iommu";
 461                         reg = <0x480bd400 0x80>;
 462                         interrupts = <24>;
 463                         ti,hwmods = "mmu_isp";
 464                         ti,#tlb-entries = <8>;
 465                 };
 466
 467                 mmu_iva: mmu@5d000000 {
 468                         #iommu-cells = <0>;
 469                         compatible = "ti,omap2-iommu";
 470                         reg = <0x5d000000 0x80>;
 471                         interrupts = <28>;
 472                         ti,hwmods = "mmu_iva";
 473                         status = "disabled";
 474                 };
 475
 476                 wdt2: wdt@48314000 {
 477                         compatible = "ti,omap3-wdt";
 478                         reg = <0x48314000 0x80>;
 479                         ti,hwmods = "wd_timer2";
 480                 };
 481
 482                 mcbsp1: mcbsp@48074000 {
 483                         compatible = "ti,omap3-mcbsp";
 484                         reg = <0x48074000 0xff>;
 485                         reg-names = "mpu";
 486                         interrupts = <16>, /* OCP compliant interrupt */
 487                                      <59>, /* TX interrupt */
 488                                      <60>; /* RX interrupt */
 489                         interrupt-names = "common", "tx", "rx";
 490                         ti,buffer-size = <128>;
 491                         ti,hwmods = "mcbsp1";
 492                         dmas = <&sdma 31>,
 493                                <&sdma 32>;
 494                         dma-names = "tx", "rx";
 495                         status = "disabled";
 496                 };
 497
 498                 mcbsp2: mcbsp@49022000 {
 499                         compatible = "ti,omap3-mcbsp";
 500                         reg = <0x49022000 0xff>,
 501                               <0x49028000 0xff>;
 502                         reg-names = "mpu", "sidetone";
 503                         interrupts = <17>, /* OCP compliant interrupt */
 504                                      <62>, /* TX interrupt */
 505                                      <63>, /* RX interrupt */
 506                                      <4>;  /* Sidetone */
 507                         interrupt-names = "common", "tx", "rx", "sidetone";
 508                         ti,buffer-size = <1280>;
 509                         ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 510                         dmas = <&sdma 33>,
 511                                <&sdma 34>;
 512                         dma-names = "tx", "rx";
 513                         status = "disabled";
 514                 };
 515
 516                 mcbsp3: mcbsp@49024000 {
 517                         compatible = "ti,omap3-mcbsp";
 518                         reg = <0x49024000 0xff>,
 519                               <0x4902a000 0xff>;
 520                         reg-names = "mpu", "sidetone";
 521                         interrupts = <22>, /* OCP compliant interrupt */
 522                                      <89>, /* TX interrupt */
 523                                      <90>, /* RX interrupt */
 524                                      <5>;  /* Sidetone */
 525                         interrupt-names = "common", "tx", "rx", "sidetone";
 526                         ti,buffer-size = <128>;
 527                         ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 528                         dmas = <&sdma 17>,
 529                                <&sdma 18>;
 530                         dma-names = "tx", "rx";
 531                         status = "disabled";
 532                 };
 533
 534                 mcbsp4: mcbsp@49026000 {
 535                         compatible = "ti,omap3-mcbsp";
 536                         reg = <0x49026000 0xff>;
 537                         reg-names = "mpu";
 538                         interrupts = <23>, /* OCP compliant interrupt */
 539                                      <54>, /* TX interrupt */
 540                                      <55>; /* RX interrupt */
 541                         interrupt-names = "common", "tx", "rx";
 542                         ti,buffer-size = <128>;
 543                         ti,hwmods = "mcbsp4";
 544                         dmas = <&sdma 19>,
 545                                <&sdma 20>;
 546                         dma-names = "tx", "rx";
 547                         status = "disabled";
 548                 };
 549
 550                 mcbsp5: mcbsp@48096000 {
 551                         compatible = "ti,omap3-mcbsp";
 552                         reg = <0x48096000 0xff>;
 553                         reg-names = "mpu";
 554                         interrupts = <27>, /* OCP compliant interrupt */
 555                                      <81>, /* TX interrupt */
 556                                      <82>; /* RX interrupt */
 557                         interrupt-names = "common", "tx", "rx";
 558                         ti,buffer-size = <128>;
 559                         ti,hwmods = "mcbsp5";
 560                         dmas = <&sdma 21>,
 561                                <&sdma 22>;
 562                         dma-names = "tx", "rx";
 563                         status = "disabled";
 564                 };
 565
 566                 sham: sham@480c3000 {
 567                         compatible = "ti,omap3-sham";
 568                         ti,hwmods = "sham";
 569                         reg = <0x480c3000 0x64>;
 570                         interrupts = <49>;
 571                         dmas = <&sdma 69>;
 572                         dma-names = "rx";
 573                 };
 574
 575                 smartreflex_core: smartreflex@480cb000 {
 576                         compatible = "ti,omap3-smartreflex-core";
 577                         ti,hwmods = "smartreflex_core";
 578                         reg = <0x480cb000 0x400>;
 579                         interrupts = <19>;
 580                 };
 581
 582                 smartreflex_mpu_iva: smartreflex@480c9000 {
 583                         compatible = "ti,omap3-smartreflex-iva";
 584                         ti,hwmods = "smartreflex_mpu_iva";
 585                         reg = <0x480c9000 0x400>;
 586                         interrupts = <18>;
 587                 };
 588
 589                 timer1: timer@48318000 {
 590                         compatible = "ti,omap3430-timer";
 591                         reg = <0x48318000 0x400>;
 592                         interrupts = <37>;
 593                         ti,hwmods = "timer1";
 594                         ti,timer-alwon;
 595                 };
 596
 597                 timer2: timer@49032000 {
 598                         compatible = "ti,omap3430-timer";
 599                         reg = <0x49032000 0x400>;
 600                         interrupts = <38>;
 601                         ti,hwmods = "timer2";
 602                 };
 603
 604                 timer3: timer@49034000 {
 605                         compatible = "ti,omap3430-timer";
 606                         reg = <0x49034000 0x400>;
 607                         interrupts = <39>;
 608                         ti,hwmods = "timer3";
 609                 };
 610
 611                 timer4: timer@49036000 {
 612                         compatible = "ti,omap3430-timer";
 613                         reg = <0x49036000 0x400>;
 614                         interrupts = <40>;
 615                         ti,hwmods = "timer4";
 616                 };
 617
 618                 timer5: timer@49038000 {
 619                         compatible = "ti,omap3430-timer";
 620                         reg = <0x49038000 0x400>;
 621                         interrupts = <41>;
 622                         ti,hwmods = "timer5";
 623                         ti,timer-dsp;
 624                 };
 625
 626                 timer6: timer@4903a000 {
 627                         compatible = "ti,omap3430-timer";
 628                         reg = <0x4903a000 0x400>;
 629                         interrupts = <42>;
 630                         ti,hwmods = "timer6";
 631                         ti,timer-dsp;
 632                 };
 633
 634                 timer7: timer@4903c000 {
 635                         compatible = "ti,omap3430-timer";
 636                         reg = <0x4903c000 0x400>;
 637                         interrupts = <43>;
 638                         ti,hwmods = "timer7";
 639                         ti,timer-dsp;
 640                 };
 641
 642                 timer8: timer@4903e000 {
 643                         compatible = "ti,omap3430-timer";
 644                         reg = <0x4903e000 0x400>;
 645                         interrupts = <44>;
 646                         ti,hwmods = "timer8";
 647                         ti,timer-pwm;
 648                         ti,timer-dsp;
 649                 };
 650
 651                 timer9: timer@49040000 {
 652                         compatible = "ti,omap3430-timer";
 653                         reg = <0x49040000 0x400>;
 654                         interrupts = <45>;
 655                         ti,hwmods = "timer9";
 656                         ti,timer-pwm;
 657                 };
 658
 659                 timer10: timer@48086000 {
 660                         compatible = "ti,omap3430-timer";
 661                         reg = <0x48086000 0x400>;
 662                         interrupts = <46>;
 663                         ti,hwmods = "timer10";
 664                         ti,timer-pwm;
 665                 };
 666
 667                 timer11: timer@48088000 {
 668                         compatible = "ti,omap3430-timer";
 669                         reg = <0x48088000 0x400>;
 670                         interrupts = <47>;
 671                         ti,hwmods = "timer11";
 672                         ti,timer-pwm;
 673                 };
 674
 675                 timer12: timer@48304000 {
 676                         compatible = "ti,omap3430-timer";
 677                         reg = <0x48304000 0x400>;
 678                         interrupts = <95>;
 679                         ti,hwmods = "timer12";
 680                         ti,timer-alwon;
 681                         ti,timer-secure;
 682                 };
 683
 684                 usbhstll: usbhstll@48062000 {
 685                         compatible = "ti,usbhs-tll";
 686                         reg = <0x48062000 0x1000>;
 687                         interrupts = <78>;
 688                         ti,hwmods = "usb_tll_hs";
 689                 };
 690
 691                 usbhshost: usbhshost@48064000 {
 692                         compatible = "ti,usbhs-host";
 693                         reg = <0x48064000 0x400>;
 694                         ti,hwmods = "usb_host_hs";
 695                         #address-cells = <1>;
 696                         #size-cells = <1>;
 697                         ranges;
 698
 699                         usbhsohci: ohci@48064400 {
 700                                 compatible = "ti,ohci-omap3";
 701                                 reg = <0x48064400 0x400>;
 702                                 interrupt-parent = <&intc>;
 703                                 interrupts = <76>;
 704                         };
 705
 706                         usbhsehci: ehci@48064800 {
 707                                 compatible = "ti,ehci-omap";
 708                                 reg = <0x48064800 0x400>;
 709                                 interrupt-parent = <&intc>;
 710                                 interrupts = <77>;
 711                         };
 712                 };
 713
 714                 gpmc: gpmc@6e000000 {
 715                         compatible = "ti,omap3430-gpmc";
 716                         ti,hwmods = "gpmc";
 717                         reg = <0x6e000000 0x02d0>;
 718                         interrupts = <20>;
 719                         gpmc,num-cs = <8>;
 720                         gpmc,num-waitpins = <4>;
 721                         #address-cells = <2>;
 722                         #size-cells = <1>;
 723                 };
 724
 725                 usb_otg_hs: usb_otg_hs@480ab000 {
 726                         compatible = "ti,omap3-musb";
 727                         reg = <0x480ab000 0x1000>;
 728                         interrupts = <92>, <93>;
 729                         interrupt-names = "mc", "dma";
 730                         ti,hwmods = "usb_otg_hs";
 731                         multipoint = <1>;
 732                         num-eps = <16>;
 733                         ram-bits = <12>;
 734                 };
 735
 736                 dss: dss@48050000 {
 737                         compatible = "ti,omap3-dss";
 738                         reg = <0x48050000 0x200>;
 739                         status = "disabled";
 740                         ti,hwmods = "dss_core";
 741                         clocks = <&dss1_alwon_fck>;
 742                         clock-names = "fck";
 743                         #address-cells = <1>;
 744                         #size-cells = <1>;
 745                         ranges;
 746
 747                         dispc@48050400 {
 748                                 compatible = "ti,omap3-dispc";
 749                                 reg = <0x48050400 0x400>;
 750                                 interrupts = <25>;
 751                                 ti,hwmods = "dss_dispc";
 752                                 clocks = <&dss1_alwon_fck>;
 753                                 clock-names = "fck";
 754                         };
 755
 756                         dsi: encoder@4804fc00 {
 757                                 compatible = "ti,omap3-dsi";
 758                                 reg = <0x4804fc00 0x200>,
 759                                       <0x4804fe00 0x40>,
 760                                       <0x4804ff00 0x20>;
 761                                 reg-names = "proto", "phy", "pll";
 762                                 interrupts = <25>;
 763                                 status = "disabled";
 764                                 ti,hwmods = "dss_dsi1";
 765                                 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 766                                 clock-names = "fck", "sys_clk";
 767                         };
 768
 769                         rfbi: encoder@48050800 {
 770                                 compatible = "ti,omap3-rfbi";
 771                                 reg = <0x48050800 0x100>;
 772                                 status = "disabled";
 773                                 ti,hwmods = "dss_rfbi";
 774                                 clocks = <&dss1_alwon_fck>, <&dss_ick>;
 775                                 clock-names = "fck", "ick";
 776                         };
 777
 778                         venc: encoder@48050c00 {
 779                                 compatible = "ti,omap3-venc";
 780                                 reg = <0x48050c00 0x100>;
 781                                 status = "disabled";
 782                                 ti,hwmods = "dss_venc";
 783                                 clocks = <&dss_tv_fck>;
 784                                 clock-names = "fck";
 785                         };
 786                 };
 787
 788                 ssi: ssi-controller@48058000 {
 789                         compatible = "ti,omap3-ssi";
 790                         ti,hwmods = "ssi";
 791
 792                         status = "disabled";
 793
 794                         reg = <0x48058000 0x1000>,
 795                               <0x48059000 0x1000>;
 796                         reg-names = "sys",
 797                                     "gdd";
 798
 799                         interrupts = <71>;
 800                         interrupt-names = "gdd_mpu";
 801
 802                         #address-cells = <1>;
 803                         #size-cells = <1>;
 804                         ranges;
 805
 806                         ssi_port1: ssi-port@4805a000 {
 807                                 compatible = "ti,omap3-ssi-port";
 808
 809                                 reg = <0x4805a000 0x800>,
 810                                       <0x4805a800 0x800>;
 811                                 reg-names = "tx",
 812                                             "rx";
 813
 814                                 interrupt-parent = <&intc>;
 815                                 interrupts = <67>,
 816                                              <68>;
 817                         };
 818
 819                         ssi_port2: ssi-port@4805b000 {
 820                                 compatible = "ti,omap3-ssi-port";
 821
 822                                 reg = <0x4805b000 0x800>,
 823                                       <0x4805b800 0x800>;
 824                                 reg-names = "tx",
 825                                             "rx";
 826
 827                                 interrupt-parent = <&intc>;
 828                                 interrupts = <69>,
 829                                              <70>;
 830                         };
 831                 };
 832         };
 833 };
 834
 835 /include/ "omap3xxx-clocks.dtsi"