arch/arm/boot/dts/keystone.dts

   1 /*
   2  * Copyright 2013 Texas Instruments, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         model = "Texas Instruments Keystone 2 SoC";
  16         compatible =  "ti,keystone-evm";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 serial0 = &uart0;
  23         };
  24
  25         memory {
  26                 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 interrupt-parent = <&gic>;
  34
  35                 cpu@0 {
  36                         compatible = "arm,cortex-a15";
  37                         device_type = "cpu";
  38                         reg = <0>;
  39                 };
  40
  41                 cpu@1 {
  42                         compatible = "arm,cortex-a15";
  43                         device_type = "cpu";
  44                         reg = <1>;
  45                 };
  46
  47                 cpu@2 {
  48                         compatible = "arm,cortex-a15";
  49                         device_type = "cpu";
  50                         reg = <2>;
  51                 };
  52
  53                 cpu@3 {
  54                         compatible = "arm,cortex-a15";
  55                         device_type = "cpu";
  56                         reg = <3>;
  57                 };
  58         };
  59
  60         gic: interrupt-controller {
  61                 compatible = "arm,cortex-a15-gic";
  62                 #interrupt-cells = <3>;
  63                 #size-cells = <0>;
  64                 #address-cells = <1>;
  65                 interrupt-controller;
  66                 reg = <0x0 0x02561000 0x0 0x1000>,
  67                       <0x0 0x02562000 0x0 0x2000>;
  68         };
  69
  70         timer {
  71                 compatible = "arm,armv7-timer";
  72                 interrupts =
  73                         <GIC_PPI 13
  74                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  75                         <GIC_PPI 14
  76                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  77                         <GIC_PPI 11
  78                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  79                         <GIC_PPI 10
  80                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  81         };
  82
  83         pmu {
  84                 compatible = "arm,cortex-a15-pmu";
  85                 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
  86                              <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
  87                              <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
  88                              <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
  89         };
  90
  91         soc {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 compatible = "ti,keystone","simple-bus";
  95                 interrupt-parent = <&gic>;
  96                 ranges = <0x0 0x0 0x0 0xc0000000>;
  97
  98                 rstctrl: reset-controller {
  99                         compatible = "ti,keystone-reset";
 100                         reg = <0x023100e8 4>;   /* pll reset control reg */
 101                 };
 102
 103                 /include/ "keystone-clocks.dtsi"
 104
 105                 uart0: serial@02530c00 {
 106                         compatible = "ns16550a";
 107                         current-speed = <115200>;
 108                         reg-shift = <2>;
 109                         reg-io-width = <4>;
 110                         reg = <0x02530c00 0x100>;
 111                         clocks  = <&clkuart0>;
 112                         interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
 113                 };
 114
 115                 uart1:  serial@02531000 {
 116                         compatible = "ns16550a";
 117                         current-speed = <115200>;
 118                         reg-shift = <2>;
 119                         reg-io-width = <4>;
 120                         reg = <0x02531000 0x100>;
 121                         clocks  = <&clkuart1>;
 122                         interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
 123                 };
 124
 125                 i2c0: i2c@2530000 {
 126                         compatible = "ti,davinci-i2c";
 127                         reg = <0x02530000 0x400>;
 128                         clock-frequency = <100000>;
 129                         clocks = <&clki2c>;
 130                         interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133
 134                         dtt@50 {
 135                                 compatible = "at,24c1024";
 136                                 reg = <0x50>;
 137                         };
 138                 };
 139
 140                 i2c1: i2c@2530400 {
 141                         compatible = "ti,davinci-i2c";
 142                         reg = <0x02530400 0x400>;
 143                         clock-frequency = <100000>;
 144                         clocks = <&clki2c>;
 145                         interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
 146                 };
 147
 148                 i2c2: i2c@2530800 {
 149                         compatible = "ti,davinci-i2c";
 150                         reg = <0x02530800 0x400>;
 151                         clock-frequency = <100000>;
 152                         clocks = <&clki2c>;
 153                         interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
 154                 };
 155
 156                 spi0: spi@21000400 {
 157                         compatible = "ti,dm6441-spi";
 158                         reg = <0x21000400 0x200>;
 159                         num-cs = <4>;
 160                         ti,davinci-spi-intr-line = <0>;
 161                         interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
 162                         clocks = <&clkspi>;
 163                 };
 164
 165                 spi1: spi@21000600 {
 166                         compatible = "ti,dm6441-spi";
 167                         reg = <0x21000600 0x200>;
 168                         num-cs = <4>;
 169                         ti,davinci-spi-intr-line = <0>;
 170                         interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
 171                         clocks = <&clkspi>;
 172                 };
 173
 174                 spi2: spi@21000800 {
 175                         compatible = "ti,dm6441-spi";
 176                         reg = <0x21000800 0x200>;
 177                         num-cs = <4>;
 178                         ti,davinci-spi-intr-line = <0>;
 179                         interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
 180                         clocks = <&clkspi>;
 181                 };
 182         };
 183 };