arch/arm/boot/dts/integratorcp.dts

   1 /*
   2  * Device Tree for the ARM Integrator/CP platform
   3  */
   4
   5 /dts-v1/;
   6 /include/ "integrator.dtsi"
   7
   8 / {
   9         model = "ARM Integrator/CP";
  10         compatible = "arm,integrator-cp";
  11
  12         chosen {
  13                 bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
  14         };
  15
  16         syscon {
  17                 compatible = "arm,integrator-cp-syscon";
  18                 reg = <0xcb000000 0x100>;
  19         };
  20
  21         timer0: timer@13000000 {
  22                 /* TIMER0 runs @ 25MHz */
  23                 compatible = "arm,integrator-cp-timer";
  24                 status = "disabled";
  25         };
  26
  27         timer1: timer@13000100 {
  28                 /* TIMER1 runs @ 1MHz */
  29                 compatible = "arm,integrator-cp-timer";
  30         };
  31
  32         timer2: timer@13000200 {
  33                 /* TIMER2 runs @ 1MHz */
  34                 compatible = "arm,integrator-cp-timer";
  35         };
  36
  37         pic: pic@14000000 {
  38                 valid-mask = <0x1fc003ff>;
  39         };
  40
  41         cic: cic@10000040 {
  42                 compatible = "arm,versatile-fpga-irq";
  43                 #interrupt-cells = <1>;
  44                 interrupt-controller;
  45                 reg = <0x10000040 0x100>;
  46                 clear-mask = <0xffffffff>;
  47                 valid-mask = <0x00000007>;
  48         };
  49
  50         sic: sic@ca000000 {
  51                 compatible = "arm,versatile-fpga-irq";
  52                 #interrupt-cells = <1>;
  53                 interrupt-controller;
  54                 reg = <0xca000000 0x100>;
  55                 clear-mask = <0x00000fff>;
  56                 valid-mask = <0x00000fff>;
  57         };
  58
  59         ethernet@c8000000 {
  60                 compatible = "smsc,lan91c111";
  61                 reg = <0xc8000000 0x10>;
  62                 interrupt-parent = <&pic>;
  63                 interrupts = <27>;
  64         };
  65
  66         fpga {
  67                 /*
  68                  * These PrimeCells are at the same location and using
  69                  * the same interrupts in all Integrators, but in the CP
  70                  * slightly newer versions are deployed.
  71                  */
  72                 rtc@15000000 {
  73                         compatible = "arm,pl031", "arm,primecell";
  74                 };
  75
  76                 uart@16000000 {
  77                         compatible = "arm,pl011", "arm,primecell";
  78                 };
  79
  80                 uart@17000000 {
  81                         compatible = "arm,pl011", "arm,primecell";
  82                 };
  83
  84                 kmi@18000000 {
  85                         compatible = "arm,pl050", "arm,primecell";
  86                 };
  87
  88                 kmi@19000000 {
  89                         compatible = "arm,pl050", "arm,primecell";
  90                 };
  91
  92                 /*
  93                  * These PrimeCells are only available on the Integrator/CP
  94                  */
  95                 mmc@1c000000 {
  96                         compatible = "arm,pl180", "arm,primecell";
  97                         reg = <0x1c000000 0x1000>;
  98                         interrupts = <23 24>;
  99                         max-frequency = <515633>;
 100                 };
 101
 102                 aaci@1d000000 {
 103                         compatible = "arm,pl041", "arm,primecell";
 104                         reg = <0x1d000000 0x1000>;
 105                         interrupts = <25>;
 106                 };
 107
 108                 clcd@c0000000 {
 109                         compatible = "arm,pl110", "arm,primecell";
 110                         reg = <0xC0000000 0x1000>;
 111                         interrupts = <22>;
 112                 };
 113         };
 114 };