arch/arm/boot/dts/exynos5440.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5440 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         compatible = "samsung,exynos5440";
  16
  17         interrupt-parent = <&gic>;
  18
  19         aliases {
  20                 spi0 = &spi_0;
  21                 tmuctrl0 = &tmuctrl_0;
  22                 tmuctrl1 = &tmuctrl_1;
  23                 tmuctrl2 = &tmuctrl_2;
  24         };
  25
  26         clock: clock-controller@160000 {
  27                 compatible = "samsung,exynos5440-clock";
  28                 reg = <0x160000 0x1000>;
  29                 #clock-cells = <1>;
  30         };
  31
  32         gic:interrupt-controller@2E0000 {
  33                 compatible = "arm,cortex-a15-gic";
  34                 #interrupt-cells = <3>;
  35                 interrupt-controller;
  36                 reg =   <0x2E1000 0x1000>,
  37                         <0x2E2000 0x1000>,
  38                         <0x2E4000 0x2000>,
  39                         <0x2E6000 0x2000>;
  40                 interrupts = <1 9 0xf04>;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0>;
  51                 };
  52                 cpu@1 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <1>;
  56                 };
  57                 cpu@2 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a15";
  60                         reg = <2>;
  61                 };
  62                 cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <3>;
  66                 };
  67         };
  68
  69         arm-pmu {
  70                 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
  71                 interrupts = <0 52 4>,
  72                              <0 53 4>,
  73                              <0 54 4>,
  74                              <0 55 4>;
  75         };
  76
  77         timer {
  78                 compatible = "arm,cortex-a15-timer",
  79                              "arm,armv7-timer";
  80                 interrupts = <1 13 0xf08>,
  81                              <1 14 0xf08>,
  82                              <1 11 0xf08>,
  83                              <1 10 0xf08>;
  84                 clock-frequency = <50000000>;
  85         };
  86
  87         cpufreq@160000 {
  88                 compatible = "samsung,exynos5440-cpufreq";
  89                 reg = <0x160000 0x1000>;
  90                 interrupts = <0 57 0>;
  91                 operating-points = <
  92                                 /* KHz    uV */
  93                                 1500000 1100000
  94                                 1400000 1075000
  95                                 1300000 1050000
  96                                 1200000 1025000
  97                                 1100000 1000000
  98                                 1000000 975000
  99                                 900000  950000
 100                                 800000  925000
 101                 >;
 102         };
 103
 104         serial@B0000 {
 105                 compatible = "samsung,exynos4210-uart";
 106                 reg = <0xB0000 0x1000>;
 107                 interrupts = <0 2 0>;
 108                 clocks = <&clock 21>, <&clock 21>;
 109                 clock-names = "uart", "clk_uart_baud0";
 110         };
 111
 112         serial@C0000 {
 113                 compatible = "samsung,exynos4210-uart";
 114                 reg = <0xC0000 0x1000>;
 115                 interrupts = <0 3 0>;
 116                 clocks = <&clock 21>, <&clock 21>;
 117                 clock-names = "uart", "clk_uart_baud0";
 118         };
 119
 120         spi_0: spi@D0000 {
 121                 compatible = "samsung,exynos5440-spi";
 122                 reg = <0xD0000 0x100>;
 123                 interrupts = <0 4 0>;
 124                 #address-cells = <1>;
 125                 #size-cells = <0>;
 126                 samsung,spi-src-clk = <0>;
 127                 num-cs = <1>;
 128                 clocks = <&clock 21>, <&clock 16>;
 129                 clock-names = "spi", "spi_busclk0";
 130         };
 131
 132         pin_ctrl: pinctrl {
 133                 compatible = "samsung,exynos5440-pinctrl";
 134                 reg = <0xE0000 0x1000>;
 135                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
 136                              <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
 137                 interrupt-controller;
 138                 #interrupt-cells = <2>;
 139                 #gpio-cells = <2>;
 140
 141                 fan: fan {
 142                         samsung,exynos5440-pin-function = <1>;
 143                 };
 144
 145                 hdd_led0: hdd_led0 {
 146                         samsung,exynos5440-pin-function = <2>;
 147                 };
 148
 149                 hdd_led1: hdd_led1 {
 150                         samsung,exynos5440-pin-function = <3>;
 151                 };
 152
 153                 uart1: uart1 {
 154                         samsung,exynos5440-pin-function = <4>;
 155                 };
 156         };
 157
 158         i2c@F0000 {
 159                 compatible = "samsung,exynos5440-i2c";
 160                 reg = <0xF0000 0x1000>;
 161                 interrupts = <0 5 0>;
 162                 #address-cells = <1>;
 163                 #size-cells = <0>;
 164                 clocks = <&clock 21>;
 165                 clock-names = "i2c";
 166         };
 167
 168         i2c@100000 {
 169                 compatible = "samsung,exynos5440-i2c";
 170                 reg = <0x100000 0x1000>;
 171                 interrupts = <0 6 0>;
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174                 clocks = <&clock 21>;
 175                 clock-names = "i2c";
 176         };
 177
 178         watchdog {
 179                 compatible = "samsung,s3c2410-wdt";
 180                 reg = <0x110000 0x1000>;
 181                 interrupts = <0 1 0>;
 182                 clocks = <&clock 21>;
 183                 clock-names = "watchdog";
 184         };
 185
 186         gmac: ethernet@00230000 {
 187                 compatible = "snps,dwmac-3.70a";
 188                 reg = <0x00230000 0x8000>;
 189                 interrupt-parent = <&gic>;
 190                 interrupts = <0 31 4>;
 191                 interrupt-names = "macirq";
 192                 phy-mode = "sgmii";
 193                 clocks = <&clock 25>;
 194                 clock-names = "stmmaceth";
 195         };
 196
 197         amba {
 198                 #address-cells = <1>;
 199                 #size-cells = <1>;
 200                 compatible = "arm,amba-bus";
 201                 interrupt-parent = <&gic>;
 202                 ranges;
 203         };
 204
 205         rtc {
 206                 compatible = "samsung,s3c6410-rtc";
 207                 reg = <0x130000 0x1000>;
 208                 interrupts = <0 17 0>, <0 16 0>;
 209                 clocks = <&clock 21>;
 210                 clock-names = "rtc";
 211         };
 212
 213         tmuctrl_0: tmuctrl@160118 {
 214                 compatible = "samsung,exynos5440-tmu";
 215                 reg = <0x160118 0x230>, <0x160368 0x10>;
 216                 interrupts = <0 58 0>;
 217                 clocks = <&clock 21>;
 218                 clock-names = "tmu_apbif";
 219         };
 220
 221         tmuctrl_1: tmuctrl@16011C {
 222                 compatible = "samsung,exynos5440-tmu";
 223                 reg = <0x16011C 0x230>, <0x160368 0x10>;
 224                 interrupts = <0 58 0>;
 225                 clocks = <&clock 21>;
 226                 clock-names = "tmu_apbif";
 227         };
 228
 229         tmuctrl_2: tmuctrl@160120 {
 230                 compatible = "samsung,exynos5440-tmu";
 231                 reg = <0x160120 0x230>, <0x160368 0x10>;
 232                 interrupts = <0 58 0>;
 233                 clocks = <&clock 21>;
 234                 clock-names = "tmu_apbif";
 235         };
 236
 237         sata@210000 {
 238                 compatible = "snps,exynos5440-ahci";
 239                 reg = <0x210000 0x10000>;
 240                 interrupts = <0 30 0>;
 241                 clocks = <&clock 23>;
 242                 clock-names = "sata";
 243         };
 244
 245         ohci@220000 {
 246                 compatible = "samsung,exynos5440-ohci";
 247                 reg = <0x220000 0x1000>;
 248                 interrupts = <0 29 0>;
 249                 clocks = <&clock 24>;
 250                 clock-names = "usbhost";
 251         };
 252
 253         ehci@221000 {
 254                 compatible = "samsung,exynos5440-ehci";
 255                 reg = <0x221000 0x1000>;
 256                 interrupts = <0 29 0>;
 257                 clocks = <&clock 24>;
 258                 clock-names = "usbhost";
 259         };
 260
 261         pcie@290000 {
 262                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
 263                 reg = <0x290000 0x1000
 264                         0x270000 0x1000
 265                         0x271000 0x40>;
 266                 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
 267                 clocks = <&clock 28>, <&clock 27>;
 268                 clock-names = "pcie", "pcie_bus";
 269                 #address-cells = <3>;
 270                 #size-cells = <2>;
 271                 device_type = "pci";
 272                 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
 273                           0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
 274                           0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
 275                 #interrupt-cells = <1>;
 276                 interrupt-map-mask = <0 0 0 0>;
 277                 interrupt-map = <0x0 0 &gic 53>;
 278                 num-lanes = <4>;
 279                 status = "disabled";
 280         };
 281
 282         pcie@2a0000 {
 283                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
 284                 reg = <0x2a0000 0x1000
 285                         0x272000 0x1000
 286                         0x271040 0x40>;
 287                 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
 288                 clocks = <&clock 29>, <&clock 27>;
 289                 clock-names = "pcie", "pcie_bus";
 290                 #address-cells = <3>;
 291                 #size-cells = <2>;
 292                 device_type = "pci";
 293                 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
 294                           0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
 295                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
 296                 #interrupt-cells = <1>;
 297                 interrupt-map-mask = <0 0 0 0>;
 298                 interrupt-map = <0x0 0 &gic 56>;
 299                 num-lanes = <4>;
 300                 status = "disabled";
 301         };
 302 };