arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5420.h>
  17 #include "exynos5.dtsi"
  18 #include "exynos5420-pinctrl.dtsi"
  19
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21
  22 / {
  23         compatible = "samsung,exynos5420", "samsung,exynos5";
  24
  25         aliases {
  26                 mshc0 = &mmc_0;
  27                 mshc1 = &mmc_1;
  28                 mshc2 = &mmc_2;
  29                 pinctrl0 = &pinctrl_0;
  30                 pinctrl1 = &pinctrl_1;
  31                 pinctrl2 = &pinctrl_2;
  32                 pinctrl3 = &pinctrl_3;
  33                 pinctrl4 = &pinctrl_4;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &hsi2c_4;
  39                 i2c5 = &hsi2c_5;
  40                 i2c6 = &hsi2c_6;
  41                 i2c7 = &hsi2c_7;
  42                 i2c8 = &hsi2c_8;
  43                 i2c9 = &hsi2c_9;
  44                 i2c10 = &hsi2c_10;
  45                 gsc0 = &gsc_0;
  46                 gsc1 = &gsc_1;
  47                 spi0 = &spi_0;
  48                 spi1 = &spi_1;
  49                 spi2 = &spi_2;
  50                 usbdrdphy0 = &usbdrd_phy0;
  51                 usbdrdphy1 = &usbdrd_phy1;
  52         };
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a15";
  61                         reg = <0x0>;
  62                         clock-frequency = <1800000000>;
  63                         cci-control-port = <&cci_control1>;
  64                 };
  65
  66                 cpu1: cpu@1 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x1>;
  70                         clock-frequency = <1800000000>;
  71                         cci-control-port = <&cci_control1>;
  72                 };
  73
  74                 cpu2: cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a15";
  77                         reg = <0x2>;
  78                         clock-frequency = <1800000000>;
  79                         cci-control-port = <&cci_control1>;
  80                 };
  81
  82                 cpu3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0x3>;
  86                         clock-frequency = <1800000000>;
  87                         cci-control-port = <&cci_control1>;
  88                 };
  89
  90                 cpu4: cpu@100 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0x100>;
  94                         clock-frequency = <1000000000>;
  95                         cci-control-port = <&cci_control0>;
  96                 };
  97
  98                 cpu5: cpu@101 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a7";
 101                         reg = <0x101>;
 102                         clock-frequency = <1000000000>;
 103                         cci-control-port = <&cci_control0>;
 104                 };
 105
 106                 cpu6: cpu@102 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a7";
 109                         reg = <0x102>;
 110                         clock-frequency = <1000000000>;
 111                         cci-control-port = <&cci_control0>;
 112                 };
 113
 114                 cpu7: cpu@103 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a7";
 117                         reg = <0x103>;
 118                         clock-frequency = <1000000000>;
 119                         cci-control-port = <&cci_control0>;
 120                 };
 121         };
 122
 123         cci: cci@10d20000 {
 124                 compatible = "arm,cci-400";
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 reg = <0x10d20000 0x1000>;
 128                 ranges = <0x0 0x10d20000 0x6000>;
 129
 130                 cci_control0: slave-if@4000 {
 131                         compatible = "arm,cci-400-ctrl-if";
 132                         interface-type = "ace";
 133                         reg = <0x4000 0x1000>;
 134                 };
 135                 cci_control1: slave-if@5000 {
 136                         compatible = "arm,cci-400-ctrl-if";
 137                         interface-type = "ace";
 138                         reg = <0x5000 0x1000>;
 139                 };
 140         };
 141
 142         sysram@02020000 {
 143                 compatible = "mmio-sram";
 144                 reg = <0x02020000 0x54000>;
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0 0x02020000 0x54000>;
 148
 149                 smp-sysram@0 {
 150                         compatible = "samsung,exynos4210-sysram";
 151                         reg = <0x0 0x1000>;
 152                 };
 153
 154                 smp-sysram@53000 {
 155                         compatible = "samsung,exynos4210-sysram-ns";
 156                         reg = <0x53000 0x1000>;
 157                 };
 158         };
 159
 160         clock: clock-controller@10010000 {
 161                 compatible = "samsung,exynos5420-clock";
 162                 reg = <0x10010000 0x30000>;
 163                 #clock-cells = <1>;
 164         };
 165
 166         clock_audss: audss-clock-controller@3810000 {
 167                 compatible = "samsung,exynos5420-audss-clock";
 168                 reg = <0x03810000 0x0C>;
 169                 #clock-cells = <1>;
 170                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
 171                          <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
 172                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 173         };
 174
 175         mfc: codec@11000000 {
 176                 compatible = "samsung,mfc-v7";
 177                 reg = <0x11000000 0x10000>;
 178                 interrupts = <0 96 0>;
 179                 clocks = <&clock CLK_MFC>;
 180                 clock-names = "mfc";
 181                 power-domains = <&mfc_pd>;
 182                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 183                 iommu-names = "left", "right";
 184         };
 185
 186         mmc_0: mmc@12200000 {
 187                 compatible = "samsung,exynos5420-dw-mshc-smu";
 188                 interrupts = <0 75 0>;
 189                 #address-cells = <1>;
 190                 #size-cells = <0>;
 191                 reg = <0x12200000 0x2000>;
 192                 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 193                 clock-names = "biu", "ciu";
 194                 fifo-depth = <0x40>;
 195                 status = "disabled";
 196         };
 197
 198         mmc_1: mmc@12210000 {
 199                 compatible = "samsung,exynos5420-dw-mshc-smu";
 200                 interrupts = <0 76 0>;
 201                 #address-cells = <1>;
 202                 #size-cells = <0>;
 203                 reg = <0x12210000 0x2000>;
 204                 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 205                 clock-names = "biu", "ciu";
 206                 fifo-depth = <0x40>;
 207                 status = "disabled";
 208         };
 209
 210         mmc_2: mmc@12220000 {
 211                 compatible = "samsung,exynos5420-dw-mshc";
 212                 interrupts = <0 77 0>;
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 reg = <0x12220000 0x1000>;
 216                 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 217                 clock-names = "biu", "ciu";
 218                 fifo-depth = <0x40>;
 219                 status = "disabled";
 220         };
 221
 222         mct: mct@101C0000 {
 223                 compatible = "samsung,exynos4210-mct";
 224                 reg = <0x101C0000 0x800>;
 225                 interrupt-controller;
 226                 #interrupt-cells = <1>;
 227                 interrupt-parent = <&mct_map>;
 228                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
 229                                 <8>, <9>, <10>, <11>;
 230                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 231                 clock-names = "fin_pll", "mct";
 232
 233                 mct_map: mct-map {
 234                         #interrupt-cells = <1>;
 235                         #address-cells = <0>;
 236                         #size-cells = <0>;
 237                         interrupt-map = <0 &combiner 23 3>,
 238                                         <1 &combiner 23 4>,
 239                                         <2 &combiner 25 2>,
 240                                         <3 &combiner 25 3>,
 241                                         <4 &gic 0 120 0>,
 242                                         <5 &gic 0 121 0>,
 243                                         <6 &gic 0 122 0>,
 244                                         <7 &gic 0 123 0>,
 245                                         <8 &gic 0 128 0>,
 246                                         <9 &gic 0 129 0>,
 247                                         <10 &gic 0 130 0>,
 248                                         <11 &gic 0 131 0>;
 249                 };
 250         };
 251
 252         gsc_pd: power-domain@10044000 {
 253                 compatible = "samsung,exynos4210-pd";
 254                 reg = <0x10044000 0x20>;
 255                 #power-domain-cells = <0>;
 256                 clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
 257                 clock-names = "asb0", "asb1";
 258         };
 259
 260         isp_pd: power-domain@10044020 {
 261                 compatible = "samsung,exynos4210-pd";
 262                 reg = <0x10044020 0x20>;
 263                 #power-domain-cells = <0>;
 264         };
 265
 266         mfc_pd: power-domain@10044060 {
 267                 compatible = "samsung,exynos4210-pd";
 268                 reg = <0x10044060 0x20>;
 269                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
 270                 clock-names = "oscclk", "clk0";
 271                 #power-domain-cells = <0>;
 272         };
 273
 274         msc_pd: power-domain@10044120 {
 275                 compatible = "samsung,exynos4210-pd";
 276                 reg = <0x10044120 0x20>;
 277                 #power-domain-cells = <0>;
 278         };
 279
 280         disp_pd: power-domain@100440C0 {
 281                 compatible = "samsung,exynos4210-pd";
 282                 reg = <0x100440C0 0x20>;
 283                 #power-domain-cells = <0>;
 284                 clocks = <&clock CLK_FIN_PLL>,
 285                          <&clock CLK_MOUT_USER_ACLK200_DISP1>,
 286                          <&clock CLK_MOUT_USER_ACLK300_DISP1>,
 287                          <&clock CLK_MOUT_USER_ACLK400_DISP1>,
 288                          <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
 289                 clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
 290         };
 291
 292         pinctrl_0: pinctrl@13400000 {
 293                 compatible = "samsung,exynos5420-pinctrl";
 294                 reg = <0x13400000 0x1000>;
 295                 interrupts = <0 45 0>;
 296
 297                 wakeup-interrupt-controller {
 298                         compatible = "samsung,exynos4210-wakeup-eint";
 299                         interrupt-parent = <&gic>;
 300                         interrupts = <0 32 0>;
 301                 };
 302         };
 303
 304         pinctrl_1: pinctrl@13410000 {
 305                 compatible = "samsung,exynos5420-pinctrl";
 306                 reg = <0x13410000 0x1000>;
 307                 interrupts = <0 78 0>;
 308         };
 309
 310         pinctrl_2: pinctrl@14000000 {
 311                 compatible = "samsung,exynos5420-pinctrl";
 312                 reg = <0x14000000 0x1000>;
 313                 interrupts = <0 46 0>;
 314         };
 315
 316         pinctrl_3: pinctrl@14010000 {
 317                 compatible = "samsung,exynos5420-pinctrl";
 318                 reg = <0x14010000 0x1000>;
 319                 interrupts = <0 50 0>;
 320         };
 321
 322         pinctrl_4: pinctrl@03860000 {
 323                 compatible = "samsung,exynos5420-pinctrl";
 324                 reg = <0x03860000 0x1000>;
 325                 interrupts = <0 47 0>;
 326         };
 327
 328         amba {
 329                 #address-cells = <1>;
 330                 #size-cells = <1>;
 331                 compatible = "arm,amba-bus";
 332                 interrupt-parent = <&gic>;
 333                 ranges;
 334
 335                 adma: adma@03880000 {
 336                         compatible = "arm,pl330", "arm,primecell";
 337                         reg = <0x03880000 0x1000>;
 338                         interrupts = <0 110 0>;
 339                         clocks = <&clock_audss EXYNOS_ADMA>;
 340                         clock-names = "apb_pclk";
 341                         #dma-cells = <1>;
 342                         #dma-channels = <6>;
 343                         #dma-requests = <16>;
 344                 };
 345
 346                 pdma0: pdma@121A0000 {
 347                         compatible = "arm,pl330", "arm,primecell";
 348                         reg = <0x121A0000 0x1000>;
 349                         interrupts = <0 34 0>;
 350                         clocks = <&clock CLK_PDMA0>;
 351                         clock-names = "apb_pclk";
 352                         #dma-cells = <1>;
 353                         #dma-channels = <8>;
 354                         #dma-requests = <32>;
 355                 };
 356
 357                 pdma1: pdma@121B0000 {
 358                         compatible = "arm,pl330", "arm,primecell";
 359                         reg = <0x121B0000 0x1000>;
 360                         interrupts = <0 35 0>;
 361                         clocks = <&clock CLK_PDMA1>;
 362                         clock-names = "apb_pclk";
 363                         #dma-cells = <1>;
 364                         #dma-channels = <8>;
 365                         #dma-requests = <32>;
 366                 };
 367
 368                 mdma0: mdma@10800000 {
 369                         compatible = "arm,pl330", "arm,primecell";
 370                         reg = <0x10800000 0x1000>;
 371                         interrupts = <0 33 0>;
 372                         clocks = <&clock CLK_MDMA0>;
 373                         clock-names = "apb_pclk";
 374                         #dma-cells = <1>;
 375                         #dma-channels = <8>;
 376                         #dma-requests = <1>;
 377                 };
 378
 379                 mdma1: mdma@11C10000 {
 380                         compatible = "arm,pl330", "arm,primecell";
 381                         reg = <0x11C10000 0x1000>;
 382                         interrupts = <0 124 0>;
 383                         clocks = <&clock CLK_MDMA1>;
 384                         clock-names = "apb_pclk";
 385                         #dma-cells = <1>;
 386                         #dma-channels = <8>;
 387                         #dma-requests = <1>;
 388                         /*
 389                          * MDMA1 can support both secure and non-secure
 390                          * AXI transactions. When this is enabled in the kernel
 391                          * for boards that run in secure mode, we are getting
 392                          * imprecise external aborts causing the kernel to oops.
 393                          */
 394                         status = "disabled";
 395                 };
 396         };
 397
 398         i2s0: i2s@03830000 {
 399                 compatible = "samsung,exynos5420-i2s";
 400                 reg = <0x03830000 0x100>;
 401                 dmas = <&adma 0
 402                         &adma 2
 403                         &adma 1>;
 404                 dma-names = "tx", "rx", "tx-sec";
 405                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
 406                         <&clock_audss EXYNOS_I2S_BUS>,
 407                         <&clock_audss EXYNOS_SCLK_I2S>;
 408                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 409                 #clock-cells = <1>;
 410                 clock-output-names = "i2s_cdclk0";
 411                 #sound-dai-cells = <1>;
 412                 samsung,idma-addr = <0x03000000>;
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&i2s0_bus>;
 415                 status = "disabled";
 416         };
 417
 418         i2s1: i2s@12D60000 {
 419                 compatible = "samsung,exynos5420-i2s";
 420                 reg = <0x12D60000 0x100>;
 421                 dmas = <&pdma1 12
 422                         &pdma1 11>;
 423                 dma-names = "tx", "rx";
 424                 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
 425                 clock-names = "iis", "i2s_opclk0";
 426                 #clock-cells = <1>;
 427                 clock-output-names = "i2s_cdclk1";
 428                 #sound-dai-cells = <1>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&i2s1_bus>;
 431                 status = "disabled";
 432         };
 433
 434         i2s2: i2s@12D70000 {
 435                 compatible = "samsung,exynos5420-i2s";
 436                 reg = <0x12D70000 0x100>;
 437                 dmas = <&pdma0 12
 438                         &pdma0 11>;
 439                 dma-names = "tx", "rx";
 440                 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
 441                 clock-names = "iis", "i2s_opclk0";
 442                 #clock-cells = <1>;
 443                 clock-output-names = "i2s_cdclk2";
 444                 #sound-dai-cells = <1>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2s2_bus>;
 447                 status = "disabled";
 448         };
 449
 450         spi_0: spi@12d20000 {
 451                 compatible = "samsung,exynos4210-spi";
 452                 reg = <0x12d20000 0x100>;
 453                 interrupts = <0 68 0>;
 454                 dmas = <&pdma0 5
 455                         &pdma0 4>;
 456                 dma-names = "tx", "rx";
 457                 #address-cells = <1>;
 458                 #size-cells = <0>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&spi0_bus>;
 461                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 462                 clock-names = "spi", "spi_busclk0";
 463                 status = "disabled";
 464         };
 465
 466         spi_1: spi@12d30000 {
 467                 compatible = "samsung,exynos4210-spi";
 468                 reg = <0x12d30000 0x100>;
 469                 interrupts = <0 69 0>;
 470                 dmas = <&pdma1 5
 471                         &pdma1 4>;
 472                 dma-names = "tx", "rx";
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&spi1_bus>;
 477                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 478                 clock-names = "spi", "spi_busclk0";
 479                 status = "disabled";
 480         };
 481
 482         spi_2: spi@12d40000 {
 483                 compatible = "samsung,exynos4210-spi";
 484                 reg = <0x12d40000 0x100>;
 485                 interrupts = <0 70 0>;
 486                 dmas = <&pdma0 7
 487                         &pdma0 6>;
 488                 dma-names = "tx", "rx";
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&spi2_bus>;
 493                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 494                 clock-names = "spi", "spi_busclk0";
 495                 status = "disabled";
 496         };
 497
 498         pwm: pwm@12dd0000 {
 499                 compatible = "samsung,exynos4210-pwm";
 500                 reg = <0x12dd0000 0x100>;
 501                 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 502                 #pwm-cells = <3>;
 503                 clocks = <&clock CLK_PWM>;
 504                 clock-names = "timers";
 505         };
 506
 507         dp_phy: video-phy@10040728 {
 508                 compatible = "samsung,exynos5420-dp-video-phy";
 509                 samsung,pmu-syscon = <&pmu_system_controller>;
 510                 #phy-cells = <0>;
 511         };
 512
 513         mipi_phy: video-phy@10040714 {
 514                 compatible = "samsung,s5pv210-mipi-video-phy";
 515                 syscon = <&pmu_system_controller>;
 516                 #phy-cells = <1>;
 517         };
 518
 519         dsi@14500000 {
 520                 compatible = "samsung,exynos5410-mipi-dsi";
 521                 reg = <0x14500000 0x10000>;
 522                 interrupts = <0 82 0>;
 523                 phys = <&mipi_phy 1>;
 524                 phy-names = "dsim";
 525                 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
 526                 clock-names = "bus_clk", "pll_clk";
 527                 #address-cells = <1>;
 528                 #size-cells = <0>;
 529                 status = "disabled";
 530         };
 531
 532         adc: adc@12D10000 {
 533                 compatible = "samsung,exynos-adc-v2";
 534                 reg = <0x12D10000 0x100>;
 535                 interrupts = <0 106 0>;
 536                 clocks = <&clock CLK_TSADC>;
 537                 clock-names = "adc";
 538                 #io-channel-cells = <1>;
 539                 io-channel-ranges;
 540                 samsung,syscon-phandle = <&pmu_system_controller>;
 541                 status = "disabled";
 542         };
 543
 544         i2c_0: i2c@12C60000 {
 545                 compatible = "samsung,s3c2440-i2c";
 546                 reg = <0x12C60000 0x100>;
 547                 interrupts = <0 56 0>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 clocks = <&clock CLK_I2C0>;
 551                 clock-names = "i2c";
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&i2c0_bus>;
 554                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 555                 status = "disabled";
 556         };
 557
 558         i2c_1: i2c@12C70000 {
 559                 compatible = "samsung,s3c2440-i2c";
 560                 reg = <0x12C70000 0x100>;
 561                 interrupts = <0 57 0>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 clocks = <&clock CLK_I2C1>;
 565                 clock-names = "i2c";
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c1_bus>;
 568                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 569                 status = "disabled";
 570         };
 571
 572         i2c_2: i2c@12C80000 {
 573                 compatible = "samsung,s3c2440-i2c";
 574                 reg = <0x12C80000 0x100>;
 575                 interrupts = <0 58 0>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 clocks = <&clock CLK_I2C2>;
 579                 clock-names = "i2c";
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&i2c2_bus>;
 582                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 583                 status = "disabled";
 584         };
 585
 586         i2c_3: i2c@12C90000 {
 587                 compatible = "samsung,s3c2440-i2c";
 588                 reg = <0x12C90000 0x100>;
 589                 interrupts = <0 59 0>;
 590                 #address-cells = <1>;
 591                 #size-cells = <0>;
 592                 clocks = <&clock CLK_I2C3>;
 593                 clock-names = "i2c";
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&i2c3_bus>;
 596                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 597                 status = "disabled";
 598         };
 599
 600         hsi2c_4: i2c@12CA0000 {
 601                 compatible = "samsung,exynos5-hsi2c";
 602                 reg = <0x12CA0000 0x1000>;
 603                 interrupts = <0 60 0>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&i2c4_hs_bus>;
 608                 clocks = <&clock CLK_USI0>;
 609                 clock-names = "hsi2c";
 610                 status = "disabled";
 611         };
 612
 613         hsi2c_5: i2c@12CB0000 {
 614                 compatible = "samsung,exynos5-hsi2c";
 615                 reg = <0x12CB0000 0x1000>;
 616                 interrupts = <0 61 0>;
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c5_hs_bus>;
 621                 clocks = <&clock CLK_USI1>;
 622                 clock-names = "hsi2c";
 623                 status = "disabled";
 624         };
 625
 626         hsi2c_6: i2c@12CC0000 {
 627                 compatible = "samsung,exynos5-hsi2c";
 628                 reg = <0x12CC0000 0x1000>;
 629                 interrupts = <0 62 0>;
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&i2c6_hs_bus>;
 634                 clocks = <&clock CLK_USI2>;
 635                 clock-names = "hsi2c";
 636                 status = "disabled";
 637         };
 638
 639         hsi2c_7: i2c@12CD0000 {
 640                 compatible = "samsung,exynos5-hsi2c";
 641                 reg = <0x12CD0000 0x1000>;
 642                 interrupts = <0 63 0>;
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 pinctrl-names = "default";
 646                 pinctrl-0 = <&i2c7_hs_bus>;
 647                 clocks = <&clock CLK_USI3>;
 648                 clock-names = "hsi2c";
 649                 status = "disabled";
 650         };
 651
 652         hsi2c_8: i2c@12E00000 {
 653                 compatible = "samsung,exynos5-hsi2c";
 654                 reg = <0x12E00000 0x1000>;
 655                 interrupts = <0 87 0>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&i2c8_hs_bus>;
 660                 clocks = <&clock CLK_USI4>;
 661                 clock-names = "hsi2c";
 662                 status = "disabled";
 663         };
 664
 665         hsi2c_9: i2c@12E10000 {
 666                 compatible = "samsung,exynos5-hsi2c";
 667                 reg = <0x12E10000 0x1000>;
 668                 interrupts = <0 88 0>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 pinctrl-names = "default";
 672                 pinctrl-0 = <&i2c9_hs_bus>;
 673                 clocks = <&clock CLK_USI5>;
 674                 clock-names = "hsi2c";
 675                 status = "disabled";
 676         };
 677
 678         hsi2c_10: i2c@12E20000 {
 679                 compatible = "samsung,exynos5-hsi2c";
 680                 reg = <0x12E20000 0x1000>;
 681                 interrupts = <0 203 0>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&i2c10_hs_bus>;
 686                 clocks = <&clock CLK_USI6>;
 687                 clock-names = "hsi2c";
 688                 status = "disabled";
 689         };
 690
 691         hdmi: hdmi@14530000 {
 692                 compatible = "samsung,exynos5420-hdmi";
 693                 reg = <0x14530000 0x70000>;
 694                 interrupts = <0 95 0>;
 695                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 696                          <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 697                          <&clock CLK_MOUT_HDMI>;
 698                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 699                         "sclk_hdmiphy", "mout_hdmi";
 700                 phy = <&hdmiphy>;
 701                 samsung,syscon-phandle = <&pmu_system_controller>;
 702                 status = "disabled";
 703                 power-domains = <&disp_pd>;
 704         };
 705
 706         hdmiphy: hdmiphy@145D0000 {
 707                 reg = <0x145D0000 0x20>;
 708         };
 709
 710         mixer: mixer@14450000 {
 711                 compatible = "samsung,exynos5420-mixer";
 712                 reg = <0x14450000 0x10000>;
 713                 interrupts = <0 94 0>;
 714                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 715                          <&clock CLK_SCLK_HDMI>;
 716                 clock-names = "mixer", "hdmi", "sclk_hdmi";
 717                 power-domains = <&disp_pd>;
 718                 iommus = <&sysmmu_tv>;
 719         };
 720
 721         gsc_0: video-scaler@13e00000 {
 722                 compatible = "samsung,exynos5-gsc";
 723                 reg = <0x13e00000 0x1000>;
 724                 interrupts = <0 85 0>;
 725                 clocks = <&clock CLK_GSCL0>;
 726                 clock-names = "gscl";
 727                 power-domains = <&gsc_pd>;
 728                 iommus = <&sysmmu_gscl0>;
 729         };
 730
 731         gsc_1: video-scaler@13e10000 {
 732                 compatible = "samsung,exynos5-gsc";
 733                 reg = <0x13e10000 0x1000>;
 734                 interrupts = <0 86 0>;
 735                 clocks = <&clock CLK_GSCL1>;
 736                 clock-names = "gscl";
 737                 power-domains = <&gsc_pd>;
 738                 iommus = <&sysmmu_gscl1>;
 739         };
 740
 741         jpeg_0: jpeg@11F50000 {
 742                 compatible = "samsung,exynos5420-jpeg";
 743                 reg = <0x11F50000 0x1000>;
 744                 interrupts = <0 89 0>;
 745                 clock-names = "jpeg";
 746                 clocks = <&clock CLK_JPEG>;
 747                 iommus = <&sysmmu_jpeg0>;
 748         };
 749
 750         jpeg_1: jpeg@11F60000 {
 751                 compatible = "samsung,exynos5420-jpeg";
 752                 reg = <0x11F60000 0x1000>;
 753                 interrupts = <0 168 0>;
 754                 clock-names = "jpeg";
 755                 clocks = <&clock CLK_JPEG2>;
 756                 iommus = <&sysmmu_jpeg1>;
 757         };
 758
 759         pmu_system_controller: system-controller@10040000 {
 760                 compatible = "samsung,exynos5420-pmu", "syscon";
 761                 reg = <0x10040000 0x5000>;
 762                 clock-names = "clkout16";
 763                 clocks = <&clock CLK_FIN_PLL>;
 764                 #clock-cells = <1>;
 765                 interrupt-controller;
 766                 #interrupt-cells = <3>;
 767                 interrupt-parent = <&gic>;
 768         };
 769
 770         sysreg_system_controller: syscon@10050000 {
 771                 compatible = "samsung,exynos5-sysreg", "syscon";
 772                 reg = <0x10050000 0x5000>;
 773         };
 774
 775         tmu_cpu0: tmu@10060000 {
 776                 compatible = "samsung,exynos5420-tmu";
 777                 reg = <0x10060000 0x100>;
 778                 interrupts = <0 65 0>;
 779                 clocks = <&clock CLK_TMU>;
 780                 clock-names = "tmu_apbif";
 781                 #include "exynos4412-tmu-sensor-conf.dtsi"
 782         };
 783
 784         tmu_cpu1: tmu@10064000 {
 785                 compatible = "samsung,exynos5420-tmu";
 786                 reg = <0x10064000 0x100>;
 787                 interrupts = <0 183 0>;
 788                 clocks = <&clock CLK_TMU>;
 789                 clock-names = "tmu_apbif";
 790                 #include "exynos4412-tmu-sensor-conf.dtsi"
 791         };
 792
 793         tmu_cpu2: tmu@10068000 {
 794                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 795                 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
 796                 interrupts = <0 184 0>;
 797                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
 798                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 799                 #include "exynos4412-tmu-sensor-conf.dtsi"
 800         };
 801
 802         tmu_cpu3: tmu@1006c000 {
 803                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 804                 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
 805                 interrupts = <0 185 0>;
 806                 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
 807                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 808                 #include "exynos4412-tmu-sensor-conf.dtsi"
 809         };
 810
 811         tmu_gpu: tmu@100a0000 {
 812                 compatible = "samsung,exynos5420-tmu-ext-triminfo";
 813                 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
 814                 interrupts = <0 215 0>;
 815                 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
 816                 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
 817                 #include "exynos4412-tmu-sensor-conf.dtsi"
 818         };
 819
 820         thermal-zones {
 821                 cpu0_thermal: cpu0-thermal {
 822                         thermal-sensors = <&tmu_cpu0>;
 823                         #include "exynos5420-trip-points.dtsi"
 824                 };
 825                 cpu1_thermal: cpu1-thermal {
 826                        thermal-sensors = <&tmu_cpu1>;
 827                        #include "exynos5420-trip-points.dtsi"
 828                 };
 829                 cpu2_thermal: cpu2-thermal {
 830                        thermal-sensors = <&tmu_cpu2>;
 831                        #include "exynos5420-trip-points.dtsi"
 832                 };
 833                 cpu3_thermal: cpu3-thermal {
 834                        thermal-sensors = <&tmu_cpu3>;
 835                        #include "exynos5420-trip-points.dtsi"
 836                 };
 837                 gpu_thermal: gpu-thermal {
 838                        thermal-sensors = <&tmu_gpu>;
 839                        #include "exynos5420-trip-points.dtsi"
 840                 };
 841         };
 842
 843         watchdog: watchdog@101D0000 {
 844                 compatible = "samsung,exynos5420-wdt";
 845                 reg = <0x101D0000 0x100>;
 846                 interrupts = <0 42 0>;
 847                 clocks = <&clock CLK_WDT>;
 848                 clock-names = "watchdog";
 849                 samsung,syscon-phandle = <&pmu_system_controller>;
 850         };
 851
 852         sss: sss@10830000 {
 853                 compatible = "samsung,exynos4210-secss";
 854                 reg = <0x10830000 0x10000>;
 855                 interrupts = <0 112 0>;
 856                 clocks = <&clock CLK_SSS>;
 857                 clock-names = "secss";
 858         };
 859
 860         usbdrd3_0: usb@12000000 {
 861                 compatible = "samsung,exynos5250-dwusb3";
 862                 clocks = <&clock CLK_USBD300>;
 863                 clock-names = "usbdrd30";
 864                 #address-cells = <1>;
 865                 #size-cells = <1>;
 866                 ranges;
 867
 868                 usbdrd_dwc3_0: dwc3 {
 869                         compatible = "snps,dwc3";
 870                         reg = <0x12000000 0x10000>;
 871                         interrupts = <0 72 0>;
 872                         phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
 873                         phy-names = "usb2-phy", "usb3-phy";
 874                 };
 875         };
 876
 877         usbdrd_phy0: phy@12100000 {
 878                 compatible = "samsung,exynos5420-usbdrd-phy";
 879                 reg = <0x12100000 0x100>;
 880                 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 881                 clock-names = "phy", "ref";
 882                 samsung,pmu-syscon = <&pmu_system_controller>;
 883                 #phy-cells = <1>;
 884         };
 885
 886         usbdrd3_1: usb@12400000 {
 887                 compatible = "samsung,exynos5250-dwusb3";
 888                 clocks = <&clock CLK_USBD301>;
 889                 clock-names = "usbdrd30";
 890                 #address-cells = <1>;
 891                 #size-cells = <1>;
 892                 ranges;
 893
 894                 usbdrd_dwc3_1: dwc3 {
 895                         compatible = "snps,dwc3";
 896                         reg = <0x12400000 0x10000>;
 897                         interrupts = <0 73 0>;
 898                         phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
 899                         phy-names = "usb2-phy", "usb3-phy";
 900                 };
 901         };
 902
 903         usbdrd_phy1: phy@12500000 {
 904                 compatible = "samsung,exynos5420-usbdrd-phy";
 905                 reg = <0x12500000 0x100>;
 906                 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 907                 clock-names = "phy", "ref";
 908                 samsung,pmu-syscon = <&pmu_system_controller>;
 909                 #phy-cells = <1>;
 910         };
 911
 912         usbhost2: usb@12110000 {
 913                 compatible = "samsung,exynos4210-ehci";
 914                 reg = <0x12110000 0x100>;
 915                 interrupts = <0 71 0>;
 916
 917                 clocks = <&clock CLK_USBH20>;
 918                 clock-names = "usbhost";
 919                 #address-cells = <1>;
 920                 #size-cells = <0>;
 921                 port@0 {
 922                         reg = <0>;
 923                         phys = <&usb2_phy 1>;
 924                 };
 925         };
 926
 927         usbhost1: usb@12120000 {
 928                 compatible = "samsung,exynos4210-ohci";
 929                 reg = <0x12120000 0x100>;
 930                 interrupts = <0 71 0>;
 931
 932                 clocks = <&clock CLK_USBH20>;
 933                 clock-names = "usbhost";
 934                 #address-cells = <1>;
 935                 #size-cells = <0>;
 936                 port@0 {
 937                         reg = <0>;
 938                         phys = <&usb2_phy 1>;
 939                 };
 940         };
 941
 942         usb2_phy: phy@12130000 {
 943                 compatible = "samsung,exynos5250-usb2-phy";
 944                 reg = <0x12130000 0x100>;
 945                 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 946                 clock-names = "phy", "ref";
 947                 #phy-cells = <1>;
 948                 samsung,sysreg-phandle = <&sysreg_system_controller>;
 949                 samsung,pmureg-phandle = <&pmu_system_controller>;
 950         };
 951
 952         sysmmu_g2dr: sysmmu@0x10A60000 {
 953                 compatible = "samsung,exynos-sysmmu";
 954                 reg = <0x10A60000 0x1000>;
 955                 interrupt-parent = <&combiner>;
 956                 interrupts = <24 5>;
 957                 clock-names = "sysmmu", "master";
 958                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 959                 #iommu-cells = <0>;
 960         };
 961
 962         sysmmu_g2dw: sysmmu@0x10A70000 {
 963                 compatible = "samsung,exynos-sysmmu";
 964                 reg = <0x10A70000 0x1000>;
 965                 interrupt-parent = <&combiner>;
 966                 interrupts = <22 2>;
 967                 clock-names = "sysmmu", "master";
 968                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 969                 #iommu-cells = <0>;
 970         };
 971
 972         sysmmu_tv: sysmmu@0x14650000 {
 973                 compatible = "samsung,exynos-sysmmu";
 974                 reg = <0x14650000 0x1000>;
 975                 interrupt-parent = <&combiner>;
 976                 interrupts = <7 4>;
 977                 clock-names = "sysmmu", "master";
 978                 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
 979                 power-domains = <&disp_pd>;
 980                 #iommu-cells = <0>;
 981         };
 982
 983         sysmmu_gscl0: sysmmu@0x13E80000 {
 984                 compatible = "samsung,exynos-sysmmu";
 985                 reg = <0x13E80000 0x1000>;
 986                 interrupt-parent = <&combiner>;
 987                 interrupts = <2 0>;
 988                 clock-names = "sysmmu", "master";
 989                 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 990                 power-domains = <&gsc_pd>;
 991                 #iommu-cells = <0>;
 992         };
 993
 994         sysmmu_gscl1: sysmmu@0x13E90000 {
 995                 compatible = "samsung,exynos-sysmmu";
 996                 reg = <0x13E90000 0x1000>;
 997                 interrupt-parent = <&combiner>;
 998                 interrupts = <2 2>;
 999                 clock-names = "sysmmu", "master";
1000                 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1001                 power-domains = <&gsc_pd>;
1002                 #iommu-cells = <0>;
1003         };
1004
1005         sysmmu_scaler0r: sysmmu@0x12880000 {
1006                 compatible = "samsung,exynos-sysmmu";
1007                 reg = <0x12880000 0x1000>;
1008                 interrupt-parent = <&combiner>;
1009                 interrupts = <22 4>;
1010                 clock-names = "sysmmu", "master";
1011                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1012                 #iommu-cells = <0>;
1013         };
1014
1015         sysmmu_scaler1r: sysmmu@0x12890000 {
1016                 compatible = "samsung,exynos-sysmmu";
1017                 reg = <0x12890000 0x1000>;
1018                 interrupts = <0 186 0>;
1019                 clock-names = "sysmmu", "master";
1020                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1021                 #iommu-cells = <0>;
1022         };
1023
1024         sysmmu_scaler2r: sysmmu@0x128A0000 {
1025                 compatible = "samsung,exynos-sysmmu";
1026                 reg = <0x128A0000 0x1000>;
1027                 interrupts = <0 188 0>;
1028                 clock-names = "sysmmu", "master";
1029                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1030                 #iommu-cells = <0>;
1031         };
1032
1033         sysmmu_scaler0w: sysmmu@0x128C0000 {
1034                 compatible = "samsung,exynos-sysmmu";
1035                 reg = <0x128C0000 0x1000>;
1036                 interrupt-parent = <&combiner>;
1037                 interrupts = <27 2>;
1038                 clock-names = "sysmmu", "master";
1039                 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1040                 #iommu-cells = <0>;
1041         };
1042
1043         sysmmu_scaler1w: sysmmu@0x128D0000 {
1044                 compatible = "samsung,exynos-sysmmu";
1045                 reg = <0x128D0000 0x1000>;
1046                 interrupt-parent = <&combiner>;
1047                 interrupts = <22 6>;
1048                 clock-names = "sysmmu", "master";
1049                 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1050                 #iommu-cells = <0>;
1051         };
1052
1053         sysmmu_scaler2w: sysmmu@0x128E0000 {
1054                 compatible = "samsung,exynos-sysmmu";
1055                 reg = <0x128E0000 0x1000>;
1056                 interrupt-parent = <&combiner>;
1057                 interrupts = <19 6>;
1058                 clock-names = "sysmmu", "master";
1059                 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1060                 #iommu-cells = <0>;
1061         };
1062
1063         sysmmu_jpeg0: sysmmu@0x11F10000 {
1064                 compatible = "samsung,exynos-sysmmu";
1065                 reg = <0x11F10000 0x1000>;
1066                 interrupt-parent = <&combiner>;
1067                 interrupts = <4 2>;
1068                 clock-names = "sysmmu", "master";
1069                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1070                 #iommu-cells = <0>;
1071         };
1072
1073         sysmmu_jpeg1: sysmmu@0x11F20000 {
1074                 compatible = "samsung,exynos-sysmmu";
1075                 reg = <0x11F20000 0x1000>;
1076                 interrupts = <0 169 0>;
1077                 clock-names = "sysmmu", "master";
1078                 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1079                 #iommu-cells = <0>;
1080         };
1081
1082         sysmmu_mfc_l: sysmmu@0x11200000 {
1083                 compatible = "samsung,exynos-sysmmu";
1084                 reg = <0x11200000 0x1000>;
1085                 interrupt-parent = <&combiner>;
1086                 interrupts = <6 2>;
1087                 clock-names = "sysmmu", "master";
1088                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1089                 power-domains = <&mfc_pd>;
1090                 #iommu-cells = <0>;
1091         };
1092
1093         sysmmu_mfc_r: sysmmu@0x11210000 {
1094                 compatible = "samsung,exynos-sysmmu";
1095                 reg = <0x11210000 0x1000>;
1096                 interrupt-parent = <&combiner>;
1097                 interrupts = <8 5>;
1098                 clock-names = "sysmmu", "master";
1099                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1100                 power-domains = <&mfc_pd>;
1101                 #iommu-cells = <0>;
1102         };
1103
1104         sysmmu_fimd1_0: sysmmu@0x14640000 {
1105                 compatible = "samsung,exynos-sysmmu";
1106                 reg = <0x14640000 0x1000>;
1107                 interrupt-parent = <&combiner>;
1108                 interrupts = <3 2>;
1109                 clock-names = "sysmmu", "master";
1110                 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1111                 power-domains = <&disp_pd>;
1112                 #iommu-cells = <0>;
1113         };
1114
1115         sysmmu_fimd1_1: sysmmu@0x14680000 {
1116                 compatible = "samsung,exynos-sysmmu";
1117                 reg = <0x14680000 0x1000>;
1118                 interrupt-parent = <&combiner>;
1119                 interrupts = <3 0>;
1120                 clock-names = "sysmmu", "master";
1121                 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1122                 power-domains = <&disp_pd>;
1123                 #iommu-cells = <0>;
1124         };
1125 };
1126
1127 &dp {
1128         clocks = <&clock CLK_DP1>;
1129         clock-names = "dp";
1130         phys = <&dp_phy>;
1131         phy-names = "dp";
1132         power-domains = <&disp_pd>;
1133 };
1134
1135 &fimd {
1136         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1137         clock-names = "sclk_fimd", "fimd";
1138         power-domains = <&disp_pd>;
1139         iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1140         iommu-names = "m0", "m1";
1141 };
1142
1143 &rtc {
1144         clocks = <&clock CLK_RTC>;
1145         clock-names = "rtc";
1146         interrupt-parent = <&pmu_system_controller>;
1147         status = "disabled";
1148 };
1149
1150 &serial_0 {
1151         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1152         clock-names = "uart", "clk_uart_baud0";
1153 };
1154
1155 &serial_1 {
1156         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1157         clock-names = "uart", "clk_uart_baud0";
1158 };
1159
1160 &serial_2 {
1161         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1162         clock-names = "uart", "clk_uart_baud0";
1163 };
1164
1165 &serial_3 {
1166         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1167         clock-names = "uart", "clk_uart_baud0";
1168 };