arch/arm/boot/dts/atlas7.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas7 SoC
   3  *
   4  * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,atlas7";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&gic>;
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18                 serial2 = &uart2;
  19                 serial3 = &uart3;
  20                 serial4 = &uart4;
  21                 serial5 = &uart5;
  22                 serial6 = &uart6;
  23                 serial9 = &usp2;
  24         };
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32                         reg = <0>;
  33                 };
  34                 cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         reg = <1>;
  38                 };
  39         };
  40
  41         clocks {
  42                 xinw {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <32768>;
  46                         clock-output-names = "xinw";
  47                 };
  48                 xin {
  49                         compatible = "fixed-clock";
  50                         #clock-cells = <0>;
  51                         clock-frequency = <26000000>;
  52                         clock-output-names = "xin";
  53                 };
  54         };
  55
  56         noc {
  57                 compatible = "simple-bus";
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 ranges = <0x10000000 0x10000000 0xc0000000>;
  61
  62                 gic: interrupt-controller@10301000 {
  63                         compatible = "arm,cortex-a9-gic";
  64                         interrupt-controller;
  65                         #interrupt-cells = <3>;
  66                         reg = <0x10301000 0x1000>,
  67                              <0x10302000 0x0100>;
  68                 };
  69
  70                 pmu_regulator: pmu_regulator@10E30020 {
  71                         compatible = "sirf,atlas7-pmu-ldo";
  72                         reg = <0x10E30020 0x4>;
  73                         ldo: ldo {
  74                                 regulator-name = "ldo";
  75                         };
  76                 };
  77
  78                 atlas7_codec: atlas7_codec@10E30000 {
  79                         #sound-dai-cells = <0>;
  80                         compatible = "sirf,atlas7-codec";
  81                         reg = <0x10E30000 0x400>;
  82                         clocks = <&car 62>;
  83                         ldo-supply = <&ldo>;
  84                 };
  85
  86                 atlas7_iacc: atlas7_iacc@10D01000 {
  87                         #sound-dai-cells = <0>;
  88                         compatible = "sirf,atlas7-iacc";
  89                         reg = <0x10D01000 0x100>;
  90                         dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
  91                                 <&dmac3 3>, <&dmac3 9>;
  92                         dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
  93                         clocks = <&car 62>;
  94                 };
  95
  96                 ipc@13240000 {
  97                         compatible = "sirf,atlas7-ipc";
  98                         ranges = <0x13240000 0x13240000 0x00010000>;
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101
 102                         hwspinlock {
 103                                 compatible = "sirf,hwspinlock";
 104                                 reg = <0x13240000 0x00010000>;
 105
 106                                 num-spinlocks = <30>;
 107                         };
 108
 109                         ns_m3_rproc@0 {
 110                                 compatible = "sirf,ns2m30-rproc";
 111                                 reg = <0x13240000 0x00010000>;
 112                                 interrupts = <0 123 0>;
 113                         };
 114
 115                         ns_m3_rproc@1 {
 116                                 compatible = "sirf,ns2m31-rproc";
 117                                 reg = <0x13240000 0x00010000>;
 118                                 interrupts = <0 126 0>;
 119                         };
 120
 121                         ns_kal_rproc@0 {
 122                                 compatible = "sirf,ns2kal0-rproc";
 123                                 reg = <0x13240000 0x00010000>;
 124                                 interrupts = <0 124 0>;
 125                         };
 126
 127                         ns_kal_rproc@1 {
 128                                 compatible = "sirf,ns2kal1-rproc";
 129                                 reg = <0x13240000 0x00010000>;
 130                                 interrupts = <0 127 0>;
 131                         };
 132                 };
 133
 134                 pinctrl: ioc@18880000 {
 135                         compatible = "sirf,atlas7-ioc";
 136                         reg = <0x18880000 0x1000>,
 137                                 <0x10E40000 0x1000>;
 138
 139                         audio_ac97_pmx: audio_ac97@0 {
 140                                 audio_ac97 {
 141                                         groups = "audio_ac97_grp";
 142                                         function = "audio_ac97";
 143                                 };
 144                         };
 145
 146                         audio_func_dbg_pmx: audio_func_dbg@0 {
 147                                 audio_func_dbg {
 148                                         groups = "audio_func_dbg_grp";
 149                                         function = "audio_func_dbg";
 150                                 };
 151                         };
 152
 153                         audio_i2s_pmx: audio_i2s@0 {
 154                                 audio_i2s {
 155                                         groups = "audio_i2s_grp";
 156                                         function = "audio_i2s";
 157                                 };
 158                         };
 159
 160                         audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
 161                                 audio_i2s_2ch {
 162                                         groups = "audio_i2s_2ch_grp";
 163                                         function = "audio_i2s_2ch";
 164                                 };
 165                         };
 166
 167                         audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
 168                                 audio_i2s_extclk {
 169                                         groups = "audio_i2s_extclk_grp";
 170                                         function = "audio_i2s_extclk";
 171                                 };
 172                         };
 173
 174                         audio_uart0_pmx: audio_uart0@0 {
 175                                 audio_uart0 {
 176                                         groups = "audio_uart0_grp";
 177                                         function = "audio_uart0";
 178                                 };
 179                         };
 180
 181                         audio_uart1_pmx: audio_uart1@0 {
 182                                 audio_uart1 {
 183                                         groups = "audio_uart1_grp";
 184                                         function = "audio_uart1";
 185                                 };
 186                         };
 187
 188                         audio_uart2_pmx0: audio_uart2@0 {
 189                                 audio_uart2_0 {
 190                                         groups = "audio_uart2_grp0";
 191                                         function = "audio_uart2_m0";
 192                                 };
 193                         };
 194
 195                         audio_uart2_pmx1: audio_uart2@1 {
 196                                 audio_uart2_1 {
 197                                         groups = "audio_uart2_grp1";
 198                                         function = "audio_uart2_m1";
 199                                 };
 200                         };
 201
 202                         c_can_trnsvr_pmx: c_can_trnsvr@0 {
 203                                 c_can_trnsvr {
 204                                         groups = "c_can_trnsvr_grp";
 205                                         function = "c_can_trnsvr";
 206                                 };
 207                         };
 208
 209                         c0_can_pmx0: c0_can@0 {
 210                                 c0_can_0 {
 211                                         groups = "c0_can_grp0";
 212                                         function = "c0_can_m0";
 213                                 };
 214                         };
 215
 216                         c0_can_pmx1: c0_can@1 {
 217                                 c0_can_1 {
 218                                         groups = "c0_can_grp1";
 219                                         function = "c0_can_m1";
 220                                 };
 221                         };
 222
 223                         c1_can_pmx0: c1_can@0 {
 224                                 c1_can_0 {
 225                                         groups = "c1_can_grp0";
 226                                         function = "c1_can_m0";
 227                                 };
 228                         };
 229
 230                         c1_can_pmx1: c1_can@1 {
 231                                 c1_can_1 {
 232                                         groups = "c1_can_grp1";
 233                                         function = "c1_can_m1";
 234                                 };
 235                         };
 236
 237                         c1_can_pmx2: c1_can@2 {
 238                                 c1_can_2 {
 239                                         groups = "c1_can_grp2";
 240                                         function = "c1_can_m2";
 241                                 };
 242                         };
 243
 244                         ca_audio_lpc_pmx: ca_audio_lpc@0 {
 245                                 ca_audio_lpc {
 246                                         groups = "ca_audio_lpc_grp";
 247                                         function = "ca_audio_lpc";
 248                                 };
 249                         };
 250
 251                         ca_bt_lpc_pmx: ca_bt_lpc@0 {
 252                                 ca_bt_lpc {
 253                                         groups = "ca_bt_lpc_grp";
 254                                         function = "ca_bt_lpc";
 255                                 };
 256                         };
 257
 258                         ca_coex_pmx: ca_coex@0 {
 259                                 ca_coex {
 260                                         groups = "ca_coex_grp";
 261                                         function = "ca_coex";
 262                                 };
 263                         };
 264
 265                         ca_curator_lpc_pmx: ca_curator_lpc@0 {
 266                                 ca_curator_lpc {
 267                                         groups = "ca_curator_lpc_grp";
 268                                         function = "ca_curator_lpc";
 269                                 };
 270                         };
 271
 272                         ca_pcm_debug_pmx: ca_pcm_debug@0 {
 273                                 ca_pcm_debug {
 274                                         groups = "ca_pcm_debug_grp";
 275                                         function = "ca_pcm_debug";
 276                                 };
 277                         };
 278
 279                         ca_pio_pmx: ca_pio@0 {
 280                                 ca_pio {
 281                                         groups = "ca_pio_grp";
 282                                         function = "ca_pio";
 283                                 };
 284                         };
 285
 286                         ca_sdio_debug_pmx: ca_sdio_debug@0 {
 287                                 ca_sdio_debug {
 288                                         groups = "ca_sdio_debug_grp";
 289                                         function = "ca_sdio_debug";
 290                                 };
 291                         };
 292
 293                         ca_spi_pmx: ca_spi@0 {
 294                                 ca_spi {
 295                                         groups = "ca_spi_grp";
 296                                         function = "ca_spi";
 297                                 };
 298                         };
 299
 300                         ca_trb_pmx: ca_trb@0 {
 301                                 ca_trb {
 302                                         groups = "ca_trb_grp";
 303                                         function = "ca_trb";
 304                                 };
 305                         };
 306
 307                         ca_uart_debug_pmx: ca_uart_debug@0 {
 308                                 ca_uart_debug {
 309                                         groups = "ca_uart_debug_grp";
 310                                         function = "ca_uart_debug";
 311                                 };
 312                         };
 313
 314                         clkc_pmx0: clkc@0 {
 315                                 clkc_0 {
 316                                         groups = "clkc_grp0";
 317                                         function = "clkc_m0";
 318                                 };
 319                         };
 320
 321                         clkc_pmx1: clkc@1 {
 322                                 clkc_1 {
 323                                         groups = "clkc_grp1";
 324                                         function = "clkc_m1";
 325                                 };
 326                         };
 327
 328                         gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
 329                                 gn_gnss_i2c {
 330                                         groups = "gn_gnss_i2c_grp";
 331                                         function = "gn_gnss_i2c";
 332                                 };
 333                         };
 334
 335                         gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
 336                                 gn_gnss_uart_nopause {
 337                                         groups = "gn_gnss_uart_nopause_grp";
 338                                         function = "gn_gnss_uart_nopause";
 339                                 };
 340                         };
 341
 342                         gn_gnss_uart_pmx: gn_gnss_uart@0 {
 343                                 gn_gnss_uart {
 344                                         groups = "gn_gnss_uart_grp";
 345                                         function = "gn_gnss_uart";
 346                                 };
 347                         };
 348
 349                         gn_trg_spi_pmx0: gn_trg_spi@0 {
 350                                 gn_trg_spi_0 {
 351                                         groups = "gn_trg_spi_grp0";
 352                                         function = "gn_trg_spi_m0";
 353                                 };
 354                         };
 355
 356                         gn_trg_spi_pmx1: gn_trg_spi@1 {
 357                                 gn_trg_spi_1 {
 358                                         groups = "gn_trg_spi_grp1";
 359                                         function = "gn_trg_spi_m1";
 360                                 };
 361                         };
 362
 363                         cvbs_dbg_pmx: cvbs_dbg@0 {
 364                                 cvbs_dbg {
 365                                         groups = "cvbs_dbg_grp";
 366                                         function = "cvbs_dbg";
 367                                 };
 368                         };
 369
 370                         cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
 371                                 cvbs_dbg_test_0 {
 372                                         groups = "cvbs_dbg_test_grp0";
 373                                         function = "cvbs_dbg_test_m0";
 374                                 };
 375                         };
 376
 377                         cvbs_dbg_test_pmx1: cvbs_dbg_test@1 {
 378                                 cvbs_dbg_test_1 {
 379                                         groups = "cvbs_dbg_test_grp1";
 380                                         function = "cvbs_dbg_test_m1";
 381                                 };
 382                         };
 383
 384                         cvbs_dbg_test_pmx2: cvbs_dbg_test@2 {
 385                                 cvbs_dbg_test_2 {
 386                                         groups = "cvbs_dbg_test_grp2";
 387                                         function = "cvbs_dbg_test_m2";
 388                                 };
 389                         };
 390
 391                         cvbs_dbg_test_pmx3: cvbs_dbg_test@3 {
 392                                 cvbs_dbg_test_3 {
 393                                         groups = "cvbs_dbg_test_grp3";
 394                                         function = "cvbs_dbg_test_m3";
 395                                 };
 396                         };
 397
 398                         cvbs_dbg_test_pmx4: cvbs_dbg_test@4 {
 399                                 cvbs_dbg_test_4 {
 400                                         groups = "cvbs_dbg_test_grp4";
 401                                         function = "cvbs_dbg_test_m4";
 402                                 };
 403                         };
 404
 405                         cvbs_dbg_test_pmx5: cvbs_dbg_test@5 {
 406                                 cvbs_dbg_test_5 {
 407                                         groups = "cvbs_dbg_test_grp5";
 408                                         function = "cvbs_dbg_test_m5";
 409                                 };
 410                         };
 411
 412                         cvbs_dbg_test_pmx6: cvbs_dbg_test@6 {
 413                                 cvbs_dbg_test_6 {
 414                                         groups = "cvbs_dbg_test_grp6";
 415                                         function = "cvbs_dbg_test_m6";
 416                                 };
 417                         };
 418
 419                         cvbs_dbg_test_pmx7: cvbs_dbg_test@7 {
 420                                 cvbs_dbg_test_7 {
 421                                         groups = "cvbs_dbg_test_grp7";
 422                                         function = "cvbs_dbg_test_m7";
 423                                 };
 424                         };
 425
 426                         cvbs_dbg_test_pmx8: cvbs_dbg_test@8 {
 427                                 cvbs_dbg_test_8 {
 428                                         groups = "cvbs_dbg_test_grp8";
 429                                         function = "cvbs_dbg_test_m8";
 430                                 };
 431                         };
 432
 433                         cvbs_dbg_test_pmx9: cvbs_dbg_test@9 {
 434                                 cvbs_dbg_test_9 {
 435                                         groups = "cvbs_dbg_test_grp9";
 436                                         function = "cvbs_dbg_test_m9";
 437                                 };
 438                         };
 439
 440                         cvbs_dbg_test_pmx10: cvbs_dbg_test@10 {
 441                                 cvbs_dbg_test_10 {
 442                                         groups = "cvbs_dbg_test_grp10";
 443                                         function = "cvbs_dbg_test_m10";
 444                                 };
 445                         };
 446
 447                         cvbs_dbg_test_pmx11: cvbs_dbg_test@11 {
 448                                 cvbs_dbg_test_11 {
 449                                         groups = "cvbs_dbg_test_grp11";
 450                                         function = "cvbs_dbg_test_m11";
 451                                 };
 452                         };
 453
 454                         cvbs_dbg_test_pmx12: cvbs_dbg_test@12 {
 455                                 cvbs_dbg_test_12 {
 456                                         groups = "cvbs_dbg_test_grp12";
 457                                         function = "cvbs_dbg_test_m12";
 458                                 };
 459                         };
 460
 461                         cvbs_dbg_test_pmx13: cvbs_dbg_test@13 {
 462                                 cvbs_dbg_test_13 {
 463                                         groups = "cvbs_dbg_test_grp13";
 464                                         function = "cvbs_dbg_test_m13";
 465                                 };
 466                         };
 467
 468                         cvbs_dbg_test_pmx14: cvbs_dbg_test@14 {
 469                                 cvbs_dbg_test_14 {
 470                                         groups = "cvbs_dbg_test_grp14";
 471                                         function = "cvbs_dbg_test_m14";
 472                                 };
 473                         };
 474
 475                         cvbs_dbg_test_pmx15: cvbs_dbg_test@15 {
 476                                 cvbs_dbg_test_15 {
 477                                         groups = "cvbs_dbg_test_grp15";
 478                                         function = "cvbs_dbg_test_m15";
 479                                 };
 480                         };
 481
 482                         gn_gnss_power_pmx: gn_gnss_power@0 {
 483                                 gn_gnss_power {
 484                                         groups = "gn_gnss_power_grp";
 485                                         function = "gn_gnss_power";
 486                                 };
 487                         };
 488
 489                         gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
 490                                 gn_gnss_sw_status {
 491                                         groups = "gn_gnss_sw_status_grp";
 492                                         function = "gn_gnss_sw_status";
 493                                 };
 494                         };
 495
 496                         gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
 497                                 gn_gnss_eclk {
 498                                         groups = "gn_gnss_eclk_grp";
 499                                         function = "gn_gnss_eclk";
 500                                 };
 501                         };
 502
 503                         gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
 504                                 gn_gnss_irq1_0 {
 505                                         groups = "gn_gnss_irq1_grp0";
 506                                         function = "gn_gnss_irq1_m0";
 507                                 };
 508                         };
 509
 510                         gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
 511                                 gn_gnss_irq2_0 {
 512                                         groups = "gn_gnss_irq2_grp0";
 513                                         function = "gn_gnss_irq2_m0";
 514                                 };
 515                         };
 516
 517                         gn_gnss_tm_pmx: gn_gnss_tm@0 {
 518                                 gn_gnss_tm {
 519                                         groups = "gn_gnss_tm_grp";
 520                                         function = "gn_gnss_tm";
 521                                 };
 522                         };
 523
 524                         gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
 525                                 gn_gnss_tsync {
 526                                         groups = "gn_gnss_tsync_grp";
 527                                         function = "gn_gnss_tsync";
 528                                 };
 529                         };
 530
 531                         gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
 532                                 gn_io_gnsssys_sw_cfg {
 533                                         groups = "gn_io_gnsssys_sw_cfg_grp";
 534                                         function = "gn_io_gnsssys_sw_cfg";
 535                                 };
 536                         };
 537
 538                         gn_trg_pmx0: gn_trg@0 {
 539                                 gn_trg_0 {
 540                                         groups = "gn_trg_grp0";
 541                                         function = "gn_trg_m0";
 542                                 };
 543                         };
 544
 545                         gn_trg_pmx1: gn_trg@1 {
 546                                 gn_trg_1 {
 547                                         groups = "gn_trg_grp1";
 548                                         function = "gn_trg_m1";
 549                                 };
 550                         };
 551
 552                         gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
 553                                 gn_trg_shutdown_0 {
 554                                         groups = "gn_trg_shutdown_grp0";
 555                                         function = "gn_trg_shutdown_m0";
 556                                 };
 557                         };
 558
 559                         gn_trg_shutdown_pmx1: gn_trg_shutdown@1 {
 560                                 gn_trg_shutdown_1 {
 561                                         groups = "gn_trg_shutdown_grp1";
 562                                         function = "gn_trg_shutdown_m1";
 563                                 };
 564                         };
 565
 566                         gn_trg_shutdown_pmx2: gn_trg_shutdown@2 {
 567                                 gn_trg_shutdown_2 {
 568                                         groups = "gn_trg_shutdown_grp2";
 569                                         function = "gn_trg_shutdown_m2";
 570                                 };
 571                         };
 572
 573                         gn_trg_shutdown_pmx3: gn_trg_shutdown@3 {
 574                                 gn_trg_shutdown_3 {
 575                                         groups = "gn_trg_shutdown_grp3";
 576                                         function = "gn_trg_shutdown_m3";
 577                                 };
 578                         };
 579
 580                         i2c0_pmx: i2c0@0 {
 581                                 i2c0 {
 582                                         groups = "i2c0_grp";
 583                                         function = "i2c0";
 584                                 };
 585                         };
 586
 587                         i2c1_pmx: i2c1@0 {
 588                                 i2c1 {
 589                                         groups = "i2c1_grp";
 590                                         function = "i2c1";
 591                                 };
 592                         };
 593
 594                         jtag_pmx0: jtag@0 {
 595                                 jtag_0 {
 596                                         groups = "jtag_grp0";
 597                                         function = "jtag_m0";
 598                                 };
 599                         };
 600
 601                         ks_kas_spi_pmx0: ks_kas_spi@0 {
 602                                 ks_kas_spi_0 {
 603                                         groups = "ks_kas_spi_grp0";
 604                                         function = "ks_kas_spi_m0";
 605                                 };
 606                         };
 607
 608                         ld_ldd_pmx: ld_ldd@0 {
 609                                 ld_ldd {
 610                                         groups = "ld_ldd_grp";
 611                                         function = "ld_ldd";
 612                                 };
 613                         };
 614
 615                         ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
 616                                 ld_ldd_16bit {
 617                                         groups = "ld_ldd_16bit_grp";
 618                                         function = "ld_ldd_16bit";
 619                                 };
 620                         };
 621
 622                         ld_ldd_fck_pmx: ld_ldd_fck@0 {
 623                                 ld_ldd_fck {
 624                                         groups = "ld_ldd_fck_grp";
 625                                         function = "ld_ldd_fck";
 626                                 };
 627                         };
 628
 629                         ld_ldd_lck_pmx: ld_ldd_lck@0 {
 630                                 ld_ldd_lck {
 631                                         groups = "ld_ldd_lck_grp";
 632                                         function = "ld_ldd_lck";
 633                                 };
 634                         };
 635
 636                         lr_lcdrom_pmx: lr_lcdrom@0 {
 637                                 lr_lcdrom {
 638                                         groups = "lr_lcdrom_grp";
 639                                         function = "lr_lcdrom";
 640                                 };
 641                         };
 642
 643                         lvds_analog_pmx: lvds_analog@0 {
 644                                 lvds_analog {
 645                                         groups = "lvds_analog_grp";
 646                                         function = "lvds_analog";
 647                                 };
 648                         };
 649
 650                         nd_df_pmx: nd_df@0 {
 651                                 nd_df {
 652                                         groups = "nd_df_grp";
 653                                         function = "nd_df";
 654                                 };
 655                         };
 656
 657                         nd_df_nowp_pmx: nd_df_nowp@0 {
 658                                 nd_df_nowp {
 659                                         groups = "nd_df_nowp_grp";
 660                                         function = "nd_df_nowp";
 661                                 };
 662                         };
 663
 664                         ps_pmx: ps@0 {
 665                                 ps {
 666                                         groups = "ps_grp";
 667                                         function = "ps";
 668                                 };
 669                         };
 670
 671                         pwc_core_on_pmx: pwc_core_on@0 {
 672                                 pwc_core_on {
 673                                         groups = "pwc_core_on_grp";
 674                                         function = "pwc_core_on";
 675                                 };
 676                         };
 677
 678                         pwc_ext_on_pmx: pwc_ext_on@0 {
 679                                 pwc_ext_on {
 680                                         groups = "pwc_ext_on_grp";
 681                                         function = "pwc_ext_on";
 682                                 };
 683                         };
 684
 685                         pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
 686                                 pwc_gpio3_clk {
 687                                         groups = "pwc_gpio3_clk_grp";
 688                                         function = "pwc_gpio3_clk";
 689                                 };
 690                         };
 691
 692                         pwc_io_on_pmx: pwc_io_on@0 {
 693                                 pwc_io_on {
 694                                         groups = "pwc_io_on_grp";
 695                                         function = "pwc_io_on";
 696                                 };
 697                         };
 698
 699                         pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
 700                                 pwc_lowbatt_b_0 {
 701                                         groups = "pwc_lowbatt_b_grp0";
 702                                         function = "pwc_lowbatt_b_m0";
 703                                 };
 704                         };
 705
 706                         pwc_mem_on_pmx: pwc_mem_on@0 {
 707                                 pwc_mem_on {
 708                                         groups = "pwc_mem_on_grp";
 709                                         function = "pwc_mem_on";
 710                                 };
 711                         };
 712
 713                         pwc_on_key_b_pmx0: pwc_on_key_b@0 {
 714                                 pwc_on_key_b_0 {
 715                                         groups = "pwc_on_key_b_grp0";
 716                                         function = "pwc_on_key_b_m0";
 717                                 };
 718                         };
 719
 720                         pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
 721                                 pwc_wakeup_src0 {
 722                                         groups = "pwc_wakeup_src0_grp";
 723                                         function = "pwc_wakeup_src0";
 724                                 };
 725                         };
 726
 727                         pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
 728                                 pwc_wakeup_src1 {
 729                                         groups = "pwc_wakeup_src1_grp";
 730                                         function = "pwc_wakeup_src1";
 731                                 };
 732                         };
 733
 734                         pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
 735                                 pwc_wakeup_src2 {
 736                                         groups = "pwc_wakeup_src2_grp";
 737                                         function = "pwc_wakeup_src2";
 738                                 };
 739                         };
 740
 741                         pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
 742                                 pwc_wakeup_src3 {
 743                                         groups = "pwc_wakeup_src3_grp";
 744                                         function = "pwc_wakeup_src3";
 745                                 };
 746                         };
 747
 748                         pw_cko0_pmx0: pw_cko0@0 {
 749                                 pw_cko0_0 {
 750                                         groups = "pw_cko0_grp0";
 751                                         function = "pw_cko0_m0";
 752                                 };
 753                         };
 754
 755                         pw_cko0_pmx1: pw_cko0@1 {
 756                                 pw_cko0_1 {
 757                                         groups = "pw_cko0_grp1";
 758                                         function = "pw_cko0_m1";
 759                                 };
 760                         };
 761
 762                         pw_cko0_pmx2: pw_cko0@2 {
 763                                 pw_cko0_2 {
 764                                         groups = "pw_cko0_grp2";
 765                                         function = "pw_cko0_m2";
 766                                 };
 767                         };
 768
 769                         pw_cko1_pmx0: pw_cko1@0 {
 770                                 pw_cko1_0 {
 771                                         groups = "pw_cko1_grp0";
 772                                         function = "pw_cko1_m0";
 773                                 };
 774                         };
 775
 776                         pw_cko1_pmx1: pw_cko1@1 {
 777                                 pw_cko1_1 {
 778                                         groups = "pw_cko1_grp1";
 779                                         function = "pw_cko1_m1";
 780                                 };
 781                         };
 782
 783                         pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
 784                                 pw_i2s01_clk_0 {
 785                                         groups = "pw_i2s01_clk_grp0";
 786                                         function = "pw_i2s01_clk_m0";
 787                                 };
 788                         };
 789
 790                         pw_i2s01_clk_pmx1: pw_i2s01_clk@1 {
 791                                 pw_i2s01_clk_1 {
 792                                         groups = "pw_i2s01_clk_grp1";
 793                                         function = "pw_i2s01_clk_m1";
 794                                 };
 795                         };
 796
 797                         pw_pwm0_pmx: pw_pwm0@0 {
 798                                 pw_pwm0 {
 799                                         groups = "pw_pwm0_grp";
 800                                         function = "pw_pwm0";
 801                                 };
 802                         };
 803
 804                         pw_pwm1_pmx: pw_pwm1@0 {
 805                                 pw_pwm1 {
 806                                         groups = "pw_pwm1_grp";
 807                                         function = "pw_pwm1";
 808                                 };
 809                         };
 810
 811                         pw_pwm2_pmx0: pw_pwm2@0 {
 812                                 pw_pwm2_0 {
 813                                         groups = "pw_pwm2_grp0";
 814                                         function = "pw_pwm2_m0";
 815                                 };
 816                         };
 817
 818                         pw_pwm2_pmx1: pw_pwm2@1 {
 819                                 pw_pwm2_1 {
 820                                         groups = "pw_pwm2_grp1";
 821                                         function = "pw_pwm2_m1";
 822                                 };
 823                         };
 824
 825                         pw_pwm3_pmx0: pw_pwm3@0 {
 826                                 pw_pwm3_0 {
 827                                         groups = "pw_pwm3_grp0";
 828                                         function = "pw_pwm3_m0";
 829                                 };
 830                         };
 831
 832                         pw_pwm3_pmx1: pw_pwm3@1 {
 833                                 pw_pwm3_1 {
 834                                         groups = "pw_pwm3_grp1";
 835                                         function = "pw_pwm3_m1";
 836                                 };
 837                         };
 838
 839                         pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
 840                                 pw_pwm_cpu_vol_0 {
 841                                         groups = "pw_pwm_cpu_vol_grp0";
 842                                         function = "pw_pwm_cpu_vol_m0";
 843                                 };
 844                         };
 845
 846                         pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 {
 847                                 pw_pwm_cpu_vol_1 {
 848                                         groups = "pw_pwm_cpu_vol_grp1";
 849                                         function = "pw_pwm_cpu_vol_m1";
 850                                 };
 851                         };
 852
 853                         pw_backlight_pmx0: pw_backlight@0 {
 854                                 pw_backlight_0 {
 855                                         groups = "pw_backlight_grp0";
 856                                         function = "pw_backlight_m0";
 857                                 };
 858                         };
 859
 860                         pw_backlight_pmx1: pw_backlight@1 {
 861                                 pw_backlight_1 {
 862                                         groups = "pw_backlight_grp1";
 863                                         function = "pw_backlight_m1";
 864                                 };
 865                         };
 866
 867                         rg_eth_mac_pmx: rg_eth_mac@0 {
 868                                 rg_eth_mac {
 869                                         groups = "rg_eth_mac_grp";
 870                                         function = "rg_eth_mac";
 871                                 };
 872                         };
 873
 874                         rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
 875                                 rg_gmac_phy_intr_n {
 876                                         groups = "rg_gmac_phy_intr_n_grp";
 877                                         function = "rg_gmac_phy_intr_n";
 878                                 };
 879                         };
 880
 881                         rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
 882                                 rg_rgmii_mac {
 883                                         groups = "rg_rgmii_mac_grp";
 884                                         function = "rg_rgmii_mac";
 885                                 };
 886                         };
 887
 888                         rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
 889                                 rg_rgmii_phy_ref_clk_0 {
 890                                         groups =
 891                                                 "rg_rgmii_phy_ref_clk_grp0";
 892                                         function =
 893                                                 "rg_rgmii_phy_ref_clk_m0";
 894                                 };
 895                         };
 896
 897                         rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 {
 898                                 rg_rgmii_phy_ref_clk_1 {
 899                                         groups =
 900                                                 "rg_rgmii_phy_ref_clk_grp1";
 901                                         function =
 902                                                 "rg_rgmii_phy_ref_clk_m1";
 903                                 };
 904                         };
 905
 906                         sd0_pmx: sd0@0 {
 907                                 sd0 {
 908                                         groups = "sd0_grp";
 909                                         function = "sd0";
 910                                 };
 911                         };
 912
 913                         sd0_4bit_pmx: sd0_4bit@0 {
 914                                 sd0_4bit {
 915                                         groups = "sd0_4bit_grp";
 916                                         function = "sd0_4bit";
 917                                 };
 918                         };
 919
 920                         sd1_pmx: sd1@0 {
 921                                 sd1 {
 922                                         groups = "sd1_grp";
 923                                         function = "sd1";
 924                                 };
 925                         };
 926
 927                         sd1_4bit_pmx0: sd1_4bit@0 {
 928                                 sd1_4bit_0 {
 929                                         groups = "sd1_4bit_grp0";
 930                                         function = "sd1_4bit_m0";
 931                                 };
 932                         };
 933
 934                         sd1_4bit_pmx1: sd1_4bit@1 {
 935                                 sd1_4bit_1 {
 936                                         groups = "sd1_4bit_grp1";
 937                                         function = "sd1_4bit_m1";
 938                                 };
 939                         };
 940
 941                         sd2_pmx0: sd2@0 {
 942                                 sd2_0 {
 943                                         groups = "sd2_grp0";
 944                                         function = "sd2_m0";
 945                                 };
 946                         };
 947
 948                         sd2_no_cdb_pmx0: sd2_no_cdb@0 {
 949                                 sd2_no_cdb_0 {
 950                                         groups = "sd2_no_cdb_grp0";
 951                                         function = "sd2_no_cdb_m0";
 952                                 };
 953                         };
 954
 955                         sd3_pmx: sd3@0 {
 956                                 sd3 {
 957                                         groups = "sd3_grp";
 958                                         function = "sd3";
 959                                 };
 960                         };
 961
 962                         sd5_pmx: sd5@0 {
 963                                 sd5 {
 964                                         groups = "sd5_grp";
 965                                         function = "sd5";
 966                                 };
 967                         };
 968
 969                         sd6_pmx0: sd6@0 {
 970                                 sd6_0 {
 971                                         groups = "sd6_grp0";
 972                                         function = "sd6_m0";
 973                                 };
 974                         };
 975
 976                         sd6_pmx1: sd6@1 {
 977                                 sd6_1 {
 978                                         groups = "sd6_grp1";
 979                                         function = "sd6_m1";
 980                                 };
 981                         };
 982
 983                         sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
 984                                 sp0_ext_ldo_on {
 985                                         groups = "sp0_ext_ldo_on_grp";
 986                                         function = "sp0_ext_ldo_on";
 987                                 };
 988                         };
 989
 990                         sp0_qspi_pmx: sp0_qspi@0 {
 991                                 sp0_qspi {
 992                                         groups = "sp0_qspi_grp";
 993                                         function = "sp0_qspi";
 994                                 };
 995                         };
 996
 997                         sp1_spi_pmx: sp1_spi@0 {
 998                                 sp1_spi {
 999                                         groups = "sp1_spi_grp";
1000                                         function = "sp1_spi";
1001                                 };
1002                         };
1003
1004                         tpiu_trace_pmx: tpiu_trace@0 {
1005                                 tpiu_trace {
1006                                         groups = "tpiu_trace_grp";
1007                                         function = "tpiu_trace";
1008                                 };
1009                         };
1010
1011                         uart0_pmx: uart0@0 {
1012                                 uart0 {
1013                                         groups = "uart0_grp";
1014                                         function = "uart0";
1015                                 };
1016                         };
1017
1018                         uart0_nopause_pmx: uart0_nopause@0 {
1019                                 uart0_nopause {
1020                                         groups = "uart0_nopause_grp";
1021                                         function = "uart0_nopause";
1022                                 };
1023                         };
1024
1025                         uart1_pmx: uart1@0 {
1026                                 uart1 {
1027                                         groups = "uart1_grp";
1028                                         function = "uart1";
1029                                 };
1030                         };
1031
1032                         uart2_pmx: uart2@0 {
1033                                 uart2 {
1034                                         groups = "uart2_grp";
1035                                         function = "uart2";
1036                                 };
1037                         };
1038
1039                         uart3_pmx0: uart3@0 {
1040                                 uart3_0 {
1041                                         groups = "uart3_grp0";
1042                                         function = "uart3_m0";
1043                                 };
1044                         };
1045
1046                         uart3_pmx1: uart3@1 {
1047                                 uart3_1 {
1048                                         groups = "uart3_grp1";
1049                                         function = "uart3_m1";
1050                                 };
1051                         };
1052
1053                         uart3_pmx2: uart3@2 {
1054                                 uart3_2 {
1055                                         groups = "uart3_grp2";
1056                                         function = "uart3_m2";
1057                                 };
1058                         };
1059
1060                         uart3_pmx3: uart3@3 {
1061                                 uart3_3 {
1062                                         groups = "uart3_grp3";
1063                                         function = "uart3_m3";
1064                                 };
1065                         };
1066
1067                         uart3_nopause_pmx0: uart3_nopause@0 {
1068                                 uart3_nopause_0 {
1069                                         groups = "uart3_nopause_grp0";
1070                                         function = "uart3_nopause_m0";
1071                                 };
1072                         };
1073
1074                         uart3_nopause_pmx1: uart3_nopause@1 {
1075                                 uart3_nopause_1 {
1076                                         groups = "uart3_nopause_grp1";
1077                                         function = "uart3_nopause_m1";
1078                                 };
1079                         };
1080
1081                         uart4_pmx0: uart4@0 {
1082                                 uart4_0 {
1083                                         groups = "uart4_grp0";
1084                                         function = "uart4_m0";
1085                                 };
1086                         };
1087
1088                         uart4_pmx1: uart4@1 {
1089                                 uart4_1 {
1090                                         groups = "uart4_grp1";
1091                                         function = "uart4_m1";
1092                                 };
1093                         };
1094
1095                         uart4_pmx2: uart4@2 {
1096                                 uart4_2 {
1097                                         groups = "uart4_grp2";
1098                                         function = "uart4_m2";
1099                                 };
1100                         };
1101
1102                         uart4_nopause_pmx: uart4_nopause@0 {
1103                                 uart4_nopause {
1104                                         groups = "uart4_nopause_grp";
1105                                         function = "uart4_nopause";
1106                                 };
1107                         };
1108
1109                         usb0_drvvbus_pmx: usb0_drvvbus@0 {
1110                                 usb0_drvvbus {
1111                                         groups = "usb0_drvvbus_grp";
1112                                         function = "usb0_drvvbus";
1113                                 };
1114                         };
1115
1116                         usb1_drvvbus_pmx: usb1_drvvbus@0 {
1117                                 usb1_drvvbus {
1118                                         groups = "usb1_drvvbus_grp";
1119                                         function = "usb1_drvvbus";
1120                                 };
1121                         };
1122
1123                         visbus_dout_pmx: visbus_dout@0 {
1124                                 visbus_dout {
1125                                         groups = "visbus_dout_grp";
1126                                         function = "visbus_dout";
1127                                 };
1128                         };
1129
1130                         vi_vip1_pmx: vi_vip1@0 {
1131                                 vi_vip1 {
1132                                         groups = "vi_vip1_grp";
1133                                         function = "vi_vip1";
1134                                 };
1135                         };
1136
1137                         vi_vip1_ext_pmx: vi_vip1_ext@0 {
1138                                 vi_vip1_ext {
1139                                         groups = "vi_vip1_ext_grp";
1140                                         function = "vi_vip1_ext";
1141                                 };
1142                         };
1143
1144                         vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
1145                                 vi_vip1_low8bit {
1146                                         groups = "vi_vip1_low8bit_grp";
1147                                         function = "vi_vip1_low8bit";
1148                                 };
1149                         };
1150
1151                         vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
1152                                 vi_vip1_high8bit {
1153                                         groups = "vi_vip1_high8bit_grp";
1154                                         function = "vi_vip1_high8bit";
1155                                 };
1156                         };
1157                 };
1158
1159                 pmipc {
1160                         compatible = "arteris, flexnoc", "simple-bus";
1161                         #address-cells = <1>;
1162                         #size-cells = <1>;
1163                         ranges = <0x13240000 0x13240000 0x00010000>;
1164                         pmipc@0x13240000 {
1165                                 compatible = "sirf,atlas7-pmipc";
1166                                 reg = <0x13240000 0x00010000>;
1167                         };
1168                 };
1169
1170                 dramfw {
1171                         compatible = "arteris, flexnoc", "simple-bus";
1172                         #address-cells = <1>;
1173                         #size-cells = <1>;
1174                         ranges = <0x10830000 0x10830000 0x18000>;
1175                         dramfw@10820000 {
1176                                 compatible = "sirf,nocfw-dramfw";
1177                                 reg = <0x10830000 0x18000>;
1178                         };
1179                 };
1180
1181                 spramfw {
1182                         compatible = "arteris, flexnoc", "simple-bus";
1183                         #address-cells = <1>;
1184                         #size-cells = <1>;
1185                         ranges = <0x10250000 0x10250000 0x3000>;
1186                         spramfw@10820000 {
1187                                 compatible = "sirf,nocfw-spramfw";
1188                                 reg = <0x10250000 0x3000>;
1189                         };
1190                 };
1191
1192                 cpum {
1193                         compatible = "arteris, flexnoc", "simple-bus";
1194                         #address-cells = <1>;
1195                         #size-cells = <1>;
1196                         ranges = <0x10200000 0x10200000 0x3000>;
1197                         cpum@10200000 {
1198                                 compatible = "sirf,nocfw-cpum";
1199                                 reg = <0x10200000 0x3000>;
1200                         };
1201                 };
1202
1203                 cgum {
1204                         compatible = "arteris, flexnoc", "simple-bus";
1205                         #address-cells = <1>;
1206                         #size-cells = <1>;
1207                         ranges = <0x18641000 0x18641000 0x3000>,
1208                                          <0x18620000 0x18620000 0x1000>;
1209
1210                         cgum@18641000 {
1211                                 compatible = "sirf,nocfw-cgum";
1212                                 reg = <0x18641000 0x3000>;
1213                         };
1214
1215                         car: clock-controller@18620000 {
1216                                 compatible = "sirf,atlas7-car";
1217                                 reg = <0x18620000 0x1000>;
1218                                 #clock-cells = <1>;
1219                                 #reset-cells = <1>;
1220                         };
1221                 };
1222
1223                 gnssm {
1224                         compatible = "arteris, flexnoc", "simple-bus";
1225                         #address-cells = <1>;
1226                         #size-cells = <1>;
1227                         ranges = <0x18000000 0x18000000 0x0000ffff>,
1228                                 <0x18010000 0x18010000 0x1000>,
1229                                 <0x18020000 0x18020000 0x1000>,
1230                                 <0x18030000 0x18030000 0x1000>,
1231                                 <0x18040000 0x18040000 0x1000>,
1232                                 <0x18050000 0x18050000 0x1000>,
1233                                 <0x18060000 0x18060000 0x1000>,
1234                                 <0x18100000 0x18100000 0x3000>,
1235                                 <0x18250000 0x18250000 0x10000>,
1236                                 <0x18200000 0x18200000 0x1000>;
1237
1238                         dmac0: dma-controller@18000000 {
1239                                 cell-index = <0>;
1240                                 compatible = "sirf,atlas7-dmac";
1241                                 reg = <0x18000000 0x1000>;
1242                                 interrupts = <0 12 0>;
1243                                 clocks = <&car 89>;
1244                                 dma-channels = <16>;
1245                                 #dma-cells = <1>;
1246                         };
1247
1248                         gnssmfw@0x18100000 {
1249                                 compatible = "sirf,nocfw-gnssm";
1250                                 reg = <0x18100000 0x3000>;
1251                         };
1252
1253                         uart0: uart@18010000 {
1254                                 cell-index = <0>;
1255                                 compatible = "sirf,atlas7-uart";
1256                                 reg = <0x18010000 0x1000>;
1257                                 interrupts = <0 17 0>;
1258                                 clocks = <&car 90>;
1259                                 fifosize = <128>;
1260                                 dmas = <&dmac0 3>, <&dmac0 2>;
1261                                 dma-names = "rx", "tx";
1262                         };
1263
1264                         uart1: uart@18020000 {
1265                                 cell-index = <1>;
1266                                 compatible = "sirf,atlas7-uart";
1267                                 reg = <0x18020000 0x1000>;
1268                                 interrupts = <0 18 0>;
1269                                 clocks = <&car 88>;
1270                                 fifosize = <32>;
1271                         };
1272
1273                         uart2: uart@18030000 {
1274                                 cell-index = <2>;
1275                                 compatible = "sirf,atlas7-uart";
1276                                 reg = <0x18030000 0x1000>;
1277                                 interrupts = <0 19 0>;
1278                                 clocks = <&car 91>;
1279                                 fifosize = <128>;
1280                                 dmas = <&dmac0 6>, <&dmac0 7>;
1281                                 dma-names = "rx", "tx";
1282                                 status = "disabled";
1283                         };
1284                         uart3: uart@18040000 {
1285                                 cell-index = <3>;
1286                                 compatible = "sirf,atlas7-uart";
1287                                 reg = <0x18040000 0x1000>;
1288                                 interrupts = <0 66 0>;
1289                                 clocks = <&car 92>;
1290                                 fifosize = <128>;
1291                                 dmas = <&dmac0 4>, <&dmac0 5>;
1292                                 dma-names = "rx", "tx";
1293                                 status = "disabled";
1294                         };
1295                         uart4: uart@18050000 {
1296                                 cell-index = <4>;
1297                                 compatible = "sirf,atlas7-uart";
1298                                 reg = <0x18050000 0x1000>;
1299                                 interrupts = <0 69 0>;
1300                                 clocks = <&car 93>;
1301                                 fifosize = <128>;
1302                                 dmas = <&dmac0 0>, <&dmac0 1>;
1303                                 dma-names = "rx", "tx";
1304                                 status = "disabled";
1305                         };
1306                         uart5: uart@18060000 {
1307                                 cell-index = <5>;
1308                                 compatible = "sirf,atlas7-uart";
1309                                 reg = <0x18060000 0x1000>;
1310                                 interrupts = <0 71 0>;
1311                                 clocks = <&car 94>;
1312                                 fifosize = <128>;
1313                                 dmas = <&dmac0 8>, <&dmac0 9>;
1314                                 dma-names = "rx", "tx";
1315                                 status = "disabled";
1316                         };
1317                         dspub@18250000 {
1318                                 compatible = "dx,cc44p";
1319                                 reg = <0x18250000 0x10000>;
1320                                 interrupts = <0 27 0>;
1321                         };
1322
1323                         spi1: spi@18200000 {
1324                                 compatible = "sirf,prima2-spi";
1325                                 reg = <0x18200000 0x1000>;
1326                                 interrupts = <0 16 0>;
1327                                 clocks = <&car 95>;
1328                                 #address-cells = <1>;
1329                                 #size-cells = <0>;
1330                                 dmas = <&dmac0 12>, <&dmac0 13>;
1331                                 dma-names = "rx", "tx";
1332                                 status = "disabled";
1333                         };
1334                 };
1335
1336
1337                 gpum {
1338                         compatible = "arteris, flexnoc", "simple-bus";
1339                         #address-cells = <1>;
1340                         #size-cells = <1>;
1341                         ranges = <0x13000000 0x13000000 0x3000>;
1342                         gpum@0x13000000 {
1343                                 compatible = "sirf,nocfw-gpum";
1344                                 reg = <0x13000000 0x3000>;
1345                         };
1346                 };
1347
1348                 mediam {
1349                         compatible = "arteris, flexnoc", "simple-bus";
1350                         #address-cells = <1>;
1351                         #size-cells = <1>;
1352                         ranges = <0x16000000 0x16000000 0x00200000>,
1353                                 <0x17020000 0x17020000 0x1000>,
1354                                 <0x17030000 0x17030000 0x1000>,
1355                                 <0x17040000 0x17040000 0x1000>,
1356                                 <0x17050000 0x17050000 0x10000>,
1357                                 <0x17060000 0x17060000 0x200>,
1358                                 <0x17060200 0x17060200 0x100>,
1359                                 <0x17070000 0x17070000 0x200>,
1360                                 <0x17070200 0x17070200 0x100>,
1361                                 <0x170A0000 0x170A0000 0x3000>;
1362
1363                         mediam@170A0000 {
1364                                 compatible = "sirf,nocfw-mediam";
1365                                 reg = <0x170A0000 0x3000>;
1366                         };
1367
1368                         gpio_0: gpio_mediam@17040000 {
1369                                 #gpio-cells = <2>;
1370                                 #interrupt-cells = <2>;
1371                                 compatible = "sirf,atlas7-gpio";
1372                                 reg = <0x17040000 0x1000>;
1373                                 interrupts = <0 13 0>, <0 14 0>;
1374                                 clocks = <&car 107>;
1375                                 clock-names = "gpio0_io";
1376                                 gpio-controller;
1377                                 interrupt-controller;
1378
1379                                 gpio-banks = <2>;
1380                                 gpio-ranges = <&pinctrl 0 0 0>,
1381                                                 <&pinctrl 32 0 0>;
1382                                 gpio-ranges-group-names = "lvds_gpio_grp",
1383                                                         "uart_nand_gpio_grp";
1384                         };
1385
1386                         nand@17050000 {
1387                                 compatible = "sirf,atlas7-nand";
1388                                 reg = <0x17050000 0x10000>;
1389                                 interrupts = <0 41 0>;
1390                                 clocks = <&car 108>, <&car 112>;
1391                                 clock-names = "nand_io", "nand_nand";
1392                         };
1393
1394                         sd0: sdhci@16000000 {
1395                                 cell-index = <0>;
1396                                 compatible = "sirf,atlas7-sdhc";
1397                                 reg = <0x16000000 0x100000>;
1398                                 interrupts = <0 38 0>;
1399                                 clocks = <&car 109>, <&car 111>;
1400                                 clock-names = "core", "iface";
1401                                 wp-inverted;
1402                                 non-removable;
1403                                 status = "disabled";
1404                                 bus-width = <8>;
1405                         };
1406
1407                         sd1: sdhci@16100000 {
1408                                 cell-index = <1>;
1409                                 compatible = "sirf,atlas7-sdhc";
1410                                 reg = <0x16100000 0x100000>;
1411                                 interrupts = <0 38 0>;
1412                                 clocks = <&car 109>, <&car 111>;
1413                                 clock-names = "core", "iface";
1414                                 non-removable;
1415                                 status = "disabled";
1416                                 bus-width = <8>;
1417                         };
1418
1419                         usb0: usb@17060000 {
1420                                 cell-index = <0>;
1421                                 compatible = "sirf,atlas7-usb";
1422                                 reg = <0x17060000 0x200>;
1423                                 interrupts = <0 10 0>;
1424                                 clocks = <&car 113>;
1425                                 sirf,usbphy = <&usbphy0>;
1426                                 phy_type = "utmi";
1427                                 dr_mode = "otg";
1428                                 maximum-speed = "high-speed";
1429                                 status = "okay";
1430                         };
1431
1432                         usb1: usb@17070000 {
1433                                 cell-index = <1>;
1434                                 compatible = "sirf,atlas7-usb";
1435                                 reg = <0x17070000 0x200>;
1436                                 interrupts = <0 11 0>;
1437                                 clocks = <&car 114>;
1438                                 sirf,usbphy = <&usbphy1>;
1439                                 phy_type = "utmi";
1440                                 dr_mode = "host";
1441                                 maximum-speed = "high-speed";
1442                                 status = "okay";
1443                         };
1444
1445                         usbphy0: usbphy@0 {
1446                                 compatible = "sirf,atlas7-usbphy";
1447                                 reg = <0x17060200 0x100>;
1448                                 clocks = <&car 115>;
1449                                 status = "okay";
1450                         };
1451
1452                         usbphy1: usbphy@1 {
1453                                 compatible = "sirf,atlas7-usbphy";
1454                                 reg = <0x17070200 0x100>;
1455                                 clocks = <&car 116>;
1456                                 status = "okay";
1457                         };
1458
1459                         i2c0: i2c@17020000 {
1460                                 cell-index = <0>;
1461                                 compatible = "sirf,prima2-i2c";
1462                                 reg = <0x17020000 0x1000>;
1463                                 interrupts = <0 24 0>;
1464                                 clocks = <&car 105>;
1465                                 #address-cells = <1>;
1466                                 #size-cells = <0>;
1467                         };
1468
1469                 };
1470
1471                 vdifm {
1472                         compatible = "arteris, flexnoc", "simple-bus";
1473                         #address-cells = <1>;
1474                         #size-cells = <1>;
1475                         ranges = <0x13290000 0x13290000 0x3000>,
1476                                 <0x13300000 0x13300000 0x1000>,
1477                                 <0x14200000 0x14200000 0x600000>;
1478
1479                         vdifm@13290000 {
1480                                 compatible = "sirf,nocfw-vdifm";
1481                                 reg = <0x13290000 0x3000>;
1482                         };
1483
1484                         gpio_1: gpio_vdifm@13300000 {
1485                                 #gpio-cells = <2>;
1486                                 #interrupt-cells = <2>;
1487                                 compatible = "sirf,atlas7-gpio";
1488                                 reg = <0x13300000 0x1000>;
1489                                 interrupts = <0 43 0>, <0 44 0>,
1490                                                 <0 45 0>, <0 46 0>;
1491                                 clocks = <&car 84>;
1492                                 clock-names = "gpio1_io";
1493                                 gpio-controller;
1494                                 interrupt-controller;
1495
1496                                 gpio-banks = <4>;
1497                                 gpio-ranges = <&pinctrl 0 0 0>,
1498                                                 <&pinctrl 32 0 0>,
1499                                                 <&pinctrl 64 0 0>,
1500                                                 <&pinctrl 96 0 0>;
1501                                 gpio-ranges-group-names = "gnss_gpio_grp",
1502                                                         "lcd_vip_gpio_grp",
1503                                                         "sdio_i2s_gpio_grp",
1504                                                         "sp_rgmii_gpio_grp";
1505                         };
1506
1507                         sd2: sdhci@14200000 {
1508                                 cell-index = <2>;
1509                                 compatible = "sirf,atlas7-sdhc";
1510                                 reg = <0x14200000 0x100000>;
1511                                 interrupts = <0 23 0>;
1512                                 clocks = <&car 70>, <&car 75>;
1513                                 clock-names = "core", "iface";
1514                                 status = "disabled";
1515                                 bus-width = <4>;
1516                                 sd-uhs-sdr50;
1517                                 vqmmc-supply = <&vqmmc>;
1518                                 vqmmc: vqmmc@2 {
1519                                         regulator-min-microvolt = <1650000>;
1520                                         regulator-max-microvolt = <1950000>;
1521                                         regulator-name = "vqmmc-ldo";
1522                                         regulator-type = "voltage";
1523                                         regulator-boot-on;
1524                                         regulator-allow-bypass;
1525                                 };
1526                         };
1527
1528                         sd3: sdhci@14300000 {
1529                                 cell-index = <3>;
1530                                 compatible = "sirf,atlas7-sdhc";
1531                                 reg = <0x14300000 0x100000>;
1532                                 interrupts = <0 23 0>;
1533                                 clocks = <&car 76>, <&car 81>;
1534                                 clock-names = "core", "iface";
1535                                 status = "disabled";
1536                                 bus-width = <4>;
1537                         };
1538
1539                         sd5: sdhci@14500000 {
1540                                 cell-index = <5>;
1541                                 compatible = "sirf,atlas7-sdhc";
1542                                 reg = <0x14500000 0x100000>;
1543                                 interrupts = <0 39 0>;
1544                                 clocks = <&car 71>, <&car 76>;
1545                                 clock-names = "core", "iface";
1546                                 status = "disabled";
1547                                 bus-width = <4>;
1548                                 loop-dma;
1549                         };
1550
1551                         sd6: sdhci@14600000 {
1552                                 cell-index = <6>;
1553                                 compatible = "sirf,atlas7-sdhc";
1554                                 reg = <0x14600000 0x100000>;
1555                                 interrupts = <0 98 0>;
1556                                 clocks = <&car 72>, <&car 77>;
1557                                 clock-names = "core", "iface";
1558                                 status = "disabled";
1559                                 bus-width = <4>;
1560                         };
1561
1562                         sd7: sdhci@14700000 {
1563                                 cell-index = <7>;
1564                                 compatible = "sirf,atlas7-sdhc";
1565                                 reg = <0x14700000 0x100000>;
1566                                 interrupts = <0 98 0>;
1567                                 clocks = <&car 72>, <&car 77>;
1568                                 clock-names = "core", "iface";
1569                                 status = "disabled";
1570                                 bus-width = <4>;
1571                         };
1572                 };
1573
1574                 audiom {
1575                         compatible = "arteris, flexnoc", "simple-bus";
1576                         #address-cells = <1>;
1577                         #size-cells = <1>;
1578                         ranges = <0x10d50000 0x10d50000 0x0000ffff>,
1579                                         <0x10d60000 0x10d60000 0x0000ffff>,
1580                                         <0x10d80000 0x10d80000 0x0000ffff>,
1581                                         <0x10d90000 0x10d90000 0x0000ffff>,
1582                                         <0x10ED0000 0x10ED0000 0x3000>,
1583                                         <0x10dc8000 0x10dc8000 0x1000>,
1584                                         <0x10dc0000 0x10dc0000 0x1000>,
1585                                         <0x10db0000 0x10db0000 0x4000>,
1586                                         <0x10d40000 0x10d40000 0x1000>,
1587                                         <0x10d30000 0x10d30000 0x1000>;
1588
1589                         timer@10dc0000 {
1590                                 compatible = "sirf,atlas7-tick";
1591                                 reg = <0x10dc0000 0x1000>;
1592                                 interrupts = <0 0 0>,
1593                                            <0 1 0>,
1594                                            <0 2 0>,
1595                                            <0 49 0>,
1596                                            <0 50 0>,
1597                                            <0 51 0>;
1598                                 clocks = <&car 47>;
1599                         };
1600
1601                         timerb@10dc8000 {
1602                                         compatible = "sirf,atlas7-tick";
1603                                         reg = <0x10dc8000 0x1000>;
1604                                         interrupts = <0 74 0>,
1605                                                            <0 75 0>,
1606                                                            <0 76 0>,
1607                                                            <0 77 0>,
1608                                                            <0 78 0>,
1609                                                            <0 79 0>;
1610                                         clocks = <&car 47>;
1611                         };
1612
1613                         vip0@10db0000 {
1614                                 compatible = "sirf,atlas7-vip0";
1615                                 reg = <0x10db0000 0x2000>;
1616                                 interrupts = <0 85 0>;
1617                                 sirf,vip_cma_size = <0xC00000>;
1618                         };
1619
1620                         cvd@10db2000 {
1621                                 compatible = "sirf,cvd";
1622                                 reg = <0x10db2000 0x2000>;
1623                                 clocks = <&car 46>;
1624                         };
1625
1626                         dmac2: dma-controller@10d50000 {
1627                                 cell-index = <2>;
1628                                 compatible = "sirf,atlas7-dmac";
1629                                 reg = <0x10d50000 0xffff>;
1630                                 interrupts = <0 55 0>;
1631                                 clocks = <&car 60>;
1632                                 dma-channels = <16>;
1633                                 #dma-cells = <1>;
1634                         };
1635
1636                         dmac3: dma-controller@10d60000 {
1637                                 cell-index = <3>;
1638                                 compatible = "sirf,atlas7-dmac";
1639                                 reg = <0x10d60000 0xffff>;
1640                                 interrupts = <0 56 0>;
1641                                 clocks = <&car 61>;
1642                                 dma-channels = <16>;
1643                                 #dma-cells = <1>;
1644                         };
1645
1646                         adc: adc@10d80000 {
1647                                 compatible = "sirf,atlas7-adc";
1648                                 reg = <0x10d80000 0xffff>;
1649                                 interrupts = <0 34 0>;
1650                                 clocks = <&car 49>;
1651                                 #io-channel-cells = <1>;
1652                         };
1653
1654                         pulsec@10d90000 {
1655                                 compatible = "sirf,prima2-pulsec";
1656                                 reg = <0x10d90000 0xffff>;
1657                                 interrupts = <0 42 0>;
1658                                 clocks = <&car 54>;
1659                         };
1660
1661                         audiom@10ED0000 {
1662                                 compatible = "sirf,nocfw-audiom";
1663                                 reg = <0x10ED0000 0x3000>;
1664                                 interrupts = <0 102 0>;
1665                         };
1666
1667                         usp1: usp@10d30000 {
1668                                 cell-index = <1>;
1669                                 reg = <0x10d30000 0x1000>;
1670                                 fifosize = <512>;
1671                                 clocks = <&car 58>;
1672                                 dmas = <&dmac2 6>, <&dmac2 7>;
1673                                 dma-names = "rx", "tx";
1674                         };
1675
1676                         usp2: usp@10d40000 {
1677                                 cell-index = <2>;
1678                                 reg = <0x10d40000 0x1000>;
1679                                 interrupts = <0 22 0>;
1680                                 clocks = <&car 59>;
1681                                 dmas = <&dmac2 12>, <&dmac2 13>;
1682                                 dma-names = "rx", "tx";
1683                                 #address-cells = <1>;
1684                                 #size-cells = <0>;
1685                                 status = "disabled";
1686                         };
1687                 };
1688
1689                 ddrm {
1690                         compatible = "arteris, flexnoc", "simple-bus";
1691                         #address-cells = <1>;
1692                         #size-cells = <1>;
1693                         ranges = <0x10820000 0x10820000 0x3000>,
1694                                         <0x10800000 0x10800000 0x2000>;
1695                         ddrm@10820000 {
1696                                 compatible = "sirf,nocfw-ddrm";
1697                                 reg = <0x10820000 0x3000>;
1698                                 interrupts = <0 105 0>;
1699                         };
1700
1701                         memory-controller@0x10800000 {
1702                                 compatible = "sirf,atlas7-memc";
1703                                 reg = <0x10800000 0x2000>;
1704                         };
1705
1706                 };
1707
1708                 btm {
1709                         compatible = "arteris, flexnoc", "simple-bus";
1710                         #address-cells = <1>;
1711                         #size-cells = <1>;
1712                         ranges = <0x11002000 0x11002000 0x0000ffff>,
1713                                <0x11010000 0x11010000 0x3000>,
1714                                <0x11000000 0x11000000 0x1000>,
1715                                <0x11001000 0x11001000 0x1000>;
1716
1717                         dmac4: dma-controller@11002000 {
1718                                 cell-index = <4>;
1719                                 compatible = "sirf,atlas7-dmac";
1720                                 reg = <0x11002000 0x1000>;
1721                                 interrupts = <0 99 0>;
1722                                 clocks = <&car 130>;
1723                                 dma-channels = <16>;
1724                                 #dma-cells = <1>;
1725                         };
1726                         uart6: uart@11000000 {
1727                                 cell-index = <6>;
1728                                 compatible = "sirf,atlas7-bt-uart",
1729                                                 "sirf,atlas7-uart";
1730                                 reg = <0x11000000 0x1000>;
1731                                 interrupts = <0 100 0>;
1732                                 clocks = <&car 131>, <&car 133>, <&car 134>;
1733                                 clock-names = "uart", "general", "noc";
1734                                 fifosize = <128>;
1735                                 dmas = <&dmac4 12>, <&dmac4 13>;
1736                                 dma-names = "rx", "tx";
1737                                 status = "disabled";
1738                         };
1739
1740                         usp3: usp@11001000 {
1741                                 compatible = "sirf,atlas7-bt-usp",
1742                                            "sirf,prima2-usp-pcm";
1743                                 cell-index = <3>;
1744                                 reg = <0x11001000 0x1000>;
1745                                 fifosize = <512>;
1746                                 clocks = <&car 132>, <&car 129>, <&car 133>,
1747                                         <&car 134>, <&car 135>;
1748                                 clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
1749                                         "noc_btm_io", "thbtm_io";
1750                                 dmas = <&dmac4 0>, <&dmac4 1>;
1751                                 dma-names = "rx", "tx";
1752                         };
1753
1754                         btm@11010000 {
1755                                 compatible = "sirf,nocfw-btm";
1756                                 reg = <0x11010000 0x3000>;
1757                         };
1758                 };
1759
1760                 rtcm {
1761                         compatible = "arteris, flexnoc", "simple-bus";
1762                         #address-cells = <1>;
1763                         #size-cells = <1>;
1764                         ranges = <0x18810000 0x18810000 0x3000>,
1765                                 <0x18840000 0x18840000 0x1000>,
1766                                 <0x18890000 0x18890000 0x1000>,
1767                                 <0x188B0000 0x188B0000 0x10000>,
1768                                 <0x188D0000 0x188D0000 0x1000>;
1769                         rtcm@18810000 {
1770                                 compatible = "sirf,nocfw-rtcm";
1771                                 reg = <0x18810000 0x3000>;
1772                                 interrupts = <0 109 0>;
1773                         };
1774
1775                         gpio_2: gpio_rtcm@18890000 {
1776                                 #gpio-cells = <2>;
1777                                 #interrupt-cells = <2>;
1778                                 compatible = "sirf,atlas7-gpio";
1779                                 reg = <0x18890000 0x1000>;
1780                                 interrupts = <0 47 0>;
1781                                 gpio-controller;
1782                                 interrupt-controller;
1783
1784                                 gpio-banks = <1>;
1785                                 gpio-ranges = <&pinctrl 0 0 0>;
1786                                 gpio-ranges-group-names = "rtc_gpio_grp";
1787                         };
1788
1789                         rtc-iobg@18840000 {
1790                                 compatible = "sirf,prima2-rtciobg",
1791                                         "sirf-prima2-rtciobg-bus",
1792                                         "simple-bus";
1793                                 #address-cells = <1>;
1794                                 #size-cells = <1>;
1795                                 reg = <0x18840000 0x1000>;
1796
1797                                 sysrtc@2000 {
1798                                         compatible = "sirf,prima2-sysrtc";
1799                                         reg = <0x2000 0x100>;
1800                                         interrupts = <0 52 0>;
1801                                 };
1802                                 pwrc@3000 {
1803                                         compatible = "sirf,atlas7-pwrc";
1804                                         reg = <0x3000 0x100>;
1805                                 };
1806                         };
1807
1808                         qspi: flash@188B0000 {
1809                                 cell-index = <0>;
1810                                 compatible = "sirf,atlas7-qspi-nor";
1811                                 reg = <0x188B0000 0x10000>;
1812                                 interrupts = <0 15 0>;
1813                                 #address-cells = <1>;
1814                                 #size-cells = <0>;
1815                         };
1816
1817                         retain@0x188D0000 {
1818                                 compatible = "sirf,atlas7-retain";
1819                                 reg = <0x188D0000 0x1000>;
1820                         };
1821
1822                 };
1823                 disp-iobg {
1824                         /* lcdc0 */
1825                         compatible = "simple-bus";
1826                         #address-cells = <1>;
1827                         #size-cells = <1>;
1828                         ranges = <0x13100000 0x13100000 0x20000>,
1829                                  <0x10e10000 0x10e10000 0x10000>;
1830
1831                         lcd@13100000 {
1832                                 compatible = "sirf,atlas7-lcdc";
1833                                 reg = <0x13100000 0x10000>;
1834                                 interrupts = <0 30 0>;
1835                                 clocks = <&car 79>;
1836                         };
1837                         vpp@13110000 {
1838                                 compatible = "sirf,atlas7-vpp";
1839                                 reg = <0x13110000 0x10000>;
1840                                 interrupts = <0 31 0>;
1841                                 clocks = <&car 78>;
1842                                 resets = <&car 29>;
1843                         };
1844                         lvds@10e10000 {
1845                                 compatible = "sirf,atlas7-lvdsc";
1846                                 reg = <0x10e10000 0x10000>;
1847                                 interrupts = <0 64 0>;
1848                                 clocks = <&car 54>;
1849                                 resets = <&car 29>;
1850                         };
1851
1852                 };
1853
1854                 graphics-iobg {
1855                         compatible = "simple-bus";
1856                         #address-cells = <1>;
1857                         #size-cells = <1>;
1858                         ranges = <0x12000000 0x12000000 0x1000000>;
1859
1860                         graphics@12000000 {
1861                                 compatible = "powervr,sgx531";
1862                                 reg = <0x12000000 0x1000000>;
1863                                 interrupts = <0 6 0>;
1864                                 clocks = <&car 126>;
1865                         };
1866                 };
1867         };
1868 };