arch/arm/boot/dts/armada-xp-mv78260.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  *
  12  * Contains definitions specific to the Armada XP MV78260 SoC that are not
  13  * common to all Armada XP SoCs.
  14  */
  15
  16 #include "armada-xp.dtsi"
  17
  18 / {
  19         model = "Marvell Armada XP MV78260 SoC";
  20         compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
  21
  22         aliases {
  23                 gpio0 = &gpio0;
  24                 gpio1 = &gpio1;
  25                 gpio2 = &gpio2;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "marvell,sheeva-v7";
  35                         reg = <0>;
  36                         clocks = <&cpuclk 0>;
  37                 };
  38
  39                 cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "marvell,sheeva-v7";
  42                         reg = <1>;
  43                         clocks = <&cpuclk 1>;
  44                 };
  45         };
  46
  47         soc {
  48                 /*
  49                  * MV78260 has 3 PCIe units Gen2.0: Two units can be
  50                  * configured as x4 or quad x1 lanes. One unit is
  51                  * x4/x1.
  52                  */
  53                 pcie-controller {
  54                         compatible = "marvell,armada-xp-pcie";
  55                         status = "disabled";
  56                         device_type = "pci";
  57
  58                         #address-cells = <3>;
  59                         #size-cells = <2>;
  60
  61                         msi-parent = <&mpic>;
  62                         bus-range = <0x00 0xff>;
  63
  64                         ranges =
  65                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
  66                                 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
  67                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
  68                                 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
  69                                 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
  70                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
  71                                 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
  72                                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
  73                                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
  74                                 0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
  75                                 0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
  76                                 0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
  77                                 0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
  78                                 0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
  79                                 0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
  80                                 0x82000000 0x9 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
  81                                 0x81000000 0x9 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
  82                                 0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
  83                                 0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
  84
  85                         pcie@1,0 {
  86                                 device_type = "pci";
  87                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  88                                 reg = <0x0800 0 0 0 0>;
  89                                 #address-cells = <3>;
  90                                 #size-cells = <2>;
  91                                 #interrupt-cells = <1>;
  92                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
  93                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
  94                                 interrupt-map-mask = <0 0 0 0>;
  95                                 interrupt-map = <0 0 0 0 &mpic 58>;
  96                                 marvell,pcie-port = <0>;
  97                                 marvell,pcie-lane = <0>;
  98                                 clocks = <&gateclk 5>;
  99                                 status = "disabled";
 100                         };
 101
 102                         pcie@2,0 {
 103                                 device_type = "pci";
 104                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 105                                 reg = <0x1000 0 0 0 0>;
 106                                 #address-cells = <3>;
 107                                 #size-cells = <2>;
 108                                 #interrupt-cells = <1>;
 109                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 110                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 111                                 interrupt-map-mask = <0 0 0 0>;
 112                                 interrupt-map = <0 0 0 0 &mpic 59>;
 113                                 marvell,pcie-port = <0>;
 114                                 marvell,pcie-lane = <1>;
 115                                 clocks = <&gateclk 6>;
 116                                 status = "disabled";
 117                         };
 118
 119                         pcie@3,0 {
 120                                 device_type = "pci";
 121                                 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
 122                                 reg = <0x1800 0 0 0 0>;
 123                                 #address-cells = <3>;
 124                                 #size-cells = <2>;
 125                                 #interrupt-cells = <1>;
 126                                 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 127                                           0x81000000 0 0 0x81000000 0x3 0 1 0>;
 128                                 interrupt-map-mask = <0 0 0 0>;
 129                                 interrupt-map = <0 0 0 0 &mpic 60>;
 130                                 marvell,pcie-port = <0>;
 131                                 marvell,pcie-lane = <2>;
 132                                 clocks = <&gateclk 7>;
 133                                 status = "disabled";
 134                         };
 135
 136                         pcie@4,0 {
 137                                 device_type = "pci";
 138                                 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
 139                                 reg = <0x2000 0 0 0 0>;
 140                                 #address-cells = <3>;
 141                                 #size-cells = <2>;
 142                                 #interrupt-cells = <1>;
 143                                 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 144                                           0x81000000 0 0 0x81000000 0x4 0 1 0>;
 145                                 interrupt-map-mask = <0 0 0 0>;
 146                                 interrupt-map = <0 0 0 0 &mpic 61>;
 147                                 marvell,pcie-port = <0>;
 148                                 marvell,pcie-lane = <3>;
 149                                 clocks = <&gateclk 8>;
 150                                 status = "disabled";
 151                         };
 152
 153                         pcie@9,0 {
 154                                 device_type = "pci";
 155                                 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
 156                                 reg = <0x4800 0 0 0 0>;
 157                                 #address-cells = <3>;
 158                                 #size-cells = <2>;
 159                                 #interrupt-cells = <1>;
 160                                 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 161                                           0x81000000 0 0 0x81000000 0x9 0 1 0>;
 162                                 interrupt-map-mask = <0 0 0 0>;
 163                                 interrupt-map = <0 0 0 0 &mpic 99>;
 164                                 marvell,pcie-port = <2>;
 165                                 marvell,pcie-lane = <0>;
 166                                 clocks = <&gateclk 26>;
 167                                 status = "disabled";
 168                         };
 169
 170                         pcie@10,0 {
 171                                 device_type = "pci";
 172                                 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
 173                                 reg = <0x5000 0 0 0 0>;
 174                                 #address-cells = <3>;
 175                                 #size-cells = <2>;
 176                                 #interrupt-cells = <1>;
 177                                 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
 178                                           0x81000000 0 0 0x81000000 0xa 0 1 0>;
 179                                 interrupt-map-mask = <0 0 0 0>;
 180                                 interrupt-map = <0 0 0 0 &mpic 103>;
 181                                 marvell,pcie-port = <3>;
 182                                 marvell,pcie-lane = <0>;
 183                                 clocks = <&gateclk 27>;
 184                                 status = "disabled";
 185                         };
 186                 };
 187
 188                 internal-regs {
 189                         pinctrl {
 190                                 compatible = "marvell,mv78260-pinctrl";
 191                                 reg = <0x18000 0x38>;
 192
 193                                 sdio_pins: sdio-pins {
 194                                         marvell,pins = "mpp30", "mpp31", "mpp32",
 195                                                        "mpp33", "mpp34", "mpp35";
 196                                         marvell,function = "sd0";
 197                                 };
 198                         };
 199
 200                         gpio0: gpio@18100 {
 201                                 compatible = "marvell,orion-gpio";
 202                                 reg = <0x18100 0x40>;
 203                                 ngpios = <32>;
 204                                 gpio-controller;
 205                                 #gpio-cells = <2>;
 206                                 interrupt-controller;
 207                                 #interrupt-cells = <2>;
 208                                 interrupts = <82>, <83>, <84>, <85>;
 209                         };
 210
 211                         gpio1: gpio@18140 {
 212                                 compatible = "marvell,orion-gpio";
 213                                 reg = <0x18140 0x40>;
 214                                 ngpios = <32>;
 215                                 gpio-controller;
 216                                 #gpio-cells = <2>;
 217                                 interrupt-controller;
 218                                 #interrupt-cells = <2>;
 219                                 interrupts = <87>, <88>, <89>, <90>;
 220                         };
 221
 222                         gpio2: gpio@18180 {
 223                                 compatible = "marvell,orion-gpio";
 224                                 reg = <0x18180 0x40>;
 225                                 ngpios = <3>;
 226                                 gpio-controller;
 227                                 #gpio-cells = <2>;
 228                                 interrupt-controller;
 229                                 #interrupt-cells = <2>;
 230                                 interrupts = <91>;
 231                         };
 232
 233                         ethernet@34000 {
 234                                 compatible = "marvell,armada-370-neta";
 235                                 reg = <0x34000 0x4000>;
 236                                 interrupts = <14>;
 237                                 clocks = <&gateclk 1>;
 238                                 status = "disabled";
 239                         };
 240                 };
 241         };
 242 };