arch/arm/boot/dts/armada-375.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 375 family SoC
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of the
  17  *     License, or (at your option) any later version.
  18  *
  19  *     This file is distributed in the hope that it will be useful
  20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *     GNU General Public License for more details.
  23  *
  24  * Or, alternatively
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton.dtsi"
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/phy/phy.h>
  52
  53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  54
  55 / {
  56         model = "Marvell Armada 375 family SoC";
  57         compatible = "marvell,armada375";
  58
  59         aliases {
  60                 gpio0 = &gpio0;
  61                 gpio1 = &gpio1;
  62                 gpio2 = &gpio2;
  63                 serial0 = &uart0;
  64                 serial1 = &uart1;
  65         };
  66
  67         clocks {
  68                 /* 2 GHz fixed main PLL */
  69                 mainpll: mainpll {
  70                         compatible = "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <1000000000>;
  73                 };
  74                 /* 25 MHz reference crystal */
  75                 refclk: oscillator {
  76                         compatible = "fixed-clock";
  77                         #clock-cells = <0>;
  78                         clock-frequency = <25000000>;
  79                 };
  80         };
  81
  82         cpus {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85                 enable-method = "marvell,armada-375-smp";
  86
  87                 cpu@0 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a9";
  90                         reg = <0>;
  91                 };
  92                 cpu@1 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a9";
  95                         reg = <1>;
  96                 };
  97         };
  98
  99         pmu {
 100                 compatible = "arm,cortex-a9-pmu";
 101                 interrupts-extended = <&mpic 3>;
 102         };
 103
 104         soc {
 105                 compatible = "marvell,armada375-mbus", "simple-bus";
 106                 #address-cells = <2>;
 107                 #size-cells = <1>;
 108                 controller = <&mbusc>;
 109                 interrupt-parent = <&gic>;
 110                 pcie-mem-aperture = <0xe0000000 0x8000000>;
 111                 pcie-io-aperture  = <0xe8000000 0x100000>;
 112
 113                 bootrom {
 114                         compatible = "marvell,bootrom";
 115                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
 116                 };
 117
 118                 devbus-bootcs {
 119                         compatible = "marvell,mvebu-devbus";
 120                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
 121                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         clocks = <&coreclk 0>;
 125                         status = "disabled";
 126                 };
 127
 128                 devbus-cs0 {
 129                         compatible = "marvell,mvebu-devbus";
 130                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
 131                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
 132                         #address-cells = <1>;
 133                         #size-cells = <1>;
 134                         clocks = <&coreclk 0>;
 135                         status = "disabled";
 136                 };
 137
 138                 devbus-cs1 {
 139                         compatible = "marvell,mvebu-devbus";
 140                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
 141                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144                         clocks = <&coreclk 0>;
 145                         status = "disabled";
 146                 };
 147
 148                 devbus-cs2 {
 149                         compatible = "marvell,mvebu-devbus";
 150                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
 151                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         clocks = <&coreclk 0>;
 155                         status = "disabled";
 156                 };
 157
 158                 devbus-cs3 {
 159                         compatible = "marvell,mvebu-devbus";
 160                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
 161                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
 162                         #address-cells = <1>;
 163                         #size-cells = <1>;
 164                         clocks = <&coreclk 0>;
 165                         status = "disabled";
 166                 };
 167
 168                 internal-regs {
 169                         compatible = "simple-bus";
 170                         #address-cells = <1>;
 171                         #size-cells = <1>;
 172                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 173
 174                         L2: cache-controller@8000 {
 175                                 compatible = "arm,pl310-cache";
 176                                 reg = <0x8000 0x1000>;
 177                                 cache-unified;
 178                                 cache-level = <2>;
 179                         };
 180
 181                         scu@c000 {
 182                                 compatible = "arm,cortex-a9-scu";
 183                                 reg = <0xc000 0x58>;
 184                         };
 185
 186                         timer@c600 {
 187                                 compatible = "arm,cortex-a9-twd-timer";
 188                                 reg = <0xc600 0x20>;
 189                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 190                                 clocks = <&coreclk 2>;
 191                         };
 192
 193                         gic: interrupt-controller@d000 {
 194                                 compatible = "arm,cortex-a9-gic";
 195                                 #interrupt-cells = <3>;
 196                                 #size-cells = <0>;
 197                                 interrupt-controller;
 198                                 reg = <0xd000 0x1000>,
 199                                       <0xc100 0x100>;
 200                         };
 201
 202                         mdio {
 203                                 #address-cells = <1>;
 204                                 #size-cells = <0>;
 205                                 compatible = "marvell,orion-mdio";
 206                                 reg = <0xc0054 0x4>;
 207                                 clocks = <&gateclk 19>;
 208                         };
 209
 210                         /* Network controller */
 211                         ethernet@f0000 {
 212                                 compatible = "marvell,armada-375-pp2";
 213                                 reg = <0xf0000 0xa000>, /* Packet Processor regs */
 214                                       <0xc0000 0x3060>, /* LMS regs */
 215                                       <0xc4000 0x100>,  /* eth0 regs */
 216                                       <0xc5000 0x100>;  /* eth1 regs */
 217                                 clocks = <&gateclk 3>, <&gateclk 19>;
 218                                 clock-names = "pp_clk", "gop_clk";
 219                                 status = "disabled";
 220
 221                                 eth0: eth0@c4000 {
 222                                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 223                                         port-id = <0>;
 224                                         status = "disabled";
 225                                 };
 226
 227                                 eth1: eth1@c5000 {
 228                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 229                                         port-id = <1>;
 230                                         status = "disabled";
 231                                 };
 232                         };
 233
 234                         rtc@10300 {
 235                                 compatible = "marvell,orion-rtc";
 236                                 reg = <0x10300 0x20>;
 237                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 238                         };
 239
 240                         spi0: spi@10600 {
 241                                 compatible = "marvell,armada-375-spi",
 242                                                 "marvell,orion-spi";
 243                                 reg = <0x10600 0x50>;
 244                                 #address-cells = <1>;
 245                                 #size-cells = <0>;
 246                                 cell-index = <0>;
 247                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 248                                 clocks = <&coreclk 0>;
 249                                 status = "disabled";
 250                         };
 251
 252                         spi1: spi@10680 {
 253                                 compatible = "marvell,armada-375-spi",
 254                                                 "marvell,orion-spi";
 255                                 reg = <0x10680 0x50>;
 256                                 #address-cells = <1>;
 257                                 #size-cells = <0>;
 258                                 cell-index = <1>;
 259                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 260                                 clocks = <&coreclk 0>;
 261                                 status = "disabled";
 262                         };
 263
 264                         i2c0: i2c@11000 {
 265                                 compatible = "marvell,mv64xxx-i2c";
 266                                 reg = <0x11000 0x20>;
 267                                 #address-cells = <1>;
 268                                 #size-cells = <0>;
 269                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 270                                 timeout-ms = <1000>;
 271                                 clocks = <&coreclk 0>;
 272                                 status = "disabled";
 273                         };
 274
 275                         i2c1: i2c@11100 {
 276                                 compatible = "marvell,mv64xxx-i2c";
 277                                 reg = <0x11100 0x20>;
 278                                 #address-cells = <1>;
 279                                 #size-cells = <0>;
 280                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 281                                 timeout-ms = <1000>;
 282                                 clocks = <&coreclk 0>;
 283                                 status = "disabled";
 284                         };
 285
 286                         uart0: serial@12000 {
 287                                 compatible = "snps,dw-apb-uart";
 288                                 reg = <0x12000 0x100>;
 289                                 reg-shift = <2>;
 290                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 291                                 reg-io-width = <1>;
 292                                 clocks = <&coreclk 0>;
 293                                 status = "disabled";
 294                         };
 295
 296                         uart1: serial@12100 {
 297                                 compatible = "snps,dw-apb-uart";
 298                                 reg = <0x12100 0x100>;
 299                                 reg-shift = <2>;
 300                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 301                                 reg-io-width = <1>;
 302                                 clocks = <&coreclk 0>;
 303                                 status = "disabled";
 304                         };
 305
 306                         pinctrl {
 307                                 compatible = "marvell,mv88f6720-pinctrl";
 308                                 reg = <0x18000 0x24>;
 309
 310                                 i2c0_pins: i2c0-pins {
 311                                         marvell,pins = "mpp14",  "mpp15";
 312                                         marvell,function = "i2c0";
 313                                 };
 314
 315                                 i2c1_pins: i2c1-pins {
 316                                         marvell,pins = "mpp61",  "mpp62";
 317                                         marvell,function = "i2c1";
 318                                 };
 319
 320                                 nand_pins: nand-pins {
 321                                         marvell,pins = "mpp0", "mpp1", "mpp2",
 322                                                 "mpp3", "mpp4", "mpp5",
 323                                                 "mpp6", "mpp7", "mpp8",
 324                                                 "mpp9", "mpp10", "mpp11",
 325                                                 "mpp12", "mpp13";
 326                                         marvell,function = "nand";
 327                                 };
 328
 329                                 sdio_pins: sdio-pins {
 330                                         marvell,pins = "mpp24",  "mpp25", "mpp26",
 331                                                      "mpp27", "mpp28", "mpp29";
 332                                         marvell,function = "sd";
 333                                 };
 334
 335                                 spi0_pins: spi0-pins {
 336                                         marvell,pins = "mpp0",  "mpp1", "mpp4",
 337                                                      "mpp5", "mpp8", "mpp9";
 338                                         marvell,function = "spi0";
 339                                 };
 340                         };
 341
 342                         gpio0: gpio@18100 {
 343                                 compatible = "marvell,orion-gpio";
 344                                 reg = <0x18100 0x40>;
 345                                 ngpios = <32>;
 346                                 gpio-controller;
 347                                 #gpio-cells = <2>;
 348                                 interrupt-controller;
 349                                 #interrupt-cells = <2>;
 350                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 351                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 352                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 353                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 354                         };
 355
 356                         gpio1: gpio@18140 {
 357                                 compatible = "marvell,orion-gpio";
 358                                 reg = <0x18140 0x40>;
 359                                 ngpios = <32>;
 360                                 gpio-controller;
 361                                 #gpio-cells = <2>;
 362                                 interrupt-controller;
 363                                 #interrupt-cells = <2>;
 364                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 365                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 366                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 367                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 368                         };
 369
 370                         gpio2: gpio@18180 {
 371                                 compatible = "marvell,orion-gpio";
 372                                 reg = <0x18180 0x40>;
 373                                 ngpios = <3>;
 374                                 gpio-controller;
 375                                 #gpio-cells = <2>;
 376                                 interrupt-controller;
 377                                 #interrupt-cells = <2>;
 378                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 379                         };
 380
 381                         system-controller@18200 {
 382                                 compatible = "marvell,armada-375-system-controller";
 383                                 reg = <0x18200 0x100>;
 384                         };
 385
 386                         gateclk: clock-gating-control@18220 {
 387                                 compatible = "marvell,armada-375-gating-clock";
 388                                 reg = <0x18220 0x4>;
 389                                 clocks = <&coreclk 0>;
 390                                 #clock-cells = <1>;
 391                         };
 392
 393                         usbcluster: usb-cluster@18400 {
 394                                 compatible = "marvell,armada-375-usb-cluster";
 395                                 reg = <0x18400 0x4>;
 396                                 #phy-cells = <1>;
 397                         };
 398
 399                         mbusc: mbus-controller@20000 {
 400                                 compatible = "marvell,mbus-controller";
 401                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 402                         };
 403
 404                         mpic: interrupt-controller@20a00 {
 405                                 compatible = "marvell,mpic";
 406                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 407                                 #interrupt-cells = <1>;
 408                                 #size-cells = <1>;
 409                                 interrupt-controller;
 410                                 msi-controller;
 411                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 412                         };
 413
 414                         timer@20300 {
 415                                 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
 416                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 417                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 418                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 419                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 420                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 421                                                       <&mpic 5>,
 422                                                       <&mpic 6>;
 423                                 clocks = <&coreclk 0>, <&refclk>;
 424                                 clock-names = "nbclk", "fixed";
 425                         };
 426
 427                         watchdog@20300 {
 428                                 compatible = "marvell,armada-375-wdt";
 429                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
 430                                 clocks = <&coreclk 0>, <&refclk>;
 431                                 clock-names = "nbclk", "fixed";
 432                         };
 433
 434                         cpurst@20800 {
 435                                 compatible = "marvell,armada-370-cpu-reset";
 436                                 reg = <0x20800 0x10>;
 437                         };
 438
 439                         coherency-fabric@21010 {
 440                                 compatible = "marvell,armada-375-coherency-fabric";
 441                                 reg = <0x21010 0x1c>;
 442                         };
 443
 444                         usb@50000 {
 445                                 compatible = "marvell,orion-ehci";
 446                                 reg = <0x50000 0x500>;
 447                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 448                                 clocks = <&gateclk 18>;
 449                                 phys = <&usbcluster PHY_TYPE_USB2>;
 450                                 phy-names = "usb";
 451                                 status = "disabled";
 452                         };
 453
 454                         usb@54000 {
 455                                 compatible = "marvell,orion-ehci";
 456                                 reg = <0x54000 0x500>;
 457                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 458                                 clocks = <&gateclk 26>;
 459                                 status = "disabled";
 460                         };
 461
 462                         usb3@58000 {
 463                                 compatible = "marvell,armada-375-xhci";
 464                                 reg = <0x58000 0x20000>,<0x5b880 0x80>;
 465                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 466                                 clocks = <&gateclk 16>;
 467                                 phys = <&usbcluster PHY_TYPE_USB3>;
 468                                 phy-names = "usb";
 469                                 status = "disabled";
 470                         };
 471
 472                         xor@60800 {
 473                                 compatible = "marvell,orion-xor";
 474                                 reg = <0x60800 0x100
 475                                        0x60A00 0x100>;
 476                                 clocks = <&gateclk 22>;
 477                                 status = "okay";
 478
 479                                 xor00 {
 480                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 481                                         dmacap,memcpy;
 482                                         dmacap,xor;
 483                                 };
 484                                 xor01 {
 485                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 486                                         dmacap,memcpy;
 487                                         dmacap,xor;
 488                                         dmacap,memset;
 489                                 };
 490                         };
 491
 492                         xor@60900 {
 493                                 compatible = "marvell,orion-xor";
 494                                 reg = <0x60900 0x100
 495                                        0x60b00 0x100>;
 496                                 clocks = <&gateclk 23>;
 497                                 status = "okay";
 498
 499                                 xor10 {
 500                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 501                                         dmacap,memcpy;
 502                                         dmacap,xor;
 503                                 };
 504                                 xor11 {
 505                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 506                                         dmacap,memcpy;
 507                                         dmacap,xor;
 508                                         dmacap,memset;
 509                                 };
 510                         };
 511
 512                         sata@a0000 {
 513                                 compatible = "marvell,orion-sata";
 514                                 reg = <0xa0000 0x5000>;
 515                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 516                                 clocks = <&gateclk 14>, <&gateclk 20>;
 517                                 clock-names = "0", "1";
 518                                 status = "disabled";
 519                         };
 520
 521                         nand@d0000 {
 522                                 compatible = "marvell,armada370-nand";
 523                                 reg = <0xd0000 0x54>;
 524                                 #address-cells = <1>;
 525                                 #size-cells = <1>;
 526                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 527                                 clocks = <&gateclk 11>;
 528                                 status = "disabled";
 529                         };
 530
 531                         mvsdio@d4000 {
 532                                 compatible = "marvell,orion-sdio";
 533                                 reg = <0xd4000 0x200>;
 534                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 535                                 clocks = <&gateclk 17>;
 536                                 bus-width = <4>;
 537                                 cap-sdio-irq;
 538                                 cap-sd-highspeed;
 539                                 cap-mmc-highspeed;
 540                                 status = "disabled";
 541                         };
 542
 543                         thermal@e8078 {
 544                                 compatible = "marvell,armada375-thermal";
 545                                 reg = <0xe8078 0x4>, <0xe807c 0x8>;
 546                                 status = "okay";
 547                         };
 548
 549                         coreclk: mvebu-sar@e8204 {
 550                                 compatible = "marvell,armada-375-core-clock";
 551                                 reg = <0xe8204 0x04>;
 552                                 #clock-cells = <1>;
 553                         };
 554
 555                         coredivclk: corediv-clock@e8250 {
 556                                 compatible = "marvell,armada-375-corediv-clock";
 557                                 reg = <0xe8250 0xc>;
 558                                 #clock-cells = <1>;
 559                                 clocks = <&mainpll>;
 560                                 clock-output-names = "nand";
 561                         };
 562                 };
 563
 564                 pcie-controller {
 565                         compatible = "marvell,armada-370-pcie";
 566                         status = "disabled";
 567                         device_type = "pci";
 568
 569                         #address-cells = <3>;
 570                         #size-cells = <2>;
 571
 572                         msi-parent = <&mpic>;
 573                         bus-range = <0x00 0xff>;
 574
 575                         ranges =
 576                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 577                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
 578                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
 579                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
 580                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
 581                                 0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
 582
 583                         pcie@1,0 {
 584                                 device_type = "pci";
 585                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 586                                 reg = <0x0800 0 0 0 0>;
 587                                 #address-cells = <3>;
 588                                 #size-cells = <2>;
 589                                 #interrupt-cells = <1>;
 590                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 591                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 592                                 interrupt-map-mask = <0 0 0 0>;
 593                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 594                                 marvell,pcie-port = <0>;
 595                                 marvell,pcie-lane = <0>;
 596                                 clocks = <&gateclk 5>;
 597                                 status = "disabled";
 598                         };
 599
 600                         pcie@2,0 {
 601                                 device_type = "pci";
 602                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 603                                 reg = <0x1000 0 0 0 0>;
 604                                 #address-cells = <3>;
 605                                 #size-cells = <2>;
 606                                 #interrupt-cells = <1>;
 607                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 608                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 609                                 interrupt-map-mask = <0 0 0 0>;
 610                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 611                                 marvell,pcie-port = <0>;
 612                                 marvell,pcie-lane = <1>;
 613                                 clocks = <&gateclk 6>;
 614                                 status = "disabled";
 615                         };
 616
 617                 };
 618         };
 619 };