arch/arm/boot/dts/am335x-phycore-som.dtsi

   1 /*
   2  * Copyright (C) 2015 Phytec Messtechnik GmbH
   3  * Author: Teresa Remmet <t.remmet@phytec.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include "am33xx.dtsi"
  11
  12 / {
  13         model = "Phytec AM335x phyCORE";
  14         compatible = "phytec,am335x-phycore-som", "ti,am33xx";
  15
  16         aliases {
  17                 rtc0 = &i2c_rtc;
  18                 rtc1 = &rtc;
  19         };
  20
  21         cpus {
  22                 cpu@0 {
  23                         cpu0-supply = <&vdd1_reg>;
  24                 };
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 reg = <0x80000000 0x10000000>; /* 256 MB */
  30         };
  31
  32         vbat: fixedregulator@0 {
  33                 compatible = "regulator-fixed";
  34         };
  35 };
  36
  37 /* Crypto Module */
  38 &aes {
  39         status = "okay";
  40 };
  41
  42 &sham {
  43         status = "okay";
  44 };
  45
  46 /* Ethernet */
  47 &am33xx_pinmux {
  48         ethernet0_pins: pinmux_ethernet0 {
  49                 pinctrl-single,pins = <
  50                         0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs_dv */
  51                         0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxerr.rmii1_rxerr */
  52                         0x114 (PIN_OUTPUT | MUX_MODE1)          /* mii1_txen.rmii1_txen */
  53                         0x124 (PIN_OUTPUT | MUX_MODE1)          /* mii1_txd1.rmii1_txd1 */
  54                         0x128 (PIN_OUTPUT | MUX_MODE1)          /* mii1_txd0.rmii1_txd0 */
  55                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd1.rmii1_rxd1 */
  56                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd0.rmii1_rxd0 */
  57                         0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk.rmii1_refclk */
  58                 >;
  59         };
  60
  61         mdio_pins: pinmux_mdio {
  62                 pinctrl-single,pins = <
  63                         /* MDIO */
  64                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
  65                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
  66                 >;
  67         };
  68 };
  69
  70 &cpsw_emac0 {
  71         phy_id = <&davinci_mdio>, <0>;
  72         phy-mode = "rmii";
  73         dual_emac_res_vlan = <1>;
  74 };
  75
  76 &davinci_mdio {
  77         pinctrl-names = "default";
  78         pinctrl-0 = <&mdio_pins>;
  79         status = "okay";
  80 };
  81
  82 &mac {
  83         slaves = <1>;
  84         pinctrl-names = "default";
  85         pinctrl-0 = <&ethernet0_pins>;
  86         status = "okay";
  87 };
  88
  89 &phy_sel {
  90         rmii-clock-ext;
  91 };
  92
  93 /* I2C Busses */
  94 &am33xx_pinmux {
  95         i2c0_pins: pinmux_i2c0 {
  96                 pinctrl-single,pins = <
  97                         0x188 (PIN_INPUT | MUX_MODE0)   /* i2c0_sda.i2c0_sda */
  98                         0x18c (PIN_INPUT | MUX_MODE0)   /* i2c0_scl.i2c0_scl */
  99                 >;
 100         };
 101 };
 102
 103 &i2c0 {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&i2c0_pins>;
 106         clock-frequency = <400000>;
 107         status = "okay";
 108
 109         tps: pmic@2d {
 110                 reg = <0x2d>;
 111         };
 112
 113         i2c_eeprom: eeprom@52 {
 114                 compatible = "atmel,24c32";
 115                 pagesize = <32>;
 116                 reg = <0x52>;
 117                 status = "disabled";
 118         };
 119
 120         i2c_rtc: rtc@68 {
 121                 compatible = "rv4162";
 122                 reg = <0x68>;
 123                 status = "disabled";
 124         };
 125 };
 126
 127 /* NAND memory */
 128 &am33xx_pinmux {
 129                 nandflash_pins: pinmux_nandflash {
 130                         pinctrl-single,pins = <
 131                         0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
 132                         0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
 133                         0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
 134                         0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
 135                         0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
 136                         0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
 137                         0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 138                         0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 139                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 140                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0 */
 141                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 142                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 143                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 144                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 145                 >;
 146         };
 147 };
 148
 149 &elm {
 150         status = "okay";
 151 };
 152
 153 &gpmc {
 154         status = "okay";
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&nandflash_pins>;
 157         ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
 158         nandflash: nand@0,0 {
 159                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 160                 nand-bus-width = <8>;
 161                 ti,nand-ecc-opt = "bch8";
 162                 gpmc,device-nand = "true";
 163                 gpmc,device-width = <1>;
 164                 gpmc,sync-clk-ps = <0>;
 165                 gpmc,cs-on-ns = <0>;
 166                 gpmc,cs-rd-off-ns = <30>;
 167                 gpmc,cs-wr-off-ns = <30>;
 168                 gpmc,adv-on-ns = <0>;
 169                 gpmc,adv-rd-off-ns = <30>;
 170                 gpmc,adv-wr-off-ns = <30>;
 171                 gpmc,we-on-ns = <0>;
 172                 gpmc,we-off-ns = <20>;
 173                 gpmc,oe-on-ns = <10>;
 174                 gpmc,oe-off-ns = <30>;
 175                 gpmc,access-ns = <30>;
 176                 gpmc,rd-cycle-ns = <30>;
 177                 gpmc,wr-cycle-ns = <30>;
 178                 gpmc,wait-on-read = "true";
 179                 gpmc,wait-on-write = "true";
 180                 gpmc,bus-turnaround-ns = <0>;
 181                 gpmc,cycle2cycle-delay-ns = <50>;
 182                 gpmc,cycle2cycle-diffcsen;
 183                 gpmc,clk-activation-ns = <0>;
 184                 gpmc,wait-monitoring-ns = <0>;
 185                 gpmc,wr-access-ns = <30>;
 186                 gpmc,wr-data-mux-bus-ns = <0>;
 187
 188                 elm_id = <&elm>;
 189
 190                 #address-cells = <1>;
 191                 #size-cells = <1>;
 192
 193                 partition@0 {
 194                         label = "xload";
 195                         reg = <0x0 0x20000>;
 196                 };
 197                 partition@1 {
 198                         label = "xload_backup1";
 199                         reg = <0x20000 0x20000>;
 200                 };
 201                 partition@2 {
 202                         label = "xload_backup2";
 203                         reg = <0x40000 0x20000>;
 204                 };
 205                 partition@3 {
 206                         label = "xload_backup3";
 207                         reg = <0x60000 0x20000>;
 208                 };
 209                 partition@4 {
 210                         label = "barebox";
 211                         reg = <0x80000 0x80000>;
 212                 };
 213                 partition@5 {
 214                         label = "bareboxenv";
 215                         reg = <0x100000 0x40000>;
 216                 };
 217                 partition@6 {
 218                         label = "oftree";
 219                         reg = <0x140000 0x40000>;
 220                 };
 221                 partition@7 {
 222                         label = "kernel";
 223                         reg = <0x180000 0x800000>;
 224                 };
 225                 partition@8 {
 226                         label = "root";
 227                         reg = <0x980000 0x0>;
 228                 };
 229         };
 230 };
 231
 232 /* Power */
 233 #include "tps65910.dtsi"
 234
 235 &tps {
 236         vcc1-supply = <&vbat>;
 237         vcc2-supply = <&vbat>;
 238         vcc3-supply = <&vbat>;
 239         vcc4-supply = <&vbat>;
 240         vcc5-supply = <&vbat>;
 241         vcc6-supply = <&vbat>;
 242         vcc7-supply = <&vbat>;
 243         vccio-supply = <&vbat>;
 244
 245         regulators {
 246                 vrtc_reg: regulator@0 {
 247                         regulator-always-on;
 248                 };
 249
 250                 vio_reg: regulator@1 {
 251                         regulator-always-on;
 252                 };
 253
 254                 vdd1_reg: regulator@2 {
 255                         /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
 256                         regulator-name = "vdd_mpu";
 257                         regulator-min-microvolt = <912500>;
 258                         regulator-max-microvolt = <1378000>;
 259                         regulator-boot-on;
 260                         regulator-always-on;
 261                 };
 262
 263                 vdd2_reg: regulator@3 {
 264                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 265                         regulator-name = "vdd_core";
 266                         regulator-min-microvolt = <912500>;
 267                         regulator-max-microvolt = <1150000>;
 268                         regulator-boot-on;
 269                         regulator-always-on;
 270                 };
 271
 272                 vdd3_reg: regulator@4 {
 273                         regulator-always-on;
 274                 };
 275
 276                 vdig1_reg: regulator@5 {
 277                         regulator-name = "vdig1_1p8v";
 278                         regulator-min-microvolt = <1800000>;
 279                         regulator-max-microvolt = <1800000>;
 280                 };
 281
 282                 vdig2_reg: regulator@6 {
 283                         regulator-always-on;
 284                 };
 285
 286                 vpll_reg: regulator@7 {
 287                         regulator-always-on;
 288                 };
 289
 290                 vdac_reg: regulator@8 {
 291                         regulator-always-on;
 292                 };
 293
 294                 vaux1_reg: regulator@9 {
 295                         regulator-always-on;
 296                 };
 297
 298                 vaux2_reg: regulator@10 {
 299                         regulator-always-on;
 300                 };
 301
 302                 vaux33_reg: regulator@11 {
 303                         regulator-always-on;
 304                 };
 305
 306                 vmmc_reg: regulator@12 {
 307                         regulator-min-microvolt = <3300000>;
 308                         regulator-max-microvolt = <3300000>;
 309                         regulator-always-on;
 310                 };
 311         };
 312 };
 313
 314 &vbat {
 315         regulator-name = "vbat";
 316         regulator-min-microvolt = <5000000>;
 317         regulator-max-microvolt = <5000000>;
 318         regulator-boot-on;
 319 };
 320
 321 /* SPI Busses */
 322 &am33xx_pinmux {
 323         spi0_pins: pinmux_spi0 {
 324                 pinctrl-single,pins = <
 325                         0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* spi0_clk.spi0_clk */
 326                         0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* spi0_d0.spi0_d0 */
 327                         0x158 (PIN_INPUT_PULLUP | MUX_MODE0)    /* spi0_d1.spi0_d1 */
 328                         0x15c (PIN_INPUT_PULLUP | MUX_MODE0)    /* spi0_cs0.spi0_cs0 */
 329                 >;
 330         };
 331 };
 332
 333 &spi0 {
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&spi0_pins>;
 336         status = "okay";
 337
 338         serial_flash: m25p80@0 {
 339                 compatible = "m25p80";
 340                 spi-max-frequency = <48000000>;
 341                 reg = <0x0>;
 342                 m25p,fast-read;
 343                 status = "disabled";
 344                 #address-cells = <1>;
 345                 #size-cells = <1>;
 346
 347                 partition@0 {
 348                         label = "xload";
 349                         reg = <0x0 0x20000>;
 350                 };
 351                 partition@1 {
 352                         label = "barebox";
 353                         reg = <0x20000 0x80000>;
 354                 };
 355                 partition@2 {
 356                         label = "bareboxenv";
 357                         reg = <0xa0000 0x20000>;
 358                 };
 359                 partition@3 {
 360                         label = "oftree";
 361                         reg = <0xc0000 0x20000>;
 362                 };
 363                 partition@4 {
 364                         label = "kernel";
 365                         reg = <0xe0000 0x0>;
 366                 };
 367         };
 368 };