arch/arm/boot/dts/am335x-igep0033.dtsi

   1 /*
   2  * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
   3  *
   4  * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "am33xx.dtsi"
  14
  15 / {
  16         cpus {
  17                 cpu@0 {
  18                         cpu0-supply = <&vdd1_reg>;
  19                 };
  20         };
  21
  22         memory {
  23                 device_type = "memory";
  24                 reg = <0x80000000 0x10000000>; /* 256 MB */
  25         };
  26
  27         leds {
  28                 pinctrl-names = "default";
  29                 pinctrl-0 = <&leds_pins>;
  30
  31                 compatible = "gpio-leds";
  32
  33                 led@0 {
  34                         label = "com:green:user";
  35                         gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
  36                         default-state = "on";
  37                 };
  38         };
  39
  40         vbat: fixedregulator@0 {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "vbat";
  43                 regulator-min-microvolt = <5000000>;
  44                 regulator-max-microvolt = <5000000>;
  45                 regulator-boot-on;
  46         };
  47
  48         vmmc: fixedregulator@0 {
  49                 compatible = "regulator-fixed";
  50                 regulator-name = "vmmc";
  51                 regulator-min-microvolt = <3300000>;
  52                 regulator-max-microvolt = <3300000>;
  53         };
  54 };
  55
  56 &am33xx_pinmux {
  57         i2c0_pins: pinmux_i2c0_pins {
  58                 pinctrl-single,pins = <
  59                         0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
  60                         0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
  61                 >;
  62         };
  63
  64         nandflash_pins: pinmux_nandflash_pins {
  65                 pinctrl-single,pins = <
  66                         0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
  67                         0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
  68                         0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
  69                         0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
  70                         0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
  71                         0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
  72                         0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
  73                         0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
  74                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
  75                         0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
  76                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0 */
  77                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
  78                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
  79                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
  80                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
  81                 >;
  82         };
  83
  84         uart0_pins: pinmux_uart0_pins {
  85                 pinctrl-single,pins = <
  86                         0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
  87                         0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  88                 >;
  89         };
  90
  91         leds_pins: pinmux_leds_pins {
  92                 pinctrl-single,pins = <
  93                         0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
  94                 >;
  95         };
  96 };
  97
  98 &cpsw_emac0 {
  99         phy_id = <&davinci_mdio>, <0>;
 100 };
 101
 102 &cpsw_emac1 {
 103         phy_id = <&davinci_mdio>, <1>;
 104 };
 105
 106 &elm {
 107         status = "okay";
 108 };
 109
 110 &gpmc {
 111         status = "okay";
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&nandflash_pins>;
 114
 115         ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
 116
 117         nand@0,0 {
 118                 reg = <0 0 0>; /* CS0, offset 0 */
 119                 nand-bus-width = <8>;
 120                 ti,nand-ecc-opt = "bch8";
 121                 gpmc,device-nand = "true";
 122                 gpmc,device-width = <1>;
 123                 gpmc,sync-clk-ps = <0>;
 124                 gpmc,cs-on-ns = <0>;
 125                 gpmc,cs-rd-off-ns = <44>;
 126                 gpmc,cs-wr-off-ns = <44>;
 127                 gpmc,adv-on-ns = <6>;
 128                 gpmc,adv-rd-off-ns = <34>;
 129                 gpmc,adv-wr-off-ns = <44>;
 130                 gpmc,we-on-ns = <0>;
 131                 gpmc,we-off-ns = <40>;
 132                 gpmc,oe-on-ns = <0>;
 133                 gpmc,oe-off-ns = <54>;
 134                 gpmc,access-ns = <64>;
 135                 gpmc,rd-cycle-ns = <82>;
 136                 gpmc,wr-cycle-ns = <82>;
 137                 gpmc,wait-on-read = "true";
 138                 gpmc,wait-on-write = "true";
 139                 gpmc,bus-turnaround-ns = <0>;
 140                 gpmc,cycle2cycle-delay-ns = <0>;
 141                 gpmc,clk-activation-ns = <0>;
 142                 gpmc,wait-monitoring-ns = <0>;
 143                 gpmc,wr-access-ns = <40>;
 144                 gpmc,wr-data-mux-bus-ns = <0>;
 145
 146                 #address-cells = <1>;
 147                 #size-cells = <1>;
 148                 elm_id = <&elm>;
 149
 150                 /* MTD partition table */
 151                 partition@0 {
 152                         label = "SPL";
 153                         reg = <0x00000000 0x000080000>;
 154                 };
 155
 156                 partition@1 {
 157                         label = "U-boot";
 158                         reg = <0x00080000 0x001e0000>;
 159                 };
 160
 161                 partition@2 {
 162                         label = "U-Boot Env";
 163                         reg = <0x00260000 0x00020000>;
 164                 };
 165
 166                 partition@3 {
 167                         label = "Kernel";
 168                         reg = <0x00280000 0x00500000>;
 169                 };
 170
 171                 partition@4 {
 172                         label = "File System";
 173                         reg = <0x00780000 0x007880000>;
 174                 };
 175         };
 176 };
 177
 178 &i2c0 {
 179         status = "okay";
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&i2c0_pins>;
 182
 183         clock-frequency = <400000>;
 184
 185         tps: tps@2d {
 186                 reg = <0x2d>;
 187         };
 188 };
 189
 190 &mmc1 {
 191         status = "okay";
 192         vmmc-supply = <&vmmc>;
 193         bus-width = <4>;
 194 };
 195
 196 &uart0 {
 197         status = "okay";
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&uart0_pins>;
 200 };
 201
 202 #include "tps65910.dtsi"
 203
 204 &tps {
 205         vcc1-supply = <&vbat>;
 206         vcc2-supply = <&vbat>;
 207         vcc3-supply = <&vbat>;
 208         vcc4-supply = <&vbat>;
 209         vcc5-supply = <&vbat>;
 210         vcc6-supply = <&vbat>;
 211         vcc7-supply = <&vbat>;
 212         vccio-supply = <&vbat>;
 213
 214         regulators {
 215                 vrtc_reg: regulator@0 {
 216                         regulator-always-on;
 217                 };
 218
 219                 vio_reg: regulator@1 {
 220                         regulator-always-on;
 221                 };
 222
 223                 vdd1_reg: regulator@2 {
 224                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 225                         regulator-name = "vdd_mpu";
 226                         regulator-min-microvolt = <912500>;
 227                         regulator-max-microvolt = <1312500>;
 228                         regulator-boot-on;
 229                         regulator-always-on;
 230                 };
 231
 232                 vdd2_reg: regulator@3 {
 233                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 234                         regulator-name = "vdd_core";
 235                         regulator-min-microvolt = <912500>;
 236                         regulator-max-microvolt = <1150000>;
 237                         regulator-boot-on;
 238                         regulator-always-on;
 239                 };
 240
 241                 vdd3_reg: regulator@4 {
 242                         regulator-always-on;
 243                 };
 244
 245                 vdig1_reg: regulator@5 {
 246                         regulator-always-on;
 247                 };
 248
 249                 vdig2_reg: regulator@6 {
 250                         regulator-always-on;
 251                 };
 252
 253                 vpll_reg: regulator@7 {
 254                         regulator-always-on;
 255                 };
 256
 257                 vdac_reg: regulator@8 {
 258                         regulator-always-on;
 259                 };
 260
 261                 vaux1_reg: regulator@9 {
 262                         regulator-always-on;
 263                 };
 264
 265                 vaux2_reg: regulator@10 {
 266                         regulator-always-on;
 267                 };
 268
 269                 vaux33_reg: regulator@11 {
 270                         regulator-always-on;
 271                 };
 272
 273                 vmmc_reg: regulator@12 {
 274                         regulator-always-on;
 275                 };
 276         };
 277 };
 278