4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
14 #include <linux/sched.h>
15 #include <linux/cache.h>
16 #include <linux/mmu_context.h>
17 #include <linux/syscalls.h>
18 #include <linux/uaccess.h>
19 #include <linux/pagemap.h>
20 #include <asm/cacheflush.h>
21 #include <asm/cachectl.h>
22 #include <asm/setup.h>
24 static int l2_line_sz;
26 void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr,
27 unsigned long sz, const int cacheop);
29 char *arc_cache_mumbojumbo(int c, char *buf, int len)
32 struct cpuinfo_arc_cache *p;
34 #define PR_CACHE(p, cfg, str) \
36 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
38 n += scnprintf(buf + n, len - n, \
39 str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \
40 (p)->sz_k, (p)->assoc, (p)->line_len, \
41 (p)->vipt ? "VIPT" : "PIPT", \
42 (p)->alias ? " aliasing" : "", \
43 IS_ENABLED(cfg) ? "" : " (not used)");
45 PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache");
46 PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");
48 p = &cpuinfo_arc700[c].slc;
50 n += scnprintf(buf + n, len - n,
51 "SLC\t\t: %uK, %uB Line\n", p->sz_k, p->line_len);
57 * Read the Cache Build Confuration Registers, Decode them and save into
58 * the cpuinfo structure for later use.
59 * No Validation done here, simply read/convert the BCRs
61 void read_decode_cache_bcr(void)
63 struct cpuinfo_arc_cache *p_ic, *p_dc, *p_slc;
64 unsigned int cpu = smp_processor_id();
66 #ifdef CONFIG_CPU_BIG_ENDIAN
67 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
69 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
73 struct bcr_generic sbcr;
76 #ifdef CONFIG_CPU_BIG_ENDIAN
77 unsigned int pad:24, way:2, lsz:2, sz:4;
79 unsigned int sz:4, lsz:2, way:2, pad:24;
83 p_ic = &cpuinfo_arc700[cpu].icache;
84 READ_BCR(ARC_REG_IC_BCR, ibcr);
90 BUG_ON(ibcr.config != 3);
91 p_ic->assoc = 2; /* Fixed to 2w set assoc */
92 } else if (ibcr.ver >= 4) {
93 p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */
96 p_ic->line_len = 8 << ibcr.line_len;
97 p_ic->sz_k = 1 << (ibcr.sz - 1);
100 p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1;
103 p_dc = &cpuinfo_arc700[cpu].dcache;
104 READ_BCR(ARC_REG_DC_BCR, dbcr);
110 BUG_ON(dbcr.config != 2);
111 p_dc->assoc = 4; /* Fixed to 4w set assoc */
113 p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1;
114 } else if (dbcr.ver >= 4) {
115 p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */
117 p_dc->alias = 0; /* PIPT so can't VIPT alias */
120 p_dc->line_len = 16 << dbcr.line_len;
121 p_dc->sz_k = 1 << (dbcr.sz - 1);
122 p_dc->ver = dbcr.ver;
128 p_slc = &cpuinfo_arc700[cpu].slc;
129 READ_BCR(ARC_REG_SLC_BCR, sbcr);
131 READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
132 p_slc->ver = sbcr.ver;
133 p_slc->sz_k = 128 << slc_cfg.sz;
134 l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64;
139 * Line Operation on {I,D}-Cache
144 #define OP_FLUSH_N_INV 0x3
145 #define OP_INV_IC 0x4
148 * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3)
150 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
151 * The orig Cache Management Module "CDU" only required paddr to invalidate a
152 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
153 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
154 * the exact same line.
156 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
157 * paddr alone could not be used to correctly index the cache.
160 * MMU v1/v2 (Fixed Page Size 8k)
162 * The solution was to provide CDU with these additonal vaddr bits. These
163 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
164 * standard page size of 8k.
165 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
166 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
167 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
168 * represent the offset within cache-line. The adv of using this "clumsy"
169 * interface for additional info was no new reg was needed in CDU programming
172 * 17:13 represented the max num of bits passable, actual bits needed were
173 * fewer, based on the num-of-aliases possible.
174 * -for 2 alias possibility, only bit 13 needed (32K cache)
175 * -for 4 alias possibility, bits 14:13 needed (64K cache)
180 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
181 * only support 8k (default), 16k and 4k.
182 * However from hardware perspective, smaller page sizes aggrevate aliasing
183 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
184 * the existing scheme of piggybacking won't work for certain configurations.
185 * Two new registers IC_PTAG and DC_PTAG inttoduced.
186 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
190 void __cache_line_loop_v2(unsigned long paddr, unsigned long vaddr,
191 unsigned long sz, const int op)
193 unsigned int aux_cmd;
195 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
197 if (op == OP_INV_IC) {
198 aux_cmd = ARC_REG_IC_IVIL;
200 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
201 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
204 /* Ensure we properly floor/ceil the non-line aligned/sized requests
205 * and have @paddr - aligned to cache line and integral @num_lines.
206 * This however can be avoided for page sized since:
207 * -@paddr will be cache-line aligned already (being page aligned)
208 * -@sz will be integral multiple of line size (being page sized).
211 sz += paddr & ~CACHE_LINE_MASK;
212 paddr &= CACHE_LINE_MASK;
213 vaddr &= CACHE_LINE_MASK;
216 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
218 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
219 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
221 while (num_lines-- > 0) {
222 write_aux_reg(aux_cmd, paddr);
223 paddr += L1_CACHE_BYTES;
228 void __cache_line_loop_v3(unsigned long paddr, unsigned long vaddr,
229 unsigned long sz, const int op)
231 unsigned int aux_cmd, aux_tag;
233 const int full_page = __builtin_constant_p(sz) && sz == PAGE_SIZE;
235 if (op == OP_INV_IC) {
236 aux_cmd = ARC_REG_IC_IVIL;
237 aux_tag = ARC_REG_IC_PTAG;
239 aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
240 aux_tag = ARC_REG_DC_PTAG;
243 /* Ensure we properly floor/ceil the non-line aligned/sized requests
244 * and have @paddr - aligned to cache line and integral @num_lines.
245 * This however can be avoided for page sized since:
246 * -@paddr will be cache-line aligned already (being page aligned)
247 * -@sz will be integral multiple of line size (being page sized).
250 sz += paddr & ~CACHE_LINE_MASK;
251 paddr &= CACHE_LINE_MASK;
252 vaddr &= CACHE_LINE_MASK;
254 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
257 * MMUv3, cache ops require paddr in PTAG reg
258 * if V-P const for loop, PTAG can be written once outside loop
261 write_aux_reg(aux_tag, paddr);
263 while (num_lines-- > 0) {
265 write_aux_reg(aux_tag, paddr);
266 paddr += L1_CACHE_BYTES;
269 write_aux_reg(aux_cmd, vaddr);
270 vaddr += L1_CACHE_BYTES;
275 * In HS38x (MMU v4), although icache is VIPT, only paddr is needed for cache
276 * maintenance ops (in IVIL reg), as long as icache doesn't alias.
278 * For Aliasing icache, vaddr is also needed (in IVIL), while paddr is
279 * specified in PTAG (similar to MMU v3)
282 void __cache_line_loop_v4(unsigned long paddr, unsigned long vaddr,
283 unsigned long sz, const int cacheop)
285 unsigned int aux_cmd;
287 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
289 if (cacheop == OP_INV_IC) {
290 aux_cmd = ARC_REG_IC_IVIL;
292 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
293 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
296 /* Ensure we properly floor/ceil the non-line aligned/sized requests
297 * and have @paddr - aligned to cache line and integral @num_lines.
298 * This however can be avoided for page sized since:
299 * -@paddr will be cache-line aligned already (being page aligned)
300 * -@sz will be integral multiple of line size (being page sized).
303 sz += paddr & ~CACHE_LINE_MASK;
304 paddr &= CACHE_LINE_MASK;
307 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
309 while (num_lines-- > 0) {
310 write_aux_reg(aux_cmd, paddr);
311 paddr += L1_CACHE_BYTES;
315 #if (CONFIG_ARC_MMU_VER < 3)
316 #define __cache_line_loop __cache_line_loop_v2
317 #elif (CONFIG_ARC_MMU_VER == 3)
318 #define __cache_line_loop __cache_line_loop_v3
319 #elif (CONFIG_ARC_MMU_VER > 3)
320 #define __cache_line_loop __cache_line_loop_v4
323 #ifdef CONFIG_ARC_HAS_DCACHE
325 /***************************************************************
326 * Machine specific helpers for Entire D-Cache or Per Line ops
329 static inline void __before_dc_op(const int op)
331 if (op == OP_FLUSH_N_INV) {
332 /* Dcache provides 2 cmd: FLUSH or INV
333 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
334 * flush-n-inv is achieved by INV cmd but with IM=1
335 * So toggle INV sub-mode depending on op request and default
337 const unsigned int ctl = ARC_REG_DC_CTRL;
338 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
342 static inline void __after_dc_op(const int op)
345 const unsigned int ctl = ARC_REG_DC_CTRL;
348 /* flush / flush-n-inv both wait */
349 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS)
352 /* Switch back to default Invalidate mode */
353 if (op == OP_FLUSH_N_INV)
354 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);
359 * Operation on Entire D-Cache
360 * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
361 * Note that constant propagation ensures all the checks are gone
364 static inline void __dc_entire_op(const int op)
370 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
371 aux = ARC_REG_DC_IVDC;
373 aux = ARC_REG_DC_FLSH;
375 write_aux_reg(aux, 0x1);
380 /* For kernel mappings cache operation: index is same as paddr */
381 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
384 * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback)
386 static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
387 unsigned long sz, const int op)
391 local_irq_save(flags);
395 __cache_line_loop(paddr, vaddr, sz, op);
399 local_irq_restore(flags);
404 #define __dc_entire_op(op)
405 #define __dc_line_op(paddr, vaddr, sz, op)
406 #define __dc_line_op_k(paddr, sz, op)
408 #endif /* CONFIG_ARC_HAS_DCACHE */
410 #ifdef CONFIG_ARC_HAS_ICACHE
412 static inline void __ic_entire_inv(void)
414 write_aux_reg(ARC_REG_IC_IVIC, 1);
415 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
419 __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr,
424 local_irq_save(flags);
425 (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
426 local_irq_restore(flags);
431 #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s)
436 unsigned long paddr, vaddr;
440 static void __ic_line_inv_vaddr_helper(void *info)
442 struct ic_inv_args *ic_inv = info;
444 __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz);
447 static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
450 struct ic_inv_args ic_inv = {
456 on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1);
459 #endif /* CONFIG_SMP */
461 #else /* !CONFIG_ARC_HAS_ICACHE */
463 #define __ic_entire_inv()
464 #define __ic_line_inv_vaddr(pstart, vstart, sz)
466 #endif /* CONFIG_ARC_HAS_ICACHE */
468 noinline void slc_op(unsigned long paddr, unsigned long sz, const int op)
470 #ifdef CONFIG_ISA_ARCV2
474 local_irq_save(flags);
477 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
478 * - b'000 (default) is Flush,
479 * - b'001 is Invalidate if CTRL.IM == 0
480 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
482 ctrl = read_aux_reg(ARC_REG_SLC_CTRL);
484 /* Don't rely on default value of IM bit */
485 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
486 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
491 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
493 ctrl &= ~SLC_CTRL_RGN_OP_INV;
495 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
498 * Lower bits are ignored, no need to clip
499 * END needs to be setup before START (latter triggers the operation)
500 * END can't be same as START, so add (l2_line_sz - 1) to sz
502 write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
503 write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
505 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
507 local_irq_restore(flags);
511 static inline int need_slc_flush(void)
513 return is_isa_arcv2() && l2_line_sz;
516 /***********************************************************
521 * Handle cache congruency of kernel and userspace mappings of page when kernel
522 * writes-to/reads-from
524 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
525 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
526 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
527 * -In SMP, if hardware caches are coherent
529 * There's a corollary case, where kernel READs from a userspace mapped page.
530 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
532 void flush_dcache_page(struct page *page)
534 struct address_space *mapping;
536 if (!cache_is_vipt_aliasing()) {
537 clear_bit(PG_dc_clean, &page->flags);
541 /* don't handle anon pages here */
542 mapping = page_mapping(page);
547 * pagecache page, file not yet mapped to userspace
548 * Make a note that K-mapping is dirty
550 if (!mapping_mapped(mapping)) {
551 clear_bit(PG_dc_clean, &page->flags);
552 } else if (page_mapped(page)) {
554 /* kernel reading from page with U-mapping */
555 unsigned long paddr = (unsigned long)page_address(page);
556 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
558 if (addr_not_cache_congruent(paddr, vaddr))
559 __flush_dcache_page(paddr, vaddr);
562 EXPORT_SYMBOL(flush_dcache_page);
564 void dma_cache_wback_inv(unsigned long start, unsigned long sz)
566 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
568 if (need_slc_flush())
569 slc_op(start, sz, OP_FLUSH_N_INV);
571 EXPORT_SYMBOL(dma_cache_wback_inv);
573 void dma_cache_inv(unsigned long start, unsigned long sz)
575 __dc_line_op_k(start, sz, OP_INV);
577 if (need_slc_flush())
578 slc_op(start, sz, OP_INV);
580 EXPORT_SYMBOL(dma_cache_inv);
582 void dma_cache_wback(unsigned long start, unsigned long sz)
584 __dc_line_op_k(start, sz, OP_FLUSH);
586 if (need_slc_flush())
587 slc_op(start, sz, OP_FLUSH);
589 EXPORT_SYMBOL(dma_cache_wback);
592 * This is API for making I/D Caches consistent when modifying
593 * kernel code (loadable modules, kprobes, kgdb...)
594 * This is called on insmod, with kernel virtual address for CODE of
595 * the module. ARC cache maintenance ops require PHY address thus we
596 * need to convert vmalloc addr to PHY addr
598 void flush_icache_range(unsigned long kstart, unsigned long kend)
602 WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__);
604 /* Shortcut for bigger flush ranges.
605 * Here we don't care if this was kernel virtual or phy addr
607 tot_sz = kend - kstart;
608 if (tot_sz > PAGE_SIZE) {
613 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
614 if (likely(kstart > PAGE_OFFSET)) {
616 * The 2nd arg despite being paddr will be used to index icache
617 * This is OK since no alternate virtual mappings will exist
618 * given the callers for this case: kprobe/kgdb in built-in
621 __sync_icache_dcache(kstart, kstart, kend - kstart);
626 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
627 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
628 * handling of kernel vaddr.
630 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
631 * it still needs to handle a 2 page scenario, where the range
632 * straddles across 2 virtual pages and hence need for loop
635 unsigned int off, sz;
636 unsigned long phy, pfn;
638 off = kstart % PAGE_SIZE;
639 pfn = vmalloc_to_pfn((void *)kstart);
640 phy = (pfn << PAGE_SHIFT) + off;
641 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
642 __sync_icache_dcache(phy, kstart, sz);
647 EXPORT_SYMBOL(flush_icache_range);
650 * General purpose helper to make I and D cache lines consistent.
651 * @paddr is phy addr of region
652 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
653 * However in one instance, when called by kprobe (for a breakpt in
654 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
655 * use a paddr to index the cache (despite VIPT). This is fine since since a
656 * builtin kernel page will not have any virtual mappings.
657 * kprobe on loadable module will be kernel vaddr.
659 void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
661 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
662 __ic_line_inv_vaddr(paddr, vaddr, len);
665 /* wrapper to compile time eliminate alignment checks in flush loop */
666 void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
668 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
672 * wrapper to clearout kernel or userspace mappings of a page
673 * For kernel mappings @vaddr == @paddr
675 void __flush_dcache_page(unsigned long paddr, unsigned long vaddr)
677 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
680 noinline void flush_cache_all(void)
684 local_irq_save(flags);
687 __dc_entire_op(OP_FLUSH_N_INV);
689 local_irq_restore(flags);
693 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
695 void flush_cache_mm(struct mm_struct *mm)
700 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
703 unsigned int paddr = pfn << PAGE_SHIFT;
705 u_vaddr &= PAGE_MASK;
707 __flush_dcache_page(paddr, u_vaddr);
709 if (vma->vm_flags & VM_EXEC)
710 __inv_icache_page(paddr, u_vaddr);
713 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
719 void flush_anon_page(struct vm_area_struct *vma, struct page *page,
720 unsigned long u_vaddr)
722 /* TBD: do we really need to clear the kernel mapping */
723 __flush_dcache_page(page_address(page), u_vaddr);
724 __flush_dcache_page(page_address(page), page_address(page));
730 void copy_user_highpage(struct page *to, struct page *from,
731 unsigned long u_vaddr, struct vm_area_struct *vma)
733 unsigned long kfrom = (unsigned long)page_address(from);
734 unsigned long kto = (unsigned long)page_address(to);
735 int clean_src_k_mappings = 0;
738 * If SRC page was already mapped in userspace AND it's U-mapping is
739 * not congruent with K-mapping, sync former to physical page so that
740 * K-mapping in memcpy below, sees the right data
742 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
743 * equally valid for SRC page as well
745 if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
746 __flush_dcache_page(kfrom, u_vaddr);
747 clean_src_k_mappings = 1;
750 copy_page((void *)kto, (void *)kfrom);
753 * Mark DST page K-mapping as dirty for a later finalization by
754 * update_mmu_cache(). Although the finalization could have been done
755 * here as well (given that both vaddr/paddr are available).
756 * But update_mmu_cache() already has code to do that for other
757 * non copied user pages (e.g. read faults which wire in pagecache page
760 clear_bit(PG_dc_clean, &to->flags);
763 * if SRC was already usermapped and non-congruent to kernel mapping
764 * sync the kernel mapping back to physical page
766 if (clean_src_k_mappings) {
767 __flush_dcache_page(kfrom, kfrom);
768 set_bit(PG_dc_clean, &from->flags);
770 clear_bit(PG_dc_clean, &from->flags);
774 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
777 clear_bit(PG_dc_clean, &page->flags);
781 /**********************************************************************
782 * Explicit Cache flush request from user space via syscall
783 * Needed for JITs which generate code on the fly
785 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
787 /* TBD: optimize this */
792 void arc_cache_init(void)
794 unsigned int __maybe_unused cpu = smp_processor_id();
797 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
799 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
800 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
803 panic("cache support enabled but non-existent cache\n");
805 if (ic->line_len != L1_CACHE_BYTES)
806 panic("ICache line [%d] != kernel Config [%d]",
807 ic->line_len, L1_CACHE_BYTES);
809 if (ic->ver != CONFIG_ARC_MMU_VER)
810 panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
811 ic->ver, CONFIG_ARC_MMU_VER);
814 * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG
815 * pair to provide vaddr/paddr respectively, just as in MMU v3
817 if (is_isa_arcv2() && ic->alias)
818 _cache_line_loop_ic_fn = __cache_line_loop_v3;
820 _cache_line_loop_ic_fn = __cache_line_loop;
823 if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
824 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
827 panic("cache support enabled but non-existent cache\n");
829 if (dc->line_len != L1_CACHE_BYTES)
830 panic("DCache line [%d] != kernel Config [%d]",
831 dc->line_len, L1_CACHE_BYTES);
833 /* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
834 if (is_isa_arcompact()) {
835 int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
837 if (dc->alias && !handled)
838 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
839 else if (!dc->alias && handled)
840 panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");