2 * linux/arch/alpha/kernel/pci.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
9 /* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
12 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * PCI-PCI bridges cleanup
15 #include <linux/string.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/bootmem.h>
21 #include <linux/module.h>
22 #include <linux/cache.h>
23 #include <linux/slab.h>
24 #include <asm/machvec.h>
31 * Some string constants used by the various core logics.
34 const char *const pci_io_names[] = {
35 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
36 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
39 const char *const pci_mem_names[] = {
40 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
41 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
44 const char pci_hae0_name[] = "HAE0";
47 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
52 * The PCI controller list.
55 struct pci_controller *hose_head, **hose_tail = &hose_head;
56 struct pci_controller *pci_isa_hose;
62 static void quirk_isa_bridge(struct pci_dev *dev)
64 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
66 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
68 static void quirk_cypress(struct pci_dev *dev)
70 /* The Notorious Cy82C693 chip. */
72 /* The generic legacy mode IDE fixup in drivers/pci/probe.c
73 doesn't work correctly with the Cypress IDE controller as
74 it has non-standard register layout. Fix that. */
75 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
76 dev->resource[2].start = dev->resource[3].start = 0;
77 dev->resource[2].end = dev->resource[3].end = 0;
78 dev->resource[2].flags = dev->resource[3].flags = 0;
79 if (PCI_FUNC(dev->devfn) == 2) {
80 dev->resource[0].start = 0x170;
81 dev->resource[0].end = 0x177;
82 dev->resource[1].start = 0x376;
83 dev->resource[1].end = 0x376;
87 /* The Cypress bridge responds on the PCI bus in the address range
88 0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
89 way to turn this off. The bridge also supports several extended
90 BIOS ranges (disabled after power-up), and some consoles do turn
91 them on. So if we use a large direct-map window, or a large SG
92 window, we must avoid the entire 0xfff00000-0xffffffff region. */
93 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
94 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
95 __direct_map_size = 0xfff00000UL - __direct_map_base;
97 struct pci_controller *hose = dev->sysdata;
98 struct pci_iommu_arena *pci = hose->sg_pci;
99 if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
100 pci->size = 0xfff00000UL - pci->dma_base;
104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
106 /* Called for each device after PCI setup is done. */
107 static void pcibios_fixup_final(struct pci_dev *dev)
109 unsigned int class = dev->class >> 8;
111 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
112 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
116 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
118 /* Just declaring that the power-of-ten prefixes are actually the
119 power-of-two ones doesn't make it true :) */
125 pcibios_align_resource(void *data, const struct resource *res,
126 resource_size_t size, resource_size_t align)
128 struct pci_dev *dev = data;
129 struct pci_controller *hose = dev->sysdata;
130 unsigned long alignto;
131 resource_size_t start = res->start;
133 if (res->flags & IORESOURCE_IO) {
134 /* Make sure we start at our min on all hoses */
135 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
136 start = PCIBIOS_MIN_IO + hose->io_space->start;
139 * Put everything into 0x00-0xff region modulo 0x400
142 start = (start + 0x3ff) & ~0x3ff;
144 else if (res->flags & IORESOURCE_MEM) {
145 /* Make sure we start at our min on all hoses */
146 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
147 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
150 * The following holds at least for the Low Cost
151 * Alpha implementation of the PCI interface:
153 * In sparse memory address space, the first
154 * octant (16MB) of every 128MB segment is
155 * aliased to the very first 16 MB of the
156 * address space (i.e., it aliases the ISA
157 * memory address space). Thus, we try to
158 * avoid allocating PCI devices in that range.
159 * Can be allocated in 2nd-7th octant only.
160 * Devices that need more than 112MB of
161 * address space must be accessed through
162 * dense memory space only!
165 /* Align to multiple of size of minimum base. */
166 alignto = max_t(resource_size_t, 0x1000, align);
167 start = ALIGN(start, alignto);
168 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
169 if (((start / (16*MB)) & 0x7) == 0) {
170 start &= ~(128*MB - 1);
172 start = ALIGN(start, alignto);
174 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
175 start &= ~(128*MB - 1);
176 start += (128 + 16)*MB;
177 start = ALIGN(start, alignto);
191 if (alpha_mv.init_pci)
196 subsys_initcall(pcibios_init);
198 #ifdef ALPHA_RESTORE_SRM_SETUP
199 static struct pdev_srm_saved_conf *srm_saved_configs;
201 void pdev_save_srm_config(struct pci_dev *dev)
203 struct pdev_srm_saved_conf *tmp;
204 static int printed = 0;
206 if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
210 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
214 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
216 printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
219 tmp->next = srm_saved_configs;
224 srm_saved_configs = tmp;
228 pci_restore_srm_config(void)
230 struct pdev_srm_saved_conf *tmp;
232 /* No need to restore if probed only. */
233 if (pci_has_flag(PCI_PROBE_ONLY))
236 /* Restore SRM config. */
237 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
238 pci_restore_state(tmp->dev);
243 void pcibios_fixup_bus(struct pci_bus *bus)
245 struct pci_dev *dev = bus->self;
247 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
248 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
249 pci_read_bridge_bases(bus);
252 list_for_each_entry(dev, &bus->devices, bus_list) {
253 pdev_save_srm_config(dev);
258 * If we set up a device for bus mastering, we need to check the latency
259 * timer as certain firmware forgets to set it properly, as seen
260 * on SX164 and LX164 with SRM.
263 pcibios_set_master(struct pci_dev *dev)
266 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
267 if (lat >= 16) return;
268 printk("PCI: Setting latency timer of device %s to 64\n",
270 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
274 pcibios_claim_one_bus(struct pci_bus *b)
277 struct pci_bus *child_bus;
279 list_for_each_entry(dev, &b->devices, bus_list) {
282 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
283 struct resource *r = &dev->resource[i];
285 if (r->parent || !r->start || !r->flags)
287 if (pci_has_flag(PCI_PROBE_ONLY) ||
288 (r->flags & IORESOURCE_PCI_FIXED)) {
289 if (pci_claim_resource(dev, i) == 0)
292 pci_claim_bridge_resource(dev, i);
297 list_for_each_entry(child_bus, &b->children, node)
298 pcibios_claim_one_bus(child_bus);
302 pcibios_claim_console_setup(void)
306 list_for_each_entry(b, &pci_root_buses, node)
307 pcibios_claim_one_bus(b);
311 common_init_pci(void)
313 struct pci_controller *hose;
314 struct list_head resources;
317 int need_domain_info = 0;
322 /* Scan all of the recorded PCI controllers. */
323 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
324 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
326 /* Adjust hose mem_space limit to prevent PCI allocations
327 in the iommu windows. */
328 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
329 end = hose->mem_space->start + pci_mem_end;
330 if (hose->mem_space->end > end)
331 hose->mem_space->end = end;
333 INIT_LIST_HEAD(&resources);
334 pci_add_resource_offset(&resources, hose->io_space,
335 hose->io_space->start);
336 pci_add_resource_offset(&resources, hose->mem_space,
337 hose->mem_space->start);
339 bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
342 hose->need_domain_info = need_domain_info;
343 next_busno = bus->busn_res.end + 1;
344 /* Don't allow 8-bit bus number overflow inside the hose -
345 reserve some space for bridges. */
346 if (next_busno > 224) {
348 need_domain_info = 1;
352 pcibios_claim_console_setup();
354 pci_assign_unassigned_resources();
355 pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
359 struct pci_controller * __init
360 alloc_pci_controller(void)
362 struct pci_controller *hose;
364 hose = alloc_bootmem(sizeof(*hose));
367 hose_tail = &hose->next;
372 struct resource * __init
375 struct resource *res;
377 res = alloc_bootmem(sizeof(*res));
383 /* Provide information on locations of various I/O regions in physical
384 memory. Do this on a per-card basis so that we choose the right hose. */
387 sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
389 struct pci_controller *hose;
392 /* from hose or from bus.devfn */
393 if (which & IOBASE_FROM_HOSE) {
394 for(hose = hose_head; hose; hose = hose->next)
395 if (hose->index == bus) break;
396 if (!hose) return -ENODEV;
398 /* Special hook for ISA access. */
399 if (bus == 0 && dfn == 0) {
402 dev = pci_get_bus_and_slot(bus, dfn);
410 switch (which & ~IOBASE_FROM_HOSE) {
413 case IOBASE_SPARSE_MEM:
414 return hose->sparse_mem_base;
415 case IOBASE_DENSE_MEM:
416 return hose->dense_mem_base;
417 case IOBASE_SPARSE_IO:
418 return hose->sparse_io_base;
419 case IOBASE_DENSE_IO:
420 return hose->dense_io_base;
421 case IOBASE_ROOT_BUS:
422 return hose->bus->number;
428 /* Destroy an __iomem token. Not copied from lib/iomap.c. */
430 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
436 EXPORT_SYMBOL(pci_iounmap);
438 /* FIXME: Some boxes have multiple ISA bridges! */
439 struct pci_dev *isa_bridge;
440 EXPORT_SYMBOL(isa_bridge);