Documentation/devicetree/bindings/drm/msm/dsi.txt

   1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
   2
   3 DSI Controller:
   4 Required properties:
   5 - compatible:
   6   * "qcom,mdss-dsi-ctrl"
   7 - reg: Physical base address and length of the registers of controller
   8 - reg-names: The names of register regions. The following regions are required:
   9   * "dsi_ctrl"
  10 - qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
  11   be 0 or 1, since we have 2 DSI controllers at most for now.
  12 - interrupts: The interrupt signal from the DSI block.
  13 - power-domains: Should be <&mmcc MDSS_GDSC>.
  14 - clocks: device clocks
  15   See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
  16 - clock-names: the following clocks are required:
  17   * "bus_clk"
  18   * "byte_clk"
  19   * "core_clk"
  20   * "core_mmss_clk"
  21   * "iface_clk"
  22   * "mdp_core_clk"
  23   * "pixel_clk"
  24 - vdd-supply: phandle to vdd regulator device node
  25 - vddio-supply: phandle to vdd-io regulator device node
  26 - vdda-supply: phandle to vdda regulator device node
  27 - qcom,dsi-phy: phandle to DSI PHY device node
  28
  29 Optional properties:
  30 - panel@0: Node of panel connected to this DSI controller.
  31   See files in Documentation/devicetree/bindings/panel/ for each supported
  32   panel.
  33 - qcom,dual-panel-mode: Boolean value indicating if the DSI controller is
  34   driving a panel which needs 2 DSI links.
  35 - qcom,master-panel: Boolean value indicating if the DSI controller is driving
  36   the master link of the 2-DSI panel.
  37 - qcom,sync-dual-panel: Boolean value indicating if the DSI controller is
  38   driving a 2-DSI panel whose 2 links need receive command simultaneously.
  39 - interrupt-parent: phandle to the MDP block if the interrupt signal is routed
  40   through MDP block
  41
  42 DSI PHY:
  43 Required properties:
  44 - compatible: Could be the following
  45   * "qcom,dsi-phy-28nm-hpm"
  46   * "qcom,dsi-phy-28nm-lp"
  47 - reg: Physical base address and length of the registers of PLL, PHY and PHY
  48   regulator
  49 - reg-names: The names of register regions. The following regions are required:
  50   * "dsi_pll"
  51   * "dsi_phy"
  52   * "dsi_phy_regulator"
  53 - qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
  54   be 0 or 1, since we have 2 DSI PHYs at most for now.
  55 - power-domains: Should be <&mmcc MDSS_GDSC>.
  56 - clocks: device clocks
  57   See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
  58 - clock-names: the following clocks are required:
  59   * "iface_clk"
  60 - vddio-supply: phandle to vdd-io regulator device node
  61
  62 Example:
  63         mdss_dsi0: qcom,mdss_dsi@fd922800 {
  64                 compatible = "qcom,mdss-dsi-ctrl";
  65                 qcom,dsi-host-index = <0>;
  66                 interrupt-parent = <&mdss_mdp>;
  67                 interrupts = <4 0>;
  68                 reg-names = "dsi_ctrl";
  69                 reg = <0xfd922800 0x200>;
  70                 power-domains = <&mmcc MDSS_GDSC>;
  71                 clock-names =
  72                         "bus_clk",
  73                         "byte_clk",
  74                         "core_clk",
  75                         "core_mmss_clk",
  76                         "iface_clk",
  77                         "mdp_core_clk",
  78                         "pixel_clk";
  79                 clocks =
  80                         <&mmcc MDSS_AXI_CLK>,
  81                         <&mmcc MDSS_BYTE0_CLK>,
  82                         <&mmcc MDSS_ESC0_CLK>,
  83                         <&mmcc MMSS_MISC_AHB_CLK>,
  84                         <&mmcc MDSS_AHB_CLK>,
  85                         <&mmcc MDSS_MDP_CLK>,
  86                         <&mmcc MDSS_PCLK0_CLK>;
  87                 vdda-supply = <&pma8084_l2>;
  88                 vdd-supply = <&pma8084_l22>;
  89                 vddio-supply = <&pma8084_l12>;
  90
  91                 qcom,dsi-phy = <&mdss_dsi_phy0>;
  92
  93                 qcom,dual-panel-mode;
  94                 qcom,master-panel;
  95                 qcom,sync-dual-panel;
  96
  97                 panel: panel@0 {
  98                         compatible = "sharp,lq101r1sx01";
  99                         reg = <0>;
 100                         link2 = <&secondary>;
 101
 102                         power-supply = <...>;
 103                         backlight = <...>;
 104                 };
 105         };
 106
 107         mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
 108                 compatible = "qcom,dsi-phy-28nm-hpm";
 109                 qcom,dsi-phy-index = <0>;
 110                 reg-names =
 111                         "dsi_pll",
 112                         "dsi_phy",
 113                         "dsi_phy_regulator";
 114                 reg =   <0xfd922a00 0xd4>,
 115                         <0xfd922b00 0x2b0>,
 116                         <0xfd922d80 0x7b>;
 117                 clock-names = "iface_clk";
 118                 clocks = <&mmcc MDSS_AHB_CLK>;
 119                 vddio-supply = <&pma8084_l12>;
 120         };