Documentation/devicetree/bindings/arc/archs-idu-intc.txt

   1 * ARC-HS Interrupt Distribution Unit
   2
   3   This optional 2nd level interrupt controller can be used in SMP configurations for
   4   dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
   5
   6 Properties:
   7
   8 - compatible: "snps,archs-idu-intc"
   9 - interrupt-controller: This is an interrupt controller.
  10 - interrupt-parent: <reference to parent core intc>
  11 - #interrupt-cells: Must be <2>.
  12 - interrupts: <...> specifies the upstream core irqs
  13
  14   First cell specifies the "common" IRQ from peripheral to IDU
  15   Second cell specifies the irq distribution mode to cores
  16      0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
  17
  18   intc accessed via the special ARC AUX register interface, hence "reg" property
  19   is not specified.
  20
  21 Example:
  22         core_intc: core-interrupt-controller {
  23                 compatible = "snps,archs-intc";
  24                 interrupt-controller;
  25                 #interrupt-cells = <1>;
  26         };
  27
  28         idu_intc: idu-interrupt-controller {
  29                 compatible = "snps,archs-idu-intc";
  30                 interrupt-controller;
  31                 interrupt-parent = <&core_intc>;
  32
  33                 /*
  34                  * <hwirq  distribution>
  35                  * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
  36                  */
  37                 #interrupt-cells = <2>;
  38
  39                 /* upstream core irqs: downstream these are "COMMON" irq 0,1..  */
  40                 interrupts = <24 25 26 27 28 29 30 31>;
  41         };
  42
  43         some_device: serial@c0fc1000 {
  44                 interrupt-parent = <&idu_intc>;
  45                 interrupts = <0 0>;     /* upstream idu IRQ #24, Round Robin */
  46         };