From 2ba585a2f1105195897d17c061fcb0106be5fc30 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Fri, 11 Apr 2014 13:39:24 +0800 Subject: [PATCH] ENGR00307014-06 vadc: Enable vadc function Enable vadc function. That can work at PAL 720x576 and NTSC 720x480 mode. Signed-off-by: Sandor Yu --- drivers/media/platform/mxc/capture/Kconfig | 6 + drivers/media/platform/mxc/capture/Makefile | 3 + drivers/media/platform/mxc/capture/mxc_vadc.c | 973 ++++++++++++++++++ drivers/media/platform/mxc/capture/mxc_vadc.h | 232 +++++ 4 files changed, 1214 insertions(+) create mode 100644 drivers/media/platform/mxc/capture/mxc_vadc.c create mode 100644 drivers/media/platform/mxc/capture/mxc_vadc.h diff --git a/drivers/media/platform/mxc/capture/Kconfig b/drivers/media/platform/mxc/capture/Kconfig index cee7aa31f2d1..e02feb5baccd 100644 --- a/drivers/media/platform/mxc/capture/Kconfig +++ b/drivers/media/platform/mxc/capture/Kconfig @@ -36,6 +36,12 @@ config MXC_TVIN_ADV7180 ---help--- If you plan to use the adv7180 video decoder with your MXC system, say Y here. +config MXC_VADC + tristate "mxc VADC support" + depends on VIDEO_MXC_CAPTURE && VIDEO_V4L2 + ---help--- + If you plan to use the VADC with your MXC system, say Y here. + choice prompt "Select Overlay Rounting" default MXC_IPU_DEVICE_QUEUE_SDC diff --git a/drivers/media/platform/mxc/capture/Makefile b/drivers/media/platform/mxc/capture/Makefile index 4303c0a2ccdf..a04acb5d2e32 100644 --- a/drivers/media/platform/mxc/capture/Makefile +++ b/drivers/media/platform/mxc/capture/Makefile @@ -19,3 +19,6 @@ obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI) += ov5640_camera_mipi.o adv7180_tvin-objs := adv7180.o obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o + +mxc_vadc_tvin-objs := mxc_vadc.o +obj-$(CONFIG_MXC_VADC) += mxc_vadc_tvin.o diff --git a/drivers/media/platform/mxc/capture/mxc_vadc.c b/drivers/media/platform/mxc/capture/mxc_vadc.c new file mode 100644 index 000000000000..7524f10846c9 --- /dev/null +++ b/drivers/media/platform/mxc/capture/mxc_vadc.c @@ -0,0 +1,973 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mxc_vadc.h" +#include "mxc_v4l2_capture.h" + +/* Resource names for the VADC driver. */ +#define VAFE_REGS_ADDR_RES_NAME "vadc-vafe" +#define VDEC_REGS_ADDR_RES_NAME "vadc-vdec" + +#define reg32_write(addr, val) __raw_writel(val, addr) +#define reg32_read(addr) __raw_readl(addr) +#define reg32setbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos)))) + +#define reg32clrbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos))))) + +#define GPC_CNTR 0x00 +#define IMX6SX_GPC_CNTR_VADC_ANALOG_OFF_MASK BIT(17) +#define IMX6SX_GPC_CNTR_VADC_POWER_DOWN_MASK BIT(18) + +void __iomem *vafe_regbase; +void __iomem *vdec_regbase; + +static void __iomem *gpc_regbase; + +/* + * Maintains the information on the current state of the sensor. + */ +struct vadc_data { + struct sensor_data sen; + struct clk *vadc_clk; + struct regmap *gpr; + u32 vadc_in; + v4l2_std_id std_id; +}; + +/* List of input video formats supported. The video formats is corresponding + * with v4l2 id in video_fmt_t + */ +typedef enum { + VADC_NTSC = 0, /* Locked on (M) NTSC video signal. */ + VADC_PAL, /* (B, G, H, I, N)PAL video signal. */ +} video_fmt_idx; + +/* Number of video standards supported (including 'not locked' signal). */ +#define VADC_STD_MAX (VADC_PAL + 1) + +/* Video format structure. */ +typedef struct { + int v4l2_id; /* Video for linux ID. */ + char name[16]; /* Name (e.g., "NTSC", "PAL", etc.) */ + u16 raw_width; /* Raw width. */ + u16 raw_height; /* Raw height. */ + u16 active_width; /* Active width. */ + u16 active_height; /* Active height. */ +} video_fmt_t; + +/* Description of video formats supported. + * + * PAL: raw=720x625, active=720x576. + * NTSC: raw=720x525, active=720x480. + */ +static video_fmt_t video_fmts[] = { + /* NTSC */ + { + .v4l2_id = V4L2_STD_NTSC, + .name = "NTSC", + .raw_width = 720, + .raw_height = 525, + .active_width = 720, + .active_height = 480, + }, + /* (B, G, H, I, N) PAL */ + { + .v4l2_id = V4L2_STD_PAL, + .name = "PAL", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + }, +}; + +/* Standard index of vadc. */ +static video_fmt_idx video_idx = VADC_NTSC; +static void vadc_get_std(struct vadc_data *vadc, v4l2_std_id *std); + +static void afe_voltage_clampingmode(void) +{ + reg32_write(AFE_CLAMP, 0x07); + reg32_write(AFE_CLMPAMP, 0x60); + reg32_write(AFE_CLMPDAT, 0xF0); +} + +static void afe_alwayson_clampingmode(void) +{ + reg32_write(AFE_CLAMP, 0x15); + reg32_write(AFE_CLMPDAT, 0x08); + reg32_write(AFE_CLMPAMP, 0x00); +} + +static void afe_init(void) +{ + pr_debug("%s\n", __func__); + + reg32_write(AFE_PDBUF, 0x1f); + reg32_write(AFE_PDADC, 0x0f); + reg32_write(AFE_PDSARH, 0x01); + reg32_write(AFE_PDSARL, 0xff); + reg32_write(AFE_PDADCRFH, 0x01); + reg32_write(AFE_PDADCRFL, 0xff); + reg32_write(AFE_ICTRL, 0x3a); + reg32_write(AFE_ICTLSTG, 0x1e); + + reg32_write(AFE_RCTRLSTG, 0x1e); + reg32_write(AFE_INPBUF, 0x035); + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_ADCDGN, 0x40); + reg32_write(AFE_TSTSEL, 0x10); + + reg32_write(AFE_ACCTST, 0x07); + + reg32_write(AFE_BGREG, 0x08); + + reg32_write(AFE_ADCGN, 0x09); + + /* set current controlled clamping + * always on, low current */ + reg32_write(AFE_CLAMP, 0x11); + reg32_write(AFE_CLMPAMP, 0x08); +} + +static void vdec_mode_timing_init(v4l2_std_id std) +{ + if (std == V4L2_STD_NTSC) { + /* NTSC 720x480 */ + reg32_write(VDEC_HACTS, 0x66); + reg32_write(VDEC_HACTE, 0x24); + + reg32_write(VDEC_VACTS, 0x29); + reg32_write(VDEC_VACTE, 0x04); + + /* set V Position */ + reg32_write(VDEC_VRTPOS, 0x2); + } else if (std == V4L2_STD_PAL) { + /* PAL 720x576 */ + reg32_write(VDEC_HACTS, 0x66); + reg32_write(VDEC_HACTE, 0x24); + + reg32_write(VDEC_VACTS, 0x29); + reg32_write(VDEC_VACTE, 0x04); + + /* set V Position */ + reg32_write(VDEC_VRTPOS, 0x6); + } else + pr_debug("Error not support video mode\n"); + + /* set H Position */ + reg32_write(VDEC_HZPOS, 0x60); + + /* set H ignore start */ + reg32_write(VDEC_HSIGS, 0xf8); + + /* set H ignore end */ + reg32_write(VDEC_HSIGE, 0x18); +} + +/* +* vdec_init() +* Initialises the VDEC registers +* Returns: nothing +*/ +static void vdec_init(struct vadc_data *vadc) +{ + v4l2_std_id std; + + pr_debug("%s\n", __func__); + + /* Get work mode PAL or NTSC */ + vadc_get_std(vadc, &std); + + vdec_mode_timing_init(std); + + /* vcr detect threshold high, automatic detections */ + reg32_write(VDEC_VSCON2, 0); + + reg32_write(VDEC_BASE + 0x110, 0x01); + + /* set the noramp mode on the Hloop PLL. */ + reg32_write(VDEC_BASE+(0x14*4), 0x10); + + /* set the YC relative delay.*/ + reg32_write(VDEC_YCDEL, 0x90); + + /* setup the Hpll */ + reg32_write(VDEC_BASE+(0x13*4), 0x13); + + /* setup the 2d comb */ + /* set the gain of the Hdetail output to 3 + * set the notch alpha gain to 1 */ + reg32_write(VDEC_CFC2, 0x34); + + /* setup various 2d comb bits.*/ + reg32_write(VDEC_BASE+(0x02*4), 0x01); + reg32_write(VDEC_BASE+(0x03*4), 0x18); + reg32_write(VDEC_BASE+(0x04*4), 0x34); + + /* set the start of the burst gate */ + reg32_write(VDEC_BRSTGT, 0x30); + + /* set 1f motion gain */ + reg32_write(VDEC_BASE+(0x0f*4), 0x20); + + /* set the 1F chroma motion detector thresh for colour reverse detection */ + reg32_write(VDEC_THSH1, 0x02); + reg32_write(VDEC_BASE+(0x4a*4), 0x20); + reg32_write(VDEC_BASE+(0x4b*4), 0x08); + + reg32_write(VDEC_BASE+(0x4c*4), 0x08); + + /* set the threshold for the narrow/wide adaptive chroma BW */ + reg32_write(VDEC_BASE+(0x20*4), 0x20); + + /* turn up the colour with the new colour gain reg */ + /* hue: */ + reg32_write(VDEC_HUE, 0x00); + + /* cbgain: 22 B4 */ + reg32_write(VDEC_CBGN, 0xb4); + /* cr gain 80 */ + reg32_write(VDEC_CRGN, 0x80); + /* luma gain (contrast) */ + reg32_write(VDEC_CNTR, 0x80); + + /* setup the signed black level register, brightness */ + reg32_write(VDEC_BRT, 0x00); + + /* filter the standard detection + * enable the comb for the ntsc443 */ + reg32_write(VDEC_STDDBG, 0x23); + + /* setup chroma kill thresh for no chroma */ + reg32_write(VDEC_CHBTH, 0x0); + + /* set chroma loop to wider BW + * no set it to normal BW. i fixed the bw problem.*/ + reg32_write(VDEC_YCDEL, 0x00); + + /* set the compensation in the chroma loop for the Hloop + * set the ratio for the nonarithmetic 3d comb modes.*/ + reg32_write(VDEC_BASE + (0x1d*4), 0x90); + + /* set the threshold for the nonarithmetic mode for the 2d comb + * the higher the value the more Fc Fh offset we will tolerate before turning off the comb. */ + reg32_write(VDEC_BASE + (0x33*4), 0xa0); + + /* setup the bluescreen output colour */ + reg32_write(VDEC_BASE + (0x3d*4), 35); + reg32_write(VDEC_BLSCRCR, 114); + reg32_write(VDEC_BLSCRCB, 212); + + /* disable the active blanking */ + reg32_write(VDEC_BASE + (0x15*4), 0x02); + + /* setup the luma agc for automatic gain. */ + reg32_write(VDEC_LMAGC2, 0x5e); + reg32_write(VDEC_BASE + (0x40*4), 0x81); + + /* setup chroma agc */ + reg32_write(VDEC_CHAGC2, 0x09); + reg32_write(VDEC_BASE + (0x43*4), 0xa0); + + /* setup the MV thresh lower nibble + * setup the sync top cap, upper nibble */ + reg32_write(VDEC_BASE + (0x3a*4), 0x80); + reg32_write(VDEC_SHPIMP, 0x00); + + /* enable div by 4 on out for 10 bit output + * enable vga progressive output. */ + reg32_write(VDEC_BASE + (0xf3*4), 0x0c); + + /* set for 11 bit intput + * also enable dc offset integrator to go on every clock. */ + reg32_write(VDEC_BASE + (0xf4*4), 0x10); + + /* setup the vsync block */ + reg32_write(VDEC_VSCON1, 0x87); + + /* set the nosignal threshold + * set the vsync threshold */ + reg32_write(VDEC_VSSGTH, 0x35); + + /* set length for min hphase filter (or saturate limit if saturate is chosen) */ + reg32_write(VDEC_BASE + (0x45*4), 0x40); + + /* choose the internal 66Mhz clock */ + reg32_write(VDEC_BASE + (0xf8*4), 0x01); + + /* enable the internal resampler, + * select min filter not saturate for hphase noise filter for vcr detect. + * enable vcr pause mode different field lengths */ + reg32_write(VDEC_BASE + (0x46*4), 0x90); + + /* disable VCR detection, lock to the Hsync rather than the Vsync */ + reg32_write(VDEC_VSCON2, 0x04); + + /* set tiplevel goal for dc clamp. */ + reg32_write(VDEC_BASE + (0x3c*4), 0xB0); + + /* override SECAM detection and force SECAM off */ + reg32_write(VDEC_BASE + (0x2f*4), 0x20); + + /* Set r3d_hardblend in 3D control2 reg */ + reg32_write(VDEC_BASE + (0x0c*4), 0x04); +} + +/* set Input selector & input pull-downs */ +static void vadc_select_input(int vadc_in) +{ + switch (vadc_in) { + case 0: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x1e); + break; + case 1: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x2d); + break; + case 2: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x4b); + break; + case 3: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x87); + break; + default: + pr_debug("error video input %d\n", vadc_in); + } +} + + +static void vadc_power_up(struct vadc_data *vadc) +{ + /* Power on vadc analog */ + reg32clrbit(gpc_regbase + GPC_CNTR, 17); + + /* Power down vadc ext power */ + reg32clrbit(gpc_regbase + GPC_CNTR, 18); + + /* software reset afe */ + regmap_update_bits(vadc->gpr, IOMUXC_GPR1, + IMX6SX_GPR1_VADC_SW_RST_MASK, + IMX6SX_GPR1_VADC_SW_RST_RESET); + + msleep(10); + + /* clock config for vadc */ + reg32_write(VDEC_BASE + 0x320, 0xe3); + reg32_write(VDEC_BASE + 0x324, 0x38); + reg32_write(VDEC_BASE + 0x328, 0x8e); + reg32_write(VDEC_BASE + 0x32c, 0x23); + + /* Release reset bit */ + regmap_update_bits(vadc->gpr, IOMUXC_GPR1, + IMX6SX_GPR1_VADC_SW_RST_MASK, + IMX6SX_GPR1_VADC_SW_RST_RELEASE); + + /* Power on vadc ext power */ + reg32setbit(gpc_regbase + GPC_CNTR, 18); +} + +static void vadc_init(struct vadc_data *vadc) +{ + pr_debug("%s\n", __func__); + + vadc_power_up(vadc); + + afe_init(); + + /* select Video Input 0-3 */ + vadc_select_input(vadc->vadc_in); + + afe_voltage_clampingmode(); + + vdec_init(vadc); + + /* + * current control loop will move sinewave input off below + * the bottom of the signal range visible when the testbus is viewed as magnitude, + * so have to break before this point while capturing ENOB data: + */ + afe_alwayson_clampingmode(); +} + +/*! + * Return attributes of current video standard. + * Since this device autodetects the current standard, this function also + * sets the values that need to be changed if the standard changes. + * There is no set std equivalent function. + * + * @return None. + */ +static void vadc_get_std(struct vadc_data *vadc, v4l2_std_id *std) +{ + int tmp; + int idx; + + pr_debug("In vadc_get_std\n"); + + /* Read PAL mode detected result */ + tmp = reg32_read(VDEC_VIDMOD); + tmp &= (VDEC_VIDMOD_PAL_MASK | VDEC_VIDMOD_M625_MASK); + + if (tmp) { + *std = V4L2_STD_PAL; + idx = VADC_PAL; + } else { + *std = V4L2_STD_NTSC; + idx = VADC_NTSC; + } + + /* This assumes autodetect which this device uses. */ + if (*std != vadc->std_id) { + video_idx = idx; + vadc->std_id = *std; + vadc->sen.pix.width = video_fmts[video_idx].raw_width; + vadc->sen.pix.height = video_fmts[video_idx].raw_height; + } +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + pr_debug("ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -EINVAL; + } + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + int ret = 0; + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + pr_debug("In vadc:ioctl_s_parm\n"); + + switch (a->type) { + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + break; + } + + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct vadc_data *vadc = s->priv; + v4l2_std_id std; + + pr_debug("vadc:ioctl_g_fmt_cap\n"); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" Returning size of %dx%d\n", + vadc->sen.pix.width, vadc->sen.pix.height); + f->fmt.pix = vadc->sen.pix; + break; + + case V4L2_BUF_TYPE_PRIVATE: + vadc_get_std(vadc, &std); + f->fmt.pix.pixelformat = (u32)std; + break; + default: + f->fmt.pix = vadc->sen.pix; + break; + } + return 0; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + struct vadc_data *vadc = s->priv; + int ret = 0; + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = vadc->sen.brightness; + break; + case V4L2_CID_HUE: + vc->value = vadc->sen.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = vadc->sen.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = vadc->sen.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = vadc->sen.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = vadc->sen.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = vadc->sen.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In vadc:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + break; + case V4L2_CID_CONTRAST: + break; + case V4L2_CID_SATURATION: + break; + case V4L2_CID_HUE: + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + break; + case V4L2_CID_DO_WHITE_BALANCE: + break; + case V4L2_CID_RED_BALANCE: + break; + case V4L2_CID_BLUE_BALANCE: + break; + case V4L2_CID_GAMMA: + break; + case V4L2_CID_EXPOSURE: + break; + case V4L2_CID_AUTOGAIN: + break; + case V4L2_CID_GAIN: + break; + case V4L2_CID_HFLIP: + break; + case V4L2_CID_VFLIP: + break; + default: + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->index >= 1) + return -EINVAL; + + fsize->discrete.width = video_fmts[video_idx].active_width; + fsize->discrete.height = video_fmts[video_idx].active_height; + + return 0; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "vadc_camera"); + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + return 0; +} + +/*! + * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT + * @s: pointer to standard V4L2 device structure + * @fmt: pointer to standard V4L2 fmt description structure + * + * Return 0. + */ + +static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, + struct v4l2_fmtdesc *fmt) +{ + struct vadc_data *vadc = s->priv; + + /* support only one format */ + if (fmt->index > 0) + return -EINVAL; + + fmt->pixelformat = vadc->sen.pix.pixelformat; + return 0; +} + + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct vadc_data *vadc = s->priv; + + vadc_init(vadc); + + return 0; +} + +/*! + * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num + * @s: pointer to standard V4L2 device structure + * + * Delinitialise the device when slave detaches to the master. + */ +static int ioctl_dev_exit(struct v4l2_int_device *s) +{ + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc vadc_ioctl_desc[] = { + { vidioc_int_dev_init_num, + (v4l2_int_ioctl_func *)ioctl_dev_init }, + { vidioc_int_dev_exit_num, + ioctl_dev_exit}, + { vidioc_int_g_ifparm_num, + (v4l2_int_ioctl_func *)ioctl_g_ifparm }, + { vidioc_int_init_num, + (v4l2_int_ioctl_func *)ioctl_init }, + { vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap }, + { vidioc_int_g_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_g_fmt_cap }, + { vidioc_int_g_parm_num, + (v4l2_int_ioctl_func *)ioctl_g_parm }, + { vidioc_int_s_parm_num, + (v4l2_int_ioctl_func *)ioctl_s_parm }, + { vidioc_int_g_ctrl_num, + (v4l2_int_ioctl_func *)ioctl_g_ctrl }, + { vidioc_int_s_ctrl_num, + (v4l2_int_ioctl_func *)ioctl_s_ctrl }, + { vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *)ioctl_enum_framesizes }, + { vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *)ioctl_g_chip_ident }, +}; + +static struct v4l2_int_slave vadc_slave = { + .ioctls = vadc_ioctl_desc, + .num_ioctls = ARRAY_SIZE(vadc_ioctl_desc), +}; + +static const struct of_device_id fsl_vadc_dt_ids[] = { + { .compatible = "fsl,imx6sx-vadc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_vadc_dt_ids); + +static struct v4l2_int_device vadc_int_device = { + .module = THIS_MODULE, + .name = "vadc", + .type = v4l2_int_type_slave, + .u = { + .slave = &vadc_slave, + }, +}; + +static int vadc_probe(struct platform_device *pdev) +{ + struct vadc_data *vadc; + struct device_node *np = pdev->dev.of_node; + struct device_node *gpc_np; + struct resource *res; + u32 csi_id; + int ret = -1; + + vadc = devm_kzalloc(&pdev->dev, sizeof(struct vadc_data), GFP_KERNEL); + if (!vadc) { + dev_err(&pdev->dev, "Cannot allocate device data\n"); + return -ENOMEM; + } + + /* Set initial values for the sensor struct. */ + vadc->sen.streamcap.timeperframe.denominator = 30; + vadc->sen.streamcap.timeperframe.numerator = 1; + vadc->std_id = V4L2_STD_ALL; + video_idx = VADC_NTSC; + vadc->sen.pix.width = video_fmts[video_idx].raw_width; + vadc->sen.pix.height = video_fmts[video_idx].raw_height; + vadc->sen.pix.pixelformat = V4L2_PIX_FMT_YUV444; /* YUV444 */ + vadc->sen.pix.priv = 1; /* 1 is used to indicate TV in */ + vadc->sen.on = true; + + /* map vafe address */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, VAFE_REGS_ADDR_RES_NAME); + if (!res) { + dev_err(&pdev->dev, "No vafe base address found.\n"); + return -ENOMEM; + } + vafe_regbase = devm_ioremap_resource(&pdev->dev, res); + if (!vafe_regbase) { + dev_err(&pdev->dev, "ioremap failed with vafe base\n"); + return -ENOMEM; + } + + /* map vdec address */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, VDEC_REGS_ADDR_RES_NAME); + if (!res) { + dev_err(&pdev->dev, "No vdec base address found.\n"); + return -ENODEV; + } + vdec_regbase = devm_ioremap_resource(&pdev->dev, res); + if (!vdec_regbase) { + dev_err(&pdev->dev, "ioremap failed with vdec base\n"); + return -ENOMEM; + } + + /* Get clock */ + vadc->vadc_clk = devm_clk_get(&pdev->dev, "vadc"); + if (IS_ERR(vadc->vadc_clk)) { + ret = PTR_ERR(vadc->vadc_clk); + return ret; + } + + vadc->sen.sensor_clk = devm_clk_get(&pdev->dev, "csi"); + if (IS_ERR(vadc->sen.sensor_clk)) { + ret = PTR_ERR(vadc->sen.sensor_clk); + return ret; + } + + clk_prepare_enable(vadc->sen.sensor_clk); + clk_prepare_enable(vadc->vadc_clk); + + /* Get csi_id to setting vadc to csi mux in gpr */ + ret = of_property_read_u32(np, "csi_id", &csi_id); + if (ret) { + dev_err(&pdev->dev, "failed to read of property csi_id\n"); + return ret; + } + + /* remap GPR register */ + vadc->gpr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "gpr"); + if (IS_ERR(vadc->gpr)) { + dev_dbg(&pdev->dev, "can not get gpr\n"); + return -ENOMEM; + } + + /* Configuration vadc-to-csi 0 or 1 */ + if (csi_id) { + regmap_update_bits(vadc->gpr, IOMUXC_GPR5, + IMX6SX_GPR5_CSI2_MUX_CTRL_MASK, + IMX6SX_GPR5_CSI2_MUX_CTRL_CVD); + } else { + regmap_update_bits(vadc->gpr, IOMUXC_GPR5, + IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, + IMX6SX_GPR5_CSI1_MUX_CTRL_CVD); + } + + /* Get default vadc_in number */ + ret = of_property_read_u32(np, "vadc_in", &vadc->vadc_in); + if (ret) { + dev_err(&pdev->dev, "failed to read of property vadc_in\n"); + return ret; + } + + /* map GPC register */ + gpc_np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); + gpc_regbase = of_iomap(gpc_np, 0); + if (!gpc_regbase) { + dev_err(&pdev->dev, "ioremap failed with gpc base\n"); + goto error; + } + + platform_set_drvdata(pdev, vadc); + + /* Register vadc as v4l2 slave device */ + vadc_int_device.priv = vadc; + ret = v4l2_int_device_register(&vadc_int_device); + + pr_info("vadc driver loaded\n"); + + return ret; + +error: + iounmap(gpc_regbase); + return ret; +} + +static int vadc_remove(struct platform_device *pdev) +{ + struct vadc_data *vadc = platform_get_drvdata(pdev); + + v4l2_int_device_unregister(&vadc_int_device); + + clk_disable_unprepare(vadc->sen.sensor_clk); + clk_disable_unprepare(vadc->vadc_clk); + + return true; +} + +static struct platform_driver vadc_driver = { + .driver = { + .name = "fsl_vadc", + .of_match_table = of_match_ptr(fsl_vadc_dt_ids), + }, + .probe = vadc_probe, + .remove = vadc_remove, +}; + +module_platform_driver(vadc_driver); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("fsl VADC/VDEC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/mxc/capture/mxc_vadc.h b/drivers/media/platform/mxc/capture/mxc_vadc.h new file mode 100644 index 000000000000..91231be79561 --- /dev/null +++ b/drivers/media/platform/mxc/capture/mxc_vadc.h @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef MXC_VDEC_H +#define MXC_VDEC_H + +/*** define base address ***/ +#define VDEC_BASE vdec_regbase +#define AFE_BASE vafe_regbase + +/* AFE - Register offsets */ +#define AFE_BLOCK_ID_OFFSET 0x00000000 +#define AFE_PDBUF_OFFSET 0x00000004 +#define AFE_SWRST_OFFSET 0x00000008 +#define AFE_TSTSEL_OFFSET 0x0000000c +#define AFE_TSTMSC_OFFSET 0x00000010 +#define AFE_ENPADIO_OFFSET 0x00000014 +#define AFE_BGREG_OFFSET 0x00000018 +#define AFE_ACCESSAR_ID_OFFSET 0x00000400 +#define AFE_PDADC_OFFSET 0x00000404 +#define AFE_PDSARH_OFFSET 0x00000408 +#define AFE_PDSARL_OFFSET 0x0000040C +#define AFE_PDADCRFH_OFFSET 0x00000410 +#define AFE_PDADCRFL_OFFSET 0x00000414 +#define AFE_ACCTST_OFFSET 0x00000418 +#define AFE_ADCGN_OFFSET 0x0000041C +#define AFE_ICTRL_OFFSET 0x00000420 +#define AFE_ICTLSTG_OFFSET 0x00000424 +#define AFE_RCTRLSTG_OFFSET 0x00000428 +#define AFE_TCTRLSTG_OFFSET 0x0000042c +#define AFE_REFMOD_OFFSET 0x00000430 +#define AFE_REFTRIML_OFFSET 0x00000434 +#define AFE_REFTRIMH_OFFSET 0x00000438 +#define AFE_ADCR_OFFSET 0x0000043c +#define AFE_DUMMY0_OFFSET 0x00000440 +#define AFE_DUMMY1_OFFSET 0x00000444 +#define AFE_DUMMY2_OFFSET 0x00000448 +#define AFE_DACAMP_OFFSET 0x0000044c +#define AFE_CLMPTST_OFFSET 0x00000450 +#define AFE_CLMPDAT_OFFSET 0x00000454 +#define AFE_CLMPAMP_OFFSET 0x00000458 +#define AFE_CLAMP_OFFSET 0x0000045c +#define AFE_INPBUF_OFFSET 0x00000460 +#define AFE_INPFLT_OFFSET 0x00000464 +#define AFE_ADCDGN_OFFSET 0x00000468 +#define AFE_OFFDRV_OFFSET 0x0000046c +#define AFE_INPCONFIG_OFFSET 0x00000470 +#define AFE_PROGDELAY_OFFSET 0x00000474 +#define AFE_ADCOMT_OFFSET 0x00000478 +#define AFE_ALGDELAY_OFFSET 0x0000047c +#define AFE_ACC_ID_OFFSET 0x00000800 +#define AFE_ACCSTA_OFFSET 0x00000804 +#define AFE_ACCNOSLI_OFFSET 0x00000808 +#define AFE_ACCCALCON_OFFSET 0x0000080c +#define AFE_BWEWRICTRL_OFFSET 0x00000810 +#define AFE_SELSLI_OFFSET 0x00000814 +#define AFE_SELBYT_OFFSET 0x00000818 +#define AFE_REDVAL_OFFSET 0x00000820 +#define AFE_WRIBYT_OFFSET 0x00000824 + +/* AFE Register per module */ +#define AFE_BLOCK_ID (AFE_BASE + AFE_BLOCK_ID_OFFSET) +#define AFE_PDBUF (AFE_BASE + AFE_PDBUF_OFFSET) +#define AFE_SWRST (AFE_BASE + AFE_SWRST_OFFSET) +#define AFE_TSTSEL (AFE_BASE + AFE_TSTSEL_OFFSET) +#define AFE_TSTMSC (AFE_BASE + AFE_TSTMSC_OFFSET) +#define AFE_ENPADIO (AFE_BASE + AFE_ENPADIO_OFFSET) +#define AFE_BGREG (AFE_BASE + AFE_BGREG_OFFSET) +#define AFE_ACCESSAR_ID (AFE_BASE + AFE_ACCESSAR_ID_OFFSET) +#define AFE_PDADC (AFE_BASE + AFE_PDADC_OFFSET) +#define AFE_PDSARH (AFE_BASE + AFE_PDSARH_OFFSET) +#define AFE_PDSARL (AFE_BASE + AFE_PDSARL_OFFSET) +#define AFE_PDADCRFH (AFE_BASE + AFE_PDADCRFH_OFFSET) +#define AFE_PDADCRFL (AFE_BASE + AFE_PDADCRFL_OFFSET) +#define AFE_ACCTST (AFE_BASE + AFE_ACCTST_OFFSET) +#define AFE_ADCGN (AFE_BASE + AFE_ADCGN_OFFSET) +#define AFE_ICTRL (AFE_BASE + AFE_ICTRL_OFFSET) +#define AFE_ICTLSTG (AFE_BASE + AFE_ICTLSTG_OFFSET) +#define AFE_RCTRLSTG (AFE_BASE + AFE_RCTRLSTG_OFFSET) +#define AFE_TCTRLSTG (AFE_BASE + AFE_TCTRLSTG_OFFSET) +#define AFE_REFMOD (AFE_BASE + AFE_REFMOD_OFFSET) +#define AFE_REFTRIML (AFE_BASE + AFE_REFTRIML_OFFSET) +#define AFE_REFTRIMH (AFE_BASE + AFE_REFTRIMH_OFFSET) +#define AFE_ADCR (AFE_BASE + AFE_ADCR_OFFSET) +#define AFE_DUMMY0 (AFE_BASE + AFE_DUMMY0_OFFSET) +#define AFE_DUMMY1 (AFE_BASE + AFE_DUMMY1_OFFSET) +#define AFE_DUMMY2 (AFE_BASE + AFE_DUMMY2_OFFSET) +#define AFE_DACAMP (AFE_BASE + AFE_DACAMP_OFFSET) +#define AFE_CLMPTST (AFE_BASE + AFE_CLMPTST_OFFSET) +#define AFE_CLMPDAT (AFE_BASE + AFE_CLMPDAT_OFFSET) +#define AFE_CLMPAMP (AFE_BASE + AFE_CLMPAMP_OFFSET) +#define AFE_CLAMP (AFE_BASE + AFE_CLAMP_OFFSET) +#define AFE_INPBUF (AFE_BASE + AFE_INPBUF_OFFSET) +#define AFE_INPFLT (AFE_BASE + AFE_INPFLT_OFFSET) +#define AFE_ADCDGN (AFE_BASE + AFE_ADCDGN_OFFSET) +#define AFE_OFFDRV (AFE_BASE + AFE_OFFDRV_OFFSET) +#define AFE_INPCONFIG (AFE_BASE + AFE_INPCONFIG_OFFSET) +#define AFE_PROGDELAY (AFE_BASE + AFE_PROGDELAY_OFFSET) +#define AFE_ADCOMT (AFE_BASE + AFE_ADCOMT_OFFSET) +#define AFE_ALGDELAY (AFE_BASE + AFE_ALGDELAY_OFFSET) +#define AFE_ACC_ID (AFE_BASE + AFE_ACC_ID_OFFSET) +#define AFE_ACCSTA (AFE_BASE + AFE_ACCSTA_OFFSET) +#define AFE_ACCNOSLI (AFE_BASE + AFE_ACCNOSLI_OFFSET) +#define AFE_ACCCALCON (AFE_BASE + AFE_ACCCALCON_OFFSET) +#define AFE_BWEWRICTRL (AFE_BASE + AFE_BWEWRICTRL_OFFSET) +#define AFE_SELSLI (AFE_BASE + AFE_SELSLI_OFFSET) +#define AFE_SELBYT (AFE_BASE + AFE_SELBYT_OFFSET) +#define AFE_REDVAL (AFE_BASE + AFE_REDVAL_OFFSET) +#define AFE_WRIBYT (AFE_BASE + AFE_WRIBYT_OFFSET) + +/* VDEC - Register offsets */ +#define VDEC_CFC1_OFFSET 0x00000000 +#define VDEC_CFC2_OFFSET 0x00000004 +#define VDEC_BRSTGT_OFFSET 0x00000024 +#define VDEC_HZPOS_OFFSET 0x00000040 +#define VDEC_VRTPOS_OFFSET 0x00000044 +#define VDEC_HVSHIFT_OFFSET 0x00000054 +#define VDEC_HSIGS_OFFSET 0x00000058 +#define VDEC_HSIGE_OFFSET 0x0000005C +#define VDEC_VSCON1_OFFSET 0x00000060 +#define VDEC_VSCON2_OFFSET 0x00000064 +#define VDEC_YCDEL_OFFSET 0x0000006C +#define VDEC_AFTCLP_OFFSET 0x00000070 +#define VDEC_DCOFF_OFFSET 0x00000078 +#define VDEC_CSID_OFFSET 0x00000084 +#define VDEC_CBGN_OFFSET 0x00000088 +#define VDEC_CRGN_OFFSET 0x0000008C +#define VDEC_CNTR_OFFSET 0x00000090 +#define VDEC_BRT_OFFSET 0x00000094 +#define VDEC_HUE_OFFSET 0x00000098 +#define VDEC_CHBTH_OFFSET 0x0000009C +#define VDEC_SHPIMP_OFFSET 0x000000A4 +#define VDEC_CHPLLIM_OFFSET 0x000000A8 +#define VDEC_VIDMOD_OFFSET 0x000000AC +#define VDEC_VIDSTS_OFFSET 0x000000B0 +#define VDEC_NOISE_OFFSET 0x000000B4 +#define VDEC_STDDBG_OFFSET 0x000000B8 +#define VDEC_MANOVR_OFFSET 0x000000BC +#define VDEC_VSSGTH_OFFSET 0x000000C8 +#define VDEC_DBGFBH_OFFSET 0x000000D0 +#define VDEC_DBGFBL_OFFSET 0x000000D4 +#define VDEC_HACTS_OFFSET 0x000000D8 +#define VDEC_HACTE_OFFSET 0x000000DC +#define VDEC_VACTS_OFFSET 0x000000E0 +#define VDEC_VACTE_OFFSET 0x000000E4 +#define VDEC_HSTIP_OFFSET 0x000000EC +#define VDEC_BLSCRY_OFFSET 0x000000F4 +#define VDEC_BLSCRCR_OFFSET 0x000000F8 +#define VDEC_BLSCRCB_OFFSET 0x000000FC +#define VDEC_LMAGC2_OFFSET 0x00000104 +#define VDEC_CHAGC2_OFFSET 0x0000010C +#define VDEC_MINTH_OFFSET 0x00000114 +#define VDEC_VFRQOH_OFFSET 0x0000011C +#define VDEC_VFRQOL_OFFSET 0x00000120 +#define VDEC_THSH1_OFFSET 0x00000124 +#define VDEC_THSH2_OFFSET 0x00000128 +#define VDEC_NCHTH_OFFSET 0x0000012C +#define VDEC_TH1F_OFFSET 0x00000130 + +/* VDEC Register per module */ +#define VDEC_CFC1 (VDEC_BASE + VDEC_CFC1_OFFSET) +#define VDEC_CFC2 (VDEC_BASE + VDEC_CFC2_OFFSET) +#define VDEC_BRSTGT (VDEC_BASE + VDEC_BRSTGT_OFFSET) +#define VDEC_HZPOS (VDEC_BASE + VDEC_HZPOS_OFFSET) +#define VDEC_VRTPOS (VDEC_BASE + VDEC_VRTPOS_OFFSET) +#define VDEC_HVSHIFT (VDEC_BASE + VDEC_HVSHIFT_OFFSET) +#define VDEC_HSIGS (VDEC_BASE + VDEC_HSIGS_OFFSET) +#define VDEC_HSIGE (VDEC_BASE + VDEC_HSIGE_OFFSET) +#define VDEC_VSCON1 (VDEC_BASE + VDEC_VSCON1_OFFSET) +#define VDEC_VSCON2 (VDEC_BASE + VDEC_VSCON2_OFFSET) +#define VDEC_YCDEL (VDEC_BASE + VDEC_YCDEL_OFFSET) +#define VDEC_AFTCLP (VDEC_BASE + VDEC_AFTCLP_OFFSET) +#define VDEC_DCOFF (VDEC_BASE + VDEC_DCOFF_OFFSET) +#define VDEC_CSID (VDEC_BASE + VDEC_CSID_OFFSET) +#define VDEC_CBGN (VDEC_BASE + VDEC_CBGN_OFFSET) +#define VDEC_CRGN (VDEC_BASE + VDEC_CRGN_OFFSET) +#define VDEC_CNTR (VDEC_BASE + VDEC_CNTR_OFFSET) +#define VDEC_BRT (VDEC_BASE + VDEC_BRT_OFFSET) +#define VDEC_HUE (VDEC_BASE + VDEC_HUE_OFFSET) +#define VDEC_CHBTH (VDEC_BASE + VDEC_CHBTH_OFFSET) +#define VDEC_SHPIMP (VDEC_BASE + VDEC_SHPIMP_OFFSET) +#define VDEC_CHPLLIM (VDEC_BASE + VDEC_CHPLLIM_OFFSET) +#define VDEC_VIDMOD (VDEC_BASE + VDEC_VIDMOD_OFFSET) +#define VDEC_VIDSTS (VDEC_BASE + VDEC_VIDSTS_OFFSET) +#define VDEC_NOISE (VDEC_BASE + VDEC_NOISE_OFFSET) +#define VDEC_STDDBG (VDEC_BASE + VDEC_STDDBG_OFFSET) +#define VDEC_MANOVR (VDEC_BASE + VDEC_MANOVR_OFFSET) +#define VDEC_VSSGTH (VDEC_BASE + VDEC_VSSGTH_OFFSET) +#define VDEC_DBGFBH (VDEC_BASE + VDEC_DBGFBH_OFFSET) +#define VDEC_DBGFBL (VDEC_BASE + VDEC_DBGFBL_OFFSET) +#define VDEC_HACTS (VDEC_BASE + VDEC_HACTS_OFFSET) +#define VDEC_HACTE (VDEC_BASE + VDEC_HACTE_OFFSET) +#define VDEC_VACTS (VDEC_BASE + VDEC_VACTS_OFFSET) +#define VDEC_VACTE (VDEC_BASE + VDEC_VACTE_OFFSET) +#define VDEC_HSTIP (VDEC_BASE + VDEC_HSTIP_OFFSET) +#define VDEC_BLSCRY (VDEC_BASE + VDEC_BLSCRY_OFFSET) +#define VDEC_BLSCRCR (VDEC_BASE + VDEC_BLSCRCR_OFFSET) +#define VDEC_BLSCRCB (VDEC_BASE + VDEC_BLSCRCB_OFFSET) +#define VDEC_LMAGC2 (VDEC_BASE + VDEC_LMAGC2_OFFSET) +#define VDEC_CHAGC2 (VDEC_BASE + VDEC_CHAGC2_OFFSET) +#define VDEC_MINTH (VDEC_BASE + VDEC_MINTH_OFFSET) +#define VDEC_VFRQOH (VDEC_BASE + VDEC_VFRQOH_OFFSET) +#define VDEC_VFRQOL (VDEC_BASE + VDEC_VFRQOL_OFFSET) +#define VDEC_THSH1 (VDEC_BASE + VDEC_THSH1_OFFSET) +#define VDEC_THSH2 (VDEC_BASE + VDEC_THSH2_OFFSET) +#define VDEC_NCHTH (VDEC_BASE + VDEC_NCHTH_OFFSET) +#define VDEC_TH1F (VDEC_BASE + VDEC_TH1F_OFFSET) + +#define VDEC_VIDMOD_M625_SHIFT 4 +#define VDEC_VIDMOD_M625_MASK (1 << VDEC_VIDMOD_M625_SHIFT) + +#define VDEC_VIDMOD_PAL_SHIFT 7 +#define VDEC_VIDMOD_PAL_MASK (1 << VDEC_VIDMOD_PAL_SHIFT) +/*** define base address ***/ + +#endif -- 2.34.1