drm/i915/skl: disable display side power well support for now
authorImre Deak <imre.deak@intel.com>
Thu, 5 Nov 2015 21:04:11 +0000 (23:04 +0200)
committerJani Nikula <jani.nikula@intel.com>
Fri, 6 Nov 2015 12:46:05 +0000 (14:46 +0200)
commit1b0e3a049efe471c399674fd954500ce97438d30
treed213cb6a9d966aba2cc3f6699739f999428c01b1
parentb291681926a142958112eedde62823230d6afb84
drm/i915/skl: disable display side power well support for now

The display power well support on this platform is in a somewhat broken
state atm, so disable it by default.

This in effect will get rid of incorrect assert WARNs about the CSR/DMC
firmware not being loaded during power well toggling. It also removes a
problem during driver loading where a register is accessed while its
backing power well is down, resulting in another WARN. Until we come up
with the root cause of the second problem and the proper fix for both
issues, keep all display side power wells on.

Also clarify a bit the option description.

Reported-by: Dave Airlie <airlied@redhat.com>
Reference: http://mid.gmane.org/CAPM=9tyjBQjSBTKa49cRr6SYkpNW7Pq-fUFznZZ8Y1snvvk7mA@mail.gmail.com
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446757451-2777-1-git-send-email-imre.deak@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/i915_params.c
drivers/gpu/drm/i915/intel_runtime_pm.c