ARM926 (MX27) D-cache writethrough bug fix.

Patch for ARM926 (MX27) D-cache writethrough bug fix.
Source: linux-arm-kernel list, posted by Gilles Maigne on 11/17/06.

Text from e-mail posting:

arm926_dma_flush_range write the content of dcache in memory when linux
is configured with CONFIG_CPU_DCACHE_WRITETHROUGH ( cache in
write-through) and does not invalidate the virtual address range.
This is wrong for two reasons :
1/ the cache line does not need to be written because the cache is
write-through
2/ the cache line is not invalidated, so next read at this address may
come from the cache, which is wrong because main memory may contain
valid data resulting of a DMA transaction.
This patch applies to linux 2.6.18

http://www.bitshrine.org/gpp/linux-2.6.19.2-mx-arm926_dcache_writethrough_flush_fix.patch

http://www.bitshrine.org/gpp/linux-2.6.22-mx-ARM926-MX27-D-cache-writethrough-bug-fix.patch

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 5b80b6bdd0cb3676a65e7d6b7f211c2a2e7f1ce9..18d783205c15990fbfe0ff3e46ea3a0a8886c31f 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -291,7 +291,7 @@ ENTRY(arm926_dma_flush_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
        mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 #else
-       mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+       mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 #endif
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1