ARM: proc: add Cortex-A5 proc info

This patch adds processor info for ARM Ltd. Cortex A5,
which has SCU initialisation procedure identical to A9.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 15eb169bfec291faf25b158cfa9842b72f7803ad)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6f9013373a98a4e8a02ec4c95483dff194e90587..18d91a8229ad4f4c62786a814ca21beaa0902585 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -279,6 +279,7 @@ cpu_resume_l1_flags:
  *     It is assumed that:
  *     - cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
        ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
@@ -464,6 +465,16 @@ cpu_elf_name:
        .long   v7_cache_fns
 .endm
 
+       /*
+        * ARM Ltd. Cortex A5 processor.
+        */
+       .type   __v7_ca5mp_proc_info, #object
+__v7_ca5mp_proc_info:
+       .long   0x410fc050
+       .long   0xff0ffff0
+       __v7_proc __v7_ca5mp_setup
+       .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
+
        /*
         * ARM Ltd. Cortex A9 processor.
         */