ARM: tegra: roth: Mask HS200 mode support

Mask HS200 mode support for sdmmc4.

In DDR50 mode for eMMC can support max clock of 52MHz. For Tegra sdmmc
controllers, the host clock in ddr mode should be double that of the
eMMC device. Taking into consideration the dvfs tables, limiting ddr
mode clock to 51MHz to allow for lower core voltages to set even when
sdmmc4 clock is ON.

Bug 1287739

Change-Id: Ib04dce91d771ab5505dd67ea3a8d5c704d0b499e
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
(cherry picked from commit 3db4b21d8d5eb5a99dbcd3d660478a3a89ced104)
Reviewed-on: http://git-master/r/230048
Reviewed-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Matt Wagner <mwagner@nvidia.com>
GVS: Gerrit_Virtual_Submit

diff --git a/arch/arm/mach-tegra/board-roth-sdhci.c b/arch/arm/mach-tegra/board-roth-sdhci.c
index 8af2da70684bf015536db9d67cd7c6f7a95eefa3..6c26cb3c760767253708210710c5f627f8f52e09 100644 (file)
--- a/arch/arm/mach-tegra/board-roth-sdhci.c
+++ b/arch/arm/mach-tegra/board-roth-sdhci.c
@@ -170,12 +170,13 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .is_8bit = 1,
        .tap_delay = 0x5,
        .trim_delay = 0xA,
-       .ddr_clk_limit = 41000000,
+       .ddr_clk_limit = 51000000,
        .max_clk_limit = 156000000,
        .mmc_data = {
                .built_in = 1,
                .ocr_mask = MMC_OCR_1V8_MASK,
-       }
+       },
+       .uhs_mask = MMC_MASK_HS200,
 };
 
 static struct platform_device tegra_sdhci_device0 = {