skl_dpll0_update(dev_priv, cdclk_state);
- cdclk_state->cdclk = cdclk_state->ref;
+ cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
if (cdclk_state->vco == 0)
goto out;
/* Choose frequency for this cdclk */
switch (cdclk) {
default:
- WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+ WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
WARN_ON(vco != 0);
/* fall through */
case 308571:
/* Is PLL enabled and locked ? */
if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+ dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
{
struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
- cdclk_state.cdclk = cdclk_state.ref;
+ cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
{
int ratio;
- if (cdclk == dev_priv->cdclk.hw.ref)
+ if (cdclk == dev_priv->cdclk.hw.bypass)
return 0;
switch (cdclk) {
{
int ratio;
- if (cdclk == dev_priv->cdclk.hw.ref)
+ if (cdclk == dev_priv->cdclk.hw.bypass)
return 0;
switch (cdclk) {
bxt_de_pll_update(dev_priv, cdclk_state);
- cdclk_state->cdclk = cdclk_state->ref;
+ cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
if (cdclk_state->vco == 0)
goto out;
/* cdclk = vco / 2 / div{1,1.5,2,4} */
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
default:
- WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+ WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
WARN_ON(vco != 0);
/* fall through */
case 2:
intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+ dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
{
struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
- cdclk_state.cdclk = cdclk_state.ref;
+ cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
cnl_cdclk_pll_update(dev_priv, cdclk_state);
- cdclk_state->cdclk = cdclk_state->ref;
+ cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
if (cdclk_state->vco == 0)
goto out;
/* cdclk = vco / 2 / div{1,2} */
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
default:
- WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
+ WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
WARN_ON(vco != 0);
/* fall through */
case 2:
{
int ratio;
- if (cdclk == dev_priv->cdclk.hw.ref)
+ if (cdclk == dev_priv->cdclk.hw.bypass)
return 0;
switch (cdclk) {
intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
+ dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
{
struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
- cdclk_state.cdclk = cdclk_state.ref;
+ cdclk_state.cdclk = cdclk_state.bypass;
cdclk_state.vco = 0;
cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
const char *context)
{
- DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, voltage level %d\n",
+ DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
context, cdclk_state->cdclk, cdclk_state->vco,
- cdclk_state->ref, cdclk_state->voltage_level);
+ cdclk_state->ref, cdclk_state->bypass,
+ cdclk_state->voltage_level);
}
/**