ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Fri, 22 Sep 2017 16:49:11 +0000 (19:49 +0300)
committerVineet Gupta <vgupta@synopsys.com>
Fri, 6 Oct 2017 15:59:54 +0000 (08:59 -0700)
DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/boot/dts/hsdk.dts
arch/arc/configs/hsdk_defconfig

index b922f3faf5549ddf65cf7f1974f72b260d6a2a08..8adde1b492f14e833279ff75f448b7c0bb350781 100644 (file)
@@ -12,6 +12,7 @@
 /dts-v1/;
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/reset/snps,hsdk-reset.h>
 
 / {
        model = "snps,hsdk";
 
                ranges = <0x00000000 0xf0000000 0x10000000>;
 
+               cgu_rst: reset-controller@8a0 {
+                       compatible = "snps,hsdk-reset";
+                       #reset-cells = <1>;
+                       reg = <0x8A0 0x4>, <0xFF0 0x4>;
+               };
+
                core_clk: core-clk@0 {
                        compatible = "snps,hsdk-core-pll-clock";
                        reg = <0x00 0x10>, <0x14B8 0x4>;
                        clocks = <&gmacclk>;
                        clock-names = "stmmaceth";
                        phy-handle = <&phy0>;
+                       resets = <&cgu_rst HSDK_ETH_RESET>;
+                       reset-names = "stmmaceth";
 
                        mdio {
                                #address-cells = <1>;
index 7b8f8faf8a24315d3379d189cab69506539e04a8..15f0f6b5fec1ae6f8e0c1bfb4fa6c970915e1713 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_HSDK=y
 CONFIG_EXT3_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y