ARM: tegra: clocks: init shared clk after sku limit

shared clock rate is dependent on its parent max rate. Parent's max rate
get updated in sku limit init depending on the sku value. Hence initialize
shared clocks after sku limits are applied.

Bug 821534

Change-Id: Ic11631cd54af638c8afa75aceeb4bcd999c8135f
Reviewed-on: http://git-master/r/30504
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index bc3e56bc8f3382620b23b1c880c4bdb8ccd18ab3..fde39dae72d2324d466599f489a89a2c784cb745 100644 (file)
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2082,7 +2082,7 @@ static struct clk tegra_clk_emc = {
                .parent = _parent,                      \
        }
 
-struct clk tegra_list_clks[] = {
+struct clk tegra_list_periph_clks[] = {
        PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      0x31E,  32768,     mux_clk_32k,                 PERIPH_NO_RESET),
        PERIPH_CLK("kbc",       "tegra-kbc",            NULL,   36,     0,      0x31E,  32768,     mux_clk_32k, PERIPH_NO_RESET),
        PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      0x31E,  26000000,  mux_clk_m,                   0),
@@ -2150,7 +2150,9 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("isp",       "tegra_camera",         "isp",  23,     0,      0x31E,  150000000, mux_clk_m,                   0), /* same frequency as VI */
        PERIPH_CLK("csus",      "tegra_camera",         "csus", 92,     0,      0x31E,  150000000, mux_clk_m,                   PERIPH_NO_RESET),
        PERIPH_CLK("stat_mon",  "tegra-stat-mon",       NULL,   37,     0,      0x31E,  26000000,  mux_clk_m,                   0),
+};
 
+struct clk tegra_list_shared_clks[] = {
        SHARED_CLK("avp.sclk",  "tegra-avp",            "sclk", &tegra_clk_virtual_sclk),
        SHARED_CLK("usbd.sclk", "fsl-tegra-udc",        "sclk", &tegra_clk_virtual_sclk),
        SHARED_CLK("usb1.sclk", "tegra-ehci.0",         "sclk", &tegra_clk_virtual_sclk),
@@ -2280,6 +2282,7 @@ static struct tegra_sku_rate_limit sku_limits[] =
        RATE_LIMIT("host1x",    108000000, 0x0F),
 
        RATE_LIMIT("sclk",      300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+       RATE_LIMIT("vsclk",     300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
        RATE_LIMIT("hclk",      300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
        RATE_LIMIT("avp.sclk",  300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
        RATE_LIMIT("vde",       300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
@@ -2328,8 +2331,8 @@ void __init tegra2_init_clocks(void)
        for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
                tegra2_init_one_clock(tegra_ptr_clks[i]);
 
-       for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
-               tegra2_init_one_clock(&tegra_list_clks[i]);
+       for (i = 0; i < ARRAY_SIZE(tegra_list_periph_clks); i++)
+               tegra2_init_one_clock(&tegra_list_periph_clks[i]);
 
        for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
                c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
@@ -2345,6 +2348,9 @@ void __init tegra2_init_clocks(void)
 
        init_audio_sync_clock_mux();
        tegra2_init_sku_limits();
+
+       for (i = 0; i < ARRAY_SIZE(tegra_list_shared_clks); i++)
+               tegra2_init_one_clock(&tegra_list_shared_clks[i]);
 }
 
 #ifdef CONFIG_CPU_FREQ