Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 15 Dec 2014 23:52:01 +0000 (15:52 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 15 Dec 2014 23:52:01 +0000 (15:52 -0800)
Pull drm updates from Dave Airlie:
 "Highlights:

   - AMD KFD driver merge

     This is the AMD HSA interface for exposing a lowlevel interface for
     GPGPU use.  They have an open source userspace built on top of this
     interface, and the code looks as good as it was going to get out of
     tree.

   - Initial atomic modesetting work

     The need for an atomic modesetting interface to allow userspace to
     try and send a complete set of modesetting state to the driver has
     arisen, and been suffering from neglect this past year.  No more,
     the start of the common code and changes for msm driver to use it
     are in this tree.  Ongoing work to get the userspace ioctl finished
     and the code clean will probably wait until next kernel.

   - DisplayID 1.3 and tiled monitor exposed to userspace.

     Tiled monitor property is now exposed for userspace to make use of.

   - Rockchip drm driver merged.

   - imx gpu driver moved out of staging

  Other stuff:

   - core:
        panel - MIPI DSI + new panels.
        expose suggested x/y properties for virtual GPUs

   - i915:
        Initial Skylake (SKL) support
        gen3/4 reset work
        start of dri1/ums removal
        infoframe tracking
        fixes for lots of things.

   - nouveau:
        tegra k1 voltage support
        GM204 modesetting support
        GT21x memory reclocking work

   - radeon:
        CI dpm fixes
        GPUVM improvements
        Initial DPM fan control

   - rcar-du:
        HDMI support added
        removed some support for old boards
        slave encoder driver for Analog Devices adv7511

   - exynos:
        Exynos4415 SoC support

   - msm:
        a4xx gpu support
        atomic helper conversion

   - tegra:
        iommu support
        universal plane support
        ganged-mode DSI support

   - sti:
        HDMI i2c improvements

   - vmwgfx:
        some late fixes.

   - qxl:
        use suggested x/y properties"

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (969 commits)
  drm: sti: fix module compilation issue
  drm/i915: save/restore GMBUS freq across suspend/resume on gen4
  drm: sti: correctly cleanup CRTC and planes
  drm: sti: add HQVDP plane
  drm: sti: add cursor plane
  drm: sti: enable auxiliary CRTC
  drm: sti: fix delay in VTG programming
  drm: sti: prepare sti_tvout to support auxiliary crtc
  drm: sti: use drm_crtc_vblank_{on/off} instead of drm_vblank_{on/off}
  drm: sti: fix hdmi avi infoframe
  drm: sti: remove event lock while disabling vblank
  drm: sti: simplify gdp code
  drm: sti: clear all mixer control
  drm: sti: remove gpio for HDMI hot plug detection
  drm: sti: allow to change hdmi ddc i2c adapter
  drm/doc: Document drm_add_modes_noedid() usage
  drm/i915: Remove '& 0xffff' from the mask given to WA_REG()
  drm/i915: Invert the mask and val arguments in wa_add() and WA_REG()
  drm: Zero out DRM object memory upon cleanup
  drm/i915/bdw: Fix the write setting up the WIZ hashing mode
  ...

24 files changed:
1  2 
Documentation/devicetree/bindings/vendor-prefixes.txt
MAINTAINERS
drivers/gpu/drm/exynos/exynos_drm_drv.c
drivers/gpu/drm/imx/imx-drm-core.c
drivers/gpu/drm/imx/imx-hdmi.c
drivers/gpu/drm/imx/imx-ldb.c
drivers/gpu/drm/imx/imx-tve.c
drivers/gpu/drm/imx/parallel-display.c
drivers/gpu/drm/msm/msm_drv.c
drivers/gpu/drm/panel/panel-simple.c
drivers/gpu/drm/rcar-du/rcar_du_drv.c
drivers/gpu/drm/sti/sti_compositor.c
drivers/gpu/drm/sti/sti_drm_drv.c
drivers/gpu/drm/tilcdc/tilcdc_drv.c
drivers/iommu/amd_iommu_v2.c
include/linux/mmu_notifier.h
kernel/events/uprobes.c
kernel/time/time.c
mm/fremap.c
mm/huge_memory.c
mm/hugetlb.c
mm/memory.c
mm/migrate.c
mm/rmap.c

diff --cc MAINTAINERS
Simple merge
index 0000000000000000000000000000000000000000,2f80072417349e1588cf6fcf2631bb91716a500a..e48b2211d2d6852ad2a540834203576616262f41
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,705 +1,704 @@@
 -              .owner  = THIS_MODULE,
+ /*
+  * Freescale i.MX drm driver
+  *
+  * Copyright (C) 2011 Sascha Hauer, Pengutronix
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License
+  * as published by the Free Software Foundation; either version 2
+  * of the License, or (at your option) any later version.
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  */
+ #include <linux/component.h>
+ #include <linux/device.h>
+ #include <linux/fb.h>
+ #include <linux/module.h>
+ #include <linux/of_graph.h>
+ #include <linux/platform_device.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_gem_cma_helper.h>
+ #include <drm/drm_fb_cma_helper.h>
+ #include <drm/drm_plane_helper.h>
+ #include "imx-drm.h"
+ #define MAX_CRTC      4
+ struct imx_drm_crtc;
+ struct imx_drm_component {
+       struct device_node *of_node;
+       struct list_head list;
+ };
+ struct imx_drm_device {
+       struct drm_device                       *drm;
+       struct imx_drm_crtc                     *crtc[MAX_CRTC];
+       int                                     pipes;
+       struct drm_fbdev_cma                    *fbhelper;
+ };
+ struct imx_drm_crtc {
+       struct drm_crtc                         *crtc;
+       int                                     pipe;
+       struct imx_drm_crtc_helper_funcs        imx_drm_helper_funcs;
+       struct device_node                      *port;
+ };
+ static int legacyfb_depth = 16;
+ module_param(legacyfb_depth, int, 0444);
+ int imx_drm_crtc_id(struct imx_drm_crtc *crtc)
+ {
+       return crtc->pipe;
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_crtc_id);
+ static void imx_drm_driver_lastclose(struct drm_device *drm)
+ {
+ #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
+       struct imx_drm_device *imxdrm = drm->dev_private;
+       if (imxdrm->fbhelper)
+               drm_fbdev_cma_restore_mode(imxdrm->fbhelper);
+ #endif
+ }
+ static int imx_drm_driver_unload(struct drm_device *drm)
+ {
+ #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
+       struct imx_drm_device *imxdrm = drm->dev_private;
+ #endif
+       drm_kms_helper_poll_fini(drm);
+ #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
+       if (imxdrm->fbhelper)
+               drm_fbdev_cma_fini(imxdrm->fbhelper);
+ #endif
+       component_unbind_all(drm->dev, drm);
+       drm_vblank_cleanup(drm);
+       drm_mode_config_cleanup(drm);
+       platform_set_drvdata(drm->platformdev, NULL);
+       return 0;
+ }
+ static struct imx_drm_crtc *imx_drm_find_crtc(struct drm_crtc *crtc)
+ {
+       struct imx_drm_device *imxdrm = crtc->dev->dev_private;
+       unsigned i;
+       for (i = 0; i < MAX_CRTC; i++)
+               if (imxdrm->crtc[i] && imxdrm->crtc[i]->crtc == crtc)
+                       return imxdrm->crtc[i];
+       return NULL;
+ }
+ int imx_drm_panel_format_pins(struct drm_encoder *encoder,
+               u32 interface_pix_fmt, int hsync_pin, int vsync_pin)
+ {
+       struct imx_drm_crtc_helper_funcs *helper;
+       struct imx_drm_crtc *imx_crtc;
+       imx_crtc = imx_drm_find_crtc(encoder->crtc);
+       if (!imx_crtc)
+               return -EINVAL;
+       helper = &imx_crtc->imx_drm_helper_funcs;
+       if (helper->set_interface_pix_fmt)
+               return helper->set_interface_pix_fmt(encoder->crtc,
+                               encoder->encoder_type, interface_pix_fmt,
+                               hsync_pin, vsync_pin);
+       return 0;
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_panel_format_pins);
+ int imx_drm_panel_format(struct drm_encoder *encoder, u32 interface_pix_fmt)
+ {
+       return imx_drm_panel_format_pins(encoder, interface_pix_fmt, 2, 3);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_panel_format);
+ int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc)
+ {
+       return drm_vblank_get(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_get);
+ void imx_drm_crtc_vblank_put(struct imx_drm_crtc *imx_drm_crtc)
+ {
+       drm_vblank_put(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_put);
+ void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc)
+ {
+       drm_handle_vblank(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_handle_vblank);
+ static int imx_drm_enable_vblank(struct drm_device *drm, int crtc)
+ {
+       struct imx_drm_device *imxdrm = drm->dev_private;
+       struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc];
+       int ret;
+       if (!imx_drm_crtc)
+               return -EINVAL;
+       if (!imx_drm_crtc->imx_drm_helper_funcs.enable_vblank)
+               return -ENOSYS;
+       ret = imx_drm_crtc->imx_drm_helper_funcs.enable_vblank(
+                       imx_drm_crtc->crtc);
+       return ret;
+ }
+ static void imx_drm_disable_vblank(struct drm_device *drm, int crtc)
+ {
+       struct imx_drm_device *imxdrm = drm->dev_private;
+       struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc];
+       if (!imx_drm_crtc)
+               return;
+       if (!imx_drm_crtc->imx_drm_helper_funcs.disable_vblank)
+               return;
+       imx_drm_crtc->imx_drm_helper_funcs.disable_vblank(imx_drm_crtc->crtc);
+ }
+ static void imx_drm_driver_preclose(struct drm_device *drm,
+               struct drm_file *file)
+ {
+       int i;
+       if (!file->is_master)
+               return;
+       for (i = 0; i < MAX_CRTC; i++)
+               imx_drm_disable_vblank(drm, i);
+ }
+ static const struct file_operations imx_drm_driver_fops = {
+       .owner = THIS_MODULE,
+       .open = drm_open,
+       .release = drm_release,
+       .unlocked_ioctl = drm_ioctl,
+       .mmap = drm_gem_cma_mmap,
+       .poll = drm_poll,
+       .read = drm_read,
+       .llseek = noop_llseek,
+ };
+ void imx_drm_connector_destroy(struct drm_connector *connector)
+ {
+       drm_connector_unregister(connector);
+       drm_connector_cleanup(connector);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_connector_destroy);
+ void imx_drm_encoder_destroy(struct drm_encoder *encoder)
+ {
+       drm_encoder_cleanup(encoder);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_encoder_destroy);
+ static void imx_drm_output_poll_changed(struct drm_device *drm)
+ {
+ #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
+       struct imx_drm_device *imxdrm = drm->dev_private;
+       drm_fbdev_cma_hotplug_event(imxdrm->fbhelper);
+ #endif
+ }
+ static struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
+       .fb_create = drm_fb_cma_create,
+       .output_poll_changed = imx_drm_output_poll_changed,
+ };
+ /*
+  * Main DRM initialisation. This binds, initialises and registers
+  * with DRM the subcomponents of the driver.
+  */
+ static int imx_drm_driver_load(struct drm_device *drm, unsigned long flags)
+ {
+       struct imx_drm_device *imxdrm;
+       struct drm_connector *connector;
+       int ret;
+       imxdrm = devm_kzalloc(drm->dev, sizeof(*imxdrm), GFP_KERNEL);
+       if (!imxdrm)
+               return -ENOMEM;
+       imxdrm->drm = drm;
+       drm->dev_private = imxdrm;
+       /*
+        * enable drm irq mode.
+        * - with irq_enabled = true, we can use the vblank feature.
+        *
+        * P.S. note that we wouldn't use drm irq handler but
+        *      just specific driver own one instead because
+        *      drm framework supports only one irq handler and
+        *      drivers can well take care of their interrupts
+        */
+       drm->irq_enabled = true;
+       /*
+        * set max width and height as default value(4096x4096).
+        * this value would be used to check framebuffer size limitation
+        * at drm_mode_addfb().
+        */
+       drm->mode_config.min_width = 64;
+       drm->mode_config.min_height = 64;
+       drm->mode_config.max_width = 4096;
+       drm->mode_config.max_height = 4096;
+       drm->mode_config.funcs = &imx_drm_mode_config_funcs;
+       drm_mode_config_init(drm);
+       ret = drm_vblank_init(drm, MAX_CRTC);
+       if (ret)
+               goto err_kms;
+       /*
+        * with vblank_disable_allowed = true, vblank interrupt will be
+        * disabled by drm timer once a current process gives up ownership
+        * of vblank event. (after drm_vblank_put function is called)
+        */
+       drm->vblank_disable_allowed = true;
+       platform_set_drvdata(drm->platformdev, drm);
+       /* Now try and bind all our sub-components */
+       ret = component_bind_all(drm->dev, drm);
+       if (ret)
+               goto err_vblank;
+       /*
+        * All components are now added, we can publish the connector sysfs
+        * entries to userspace.  This will generate hotplug events and so
+        * userspace will expect to be able to access DRM at this point.
+        */
+       list_for_each_entry(connector, &drm->mode_config.connector_list, head) {
+               ret = drm_connector_register(connector);
+               if (ret) {
+                       dev_err(drm->dev,
+                               "[CONNECTOR:%d:%s] drm_connector_register failed: %d\n",
+                               connector->base.id,
+                               connector->name, ret);
+                       goto err_unbind;
+               }
+       }
+       /*
+        * All components are now initialised, so setup the fb helper.
+        * The fb helper takes copies of key hardware information, so the
+        * crtcs/connectors/encoders must not change after this point.
+        */
+ #if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
+       if (legacyfb_depth != 16 && legacyfb_depth != 32) {
+               dev_warn(drm->dev, "Invalid legacyfb_depth.  Defaulting to 16bpp\n");
+               legacyfb_depth = 16;
+       }
+       imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth,
+                               drm->mode_config.num_crtc, MAX_CRTC);
+       if (IS_ERR(imxdrm->fbhelper)) {
+               ret = PTR_ERR(imxdrm->fbhelper);
+               imxdrm->fbhelper = NULL;
+               goto err_unbind;
+       }
+ #endif
+       drm_kms_helper_poll_init(drm);
+       return 0;
+ err_unbind:
+       component_unbind_all(drm->dev, drm);
+ err_vblank:
+       drm_vblank_cleanup(drm);
+ err_kms:
+       drm_mode_config_cleanup(drm);
+       return ret;
+ }
+ /*
+  * imx_drm_add_crtc - add a new crtc
+  */
+ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
+               struct imx_drm_crtc **new_crtc,
+               const struct imx_drm_crtc_helper_funcs *imx_drm_helper_funcs,
+               struct device_node *port)
+ {
+       struct imx_drm_device *imxdrm = drm->dev_private;
+       struct imx_drm_crtc *imx_drm_crtc;
+       int ret;
+       /*
+        * The vblank arrays are dimensioned by MAX_CRTC - we can't
+        * pass IDs greater than this to those functions.
+        */
+       if (imxdrm->pipes >= MAX_CRTC)
+               return -EINVAL;
+       if (imxdrm->drm->open_count)
+               return -EBUSY;
+       imx_drm_crtc = kzalloc(sizeof(*imx_drm_crtc), GFP_KERNEL);
+       if (!imx_drm_crtc)
+               return -ENOMEM;
+       imx_drm_crtc->imx_drm_helper_funcs = *imx_drm_helper_funcs;
+       imx_drm_crtc->pipe = imxdrm->pipes++;
+       imx_drm_crtc->port = port;
+       imx_drm_crtc->crtc = crtc;
+       imxdrm->crtc[imx_drm_crtc->pipe] = imx_drm_crtc;
+       *new_crtc = imx_drm_crtc;
+       ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256);
+       if (ret)
+               goto err_register;
+       drm_crtc_helper_add(crtc,
+                       imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
+       drm_crtc_init(drm, crtc,
+                       imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs);
+       return 0;
+ err_register:
+       imxdrm->crtc[imx_drm_crtc->pipe] = NULL;
+       kfree(imx_drm_crtc);
+       return ret;
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_add_crtc);
+ /*
+  * imx_drm_remove_crtc - remove a crtc
+  */
+ int imx_drm_remove_crtc(struct imx_drm_crtc *imx_drm_crtc)
+ {
+       struct imx_drm_device *imxdrm = imx_drm_crtc->crtc->dev->dev_private;
+       drm_crtc_cleanup(imx_drm_crtc->crtc);
+       imxdrm->crtc[imx_drm_crtc->pipe] = NULL;
+       kfree(imx_drm_crtc);
+       return 0;
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_remove_crtc);
+ /*
+  * Find the DRM CRTC possible mask for the connected endpoint.
+  *
+  * The encoder possible masks are defined by their position in the
+  * mode_config crtc_list.  This means that CRTCs must not be added
+  * or removed once the DRM device has been fully initialised.
+  */
+ static uint32_t imx_drm_find_crtc_mask(struct imx_drm_device *imxdrm,
+       struct device_node *endpoint)
+ {
+       struct device_node *port;
+       unsigned i;
+       port = of_graph_get_remote_port(endpoint);
+       if (!port)
+               return 0;
+       of_node_put(port);
+       for (i = 0; i < MAX_CRTC; i++) {
+               struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[i];
+               if (imx_drm_crtc && imx_drm_crtc->port == port)
+                       return drm_crtc_mask(imx_drm_crtc->crtc);
+       }
+       return 0;
+ }
+ static struct device_node *imx_drm_of_get_next_endpoint(
+               const struct device_node *parent, struct device_node *prev)
+ {
+       struct device_node *node = of_graph_get_next_endpoint(parent, prev);
+       of_node_put(prev);
+       return node;
+ }
+ int imx_drm_encoder_parse_of(struct drm_device *drm,
+       struct drm_encoder *encoder, struct device_node *np)
+ {
+       struct imx_drm_device *imxdrm = drm->dev_private;
+       struct device_node *ep = NULL;
+       uint32_t crtc_mask = 0;
+       int i;
+       for (i = 0; ; i++) {
+               u32 mask;
+               ep = imx_drm_of_get_next_endpoint(np, ep);
+               if (!ep)
+                       break;
+               mask = imx_drm_find_crtc_mask(imxdrm, ep);
+               /*
+                * If we failed to find the CRTC(s) which this encoder is
+                * supposed to be connected to, it's because the CRTC has
+                * not been registered yet.  Defer probing, and hope that
+                * the required CRTC is added later.
+                */
+               if (mask == 0)
+                       return -EPROBE_DEFER;
+               crtc_mask |= mask;
+       }
+       of_node_put(ep);
+       if (i == 0)
+               return -ENOENT;
+       encoder->possible_crtcs = crtc_mask;
+       /* FIXME: this is the mask of outputs which can clone this output. */
+       encoder->possible_clones = ~0;
+       return 0;
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
+ /*
+  * @node: device tree node containing encoder input ports
+  * @encoder: drm_encoder
+  */
+ int imx_drm_encoder_get_mux_id(struct device_node *node,
+                              struct drm_encoder *encoder)
+ {
+       struct imx_drm_crtc *imx_crtc = imx_drm_find_crtc(encoder->crtc);
+       struct device_node *ep = NULL;
+       struct of_endpoint endpoint;
+       struct device_node *port;
+       int ret;
+       if (!node || !imx_crtc)
+               return -EINVAL;
+       do {
+               ep = imx_drm_of_get_next_endpoint(node, ep);
+               if (!ep)
+                       break;
+               port = of_graph_get_remote_port(ep);
+               of_node_put(port);
+               if (port == imx_crtc->port) {
+                       ret = of_graph_parse_endpoint(ep, &endpoint);
+                       return ret ? ret : endpoint.port;
+               }
+       } while (ep);
+       return -EINVAL;
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_encoder_get_mux_id);
+ static const struct drm_ioctl_desc imx_drm_ioctls[] = {
+       /* none so far */
+ };
+ static struct drm_driver imx_drm_driver = {
+       .driver_features        = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
+       .load                   = imx_drm_driver_load,
+       .unload                 = imx_drm_driver_unload,
+       .lastclose              = imx_drm_driver_lastclose,
+       .preclose               = imx_drm_driver_preclose,
+       .set_busid              = drm_platform_set_busid,
+       .gem_free_object        = drm_gem_cma_free_object,
+       .gem_vm_ops             = &drm_gem_cma_vm_ops,
+       .dumb_create            = drm_gem_cma_dumb_create,
+       .dumb_map_offset        = drm_gem_cma_dumb_map_offset,
+       .dumb_destroy           = drm_gem_dumb_destroy,
+       .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
+       .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
+       .gem_prime_import       = drm_gem_prime_import,
+       .gem_prime_export       = drm_gem_prime_export,
+       .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+       .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+       .gem_prime_vmap         = drm_gem_cma_prime_vmap,
+       .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
+       .gem_prime_mmap         = drm_gem_cma_prime_mmap,
+       .get_vblank_counter     = drm_vblank_count,
+       .enable_vblank          = imx_drm_enable_vblank,
+       .disable_vblank         = imx_drm_disable_vblank,
+       .ioctls                 = imx_drm_ioctls,
+       .num_ioctls             = ARRAY_SIZE(imx_drm_ioctls),
+       .fops                   = &imx_drm_driver_fops,
+       .name                   = "imx-drm",
+       .desc                   = "i.MX DRM graphics",
+       .date                   = "20120507",
+       .major                  = 1,
+       .minor                  = 0,
+       .patchlevel             = 0,
+ };
+ static int compare_of(struct device *dev, void *data)
+ {
+       struct device_node *np = data;
+       /* Special case for LDB, one device for two channels */
+       if (of_node_cmp(np->name, "lvds-channel") == 0) {
+               np = of_get_parent(np);
+               of_node_put(np);
+       }
+       return dev->of_node == np;
+ }
+ static int imx_drm_bind(struct device *dev)
+ {
+       return drm_platform_init(&imx_drm_driver, to_platform_device(dev));
+ }
+ static void imx_drm_unbind(struct device *dev)
+ {
+       drm_put_dev(dev_get_drvdata(dev));
+ }
+ static const struct component_master_ops imx_drm_ops = {
+       .bind = imx_drm_bind,
+       .unbind = imx_drm_unbind,
+ };
+ static int imx_drm_platform_probe(struct platform_device *pdev)
+ {
+       struct device_node *ep, *port, *remote;
+       struct component_match *match = NULL;
+       int ret;
+       int i;
+       /*
+        * Bind the IPU display interface ports first, so that
+        * imx_drm_encoder_parse_of called from encoder .bind callbacks
+        * works as expected.
+        */
+       for (i = 0; ; i++) {
+               port = of_parse_phandle(pdev->dev.of_node, "ports", i);
+               if (!port)
+                       break;
+               component_match_add(&pdev->dev, &match, compare_of, port);
+       }
+       if (i == 0) {
+               dev_err(&pdev->dev, "missing 'ports' property\n");
+               return -ENODEV;
+       }
+       /* Then bind all encoders */
+       for (i = 0; ; i++) {
+               port = of_parse_phandle(pdev->dev.of_node, "ports", i);
+               if (!port)
+                       break;
+               for_each_child_of_node(port, ep) {
+                       remote = of_graph_get_remote_port_parent(ep);
+                       if (!remote || !of_device_is_available(remote)) {
+                               of_node_put(remote);
+                               continue;
+                       } else if (!of_device_is_available(remote->parent)) {
+                               dev_warn(&pdev->dev, "parent device of %s is not available\n",
+                                        remote->full_name);
+                               of_node_put(remote);
+                               continue;
+                       }
+                       component_match_add(&pdev->dev, &match, compare_of, remote);
+                       of_node_put(remote);
+               }
+               of_node_put(port);
+       }
+       ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+       if (ret)
+               return ret;
+       return component_master_add_with_match(&pdev->dev, &imx_drm_ops, match);
+ }
+ static int imx_drm_platform_remove(struct platform_device *pdev)
+ {
+       component_master_del(&pdev->dev, &imx_drm_ops);
+       return 0;
+ }
+ #ifdef CONFIG_PM_SLEEP
+ static int imx_drm_suspend(struct device *dev)
+ {
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
+       /* The drm_dev is NULL before .load hook is called */
+       if (drm_dev == NULL)
+               return 0;
+       drm_kms_helper_poll_disable(drm_dev);
+       return 0;
+ }
+ static int imx_drm_resume(struct device *dev)
+ {
+       struct drm_device *drm_dev = dev_get_drvdata(dev);
+       if (drm_dev == NULL)
+               return 0;
+       drm_helper_resume_force_mode(drm_dev);
+       drm_kms_helper_poll_enable(drm_dev);
+       return 0;
+ }
+ #endif
+ static SIMPLE_DEV_PM_OPS(imx_drm_pm_ops, imx_drm_suspend, imx_drm_resume);
+ static const struct of_device_id imx_drm_dt_ids[] = {
+       { .compatible = "fsl,imx-display-subsystem", },
+       { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, imx_drm_dt_ids);
+ static struct platform_driver imx_drm_pdrv = {
+       .probe          = imx_drm_platform_probe,
+       .remove         = imx_drm_platform_remove,
+       .driver         = {
+               .name   = "imx-drm",
+               .pm     = &imx_drm_pm_ops,
+               .of_match_table = imx_drm_dt_ids,
+       },
+ };
+ module_platform_driver(imx_drm_pdrv);
+ MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+ MODULE_DESCRIPTION("i.MX drm driver core");
+ MODULE_LICENSE("GPL");
index 0000000000000000000000000000000000000000,aaec6b2cdf562f32c86e981555eef949c9901a2e..ddc53e039530bd4d8897e686894dd6e30359883a
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,1767 +1,1766 @@@
 -              .owner = THIS_MODULE,
+ /*
+  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
+  * for SLISHDMI13T and SLIPHDMIT IP cores
+  *
+  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+  */
+ #include <linux/component.h>
+ #include <linux/irq.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/clk.h>
+ #include <linux/hdmi.h>
+ #include <linux/regmap.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+ #include <linux/of_device.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_edid.h>
+ #include <drm/drm_encoder_slave.h>
+ #include <video/imx-ipu-v3.h>
+ #include "imx-hdmi.h"
+ #include "imx-drm.h"
+ #define HDMI_EDID_LEN         512
+ #define RGB                   0
+ #define YCBCR444              1
+ #define YCBCR422_16BITS               2
+ #define YCBCR422_8BITS                3
+ #define XVYCC444              4
+ enum hdmi_datamap {
+       RGB444_8B = 0x01,
+       RGB444_10B = 0x03,
+       RGB444_12B = 0x05,
+       RGB444_16B = 0x07,
+       YCbCr444_8B = 0x09,
+       YCbCr444_10B = 0x0B,
+       YCbCr444_12B = 0x0D,
+       YCbCr444_16B = 0x0F,
+       YCbCr422_8B = 0x16,
+       YCbCr422_10B = 0x14,
+       YCbCr422_12B = 0x12,
+ };
+ enum imx_hdmi_devtype {
+       IMX6Q_HDMI,
+       IMX6DL_HDMI,
+ };
+ static const u16 csc_coeff_default[3][4] = {
+       { 0x2000, 0x0000, 0x0000, 0x0000 },
+       { 0x0000, 0x2000, 0x0000, 0x0000 },
+       { 0x0000, 0x0000, 0x2000, 0x0000 }
+ };
+ static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
+       { 0x2000, 0x6926, 0x74fd, 0x010e },
+       { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
+       { 0x2000, 0x0000, 0x38b4, 0x7e3b }
+ };
+ static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
+       { 0x2000, 0x7106, 0x7a02, 0x00a7 },
+       { 0x2000, 0x3264, 0x0000, 0x7e6d },
+       { 0x2000, 0x0000, 0x3b61, 0x7e25 }
+ };
+ static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
+       { 0x2591, 0x1322, 0x074b, 0x0000 },
+       { 0x6535, 0x2000, 0x7acc, 0x0200 },
+       { 0x6acd, 0x7534, 0x2000, 0x0200 }
+ };
+ static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
+       { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
+       { 0x62f0, 0x2000, 0x7d11, 0x0200 },
+       { 0x6756, 0x78ab, 0x2000, 0x0200 }
+ };
+ struct hdmi_vmode {
+       bool mdvi;
+       bool mhsyncpolarity;
+       bool mvsyncpolarity;
+       bool minterlaced;
+       bool mdataenablepolarity;
+       unsigned int mpixelclock;
+       unsigned int mpixelrepetitioninput;
+       unsigned int mpixelrepetitionoutput;
+ };
+ struct hdmi_data_info {
+       unsigned int enc_in_format;
+       unsigned int enc_out_format;
+       unsigned int enc_color_depth;
+       unsigned int colorimetry;
+       unsigned int pix_repet_factor;
+       unsigned int hdcp_enable;
+       struct hdmi_vmode video_mode;
+ };
+ struct imx_hdmi {
+       struct drm_connector connector;
+       struct drm_encoder encoder;
+       enum imx_hdmi_devtype dev_type;
+       struct device *dev;
+       struct clk *isfr_clk;
+       struct clk *iahb_clk;
+       struct hdmi_data_info hdmi_data;
+       int vic;
+       u8 edid[HDMI_EDID_LEN];
+       bool cable_plugin;
+       bool phy_enabled;
+       struct drm_display_mode previous_mode;
+       struct regmap *regmap;
+       struct i2c_adapter *ddc;
+       void __iomem *regs;
+       unsigned int sample_rate;
+       int ratio;
+ };
+ static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di)
+ {
+       regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
+                          IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
+                          ipu_di << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
+ }
+ static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset)
+ {
+       writeb(val, hdmi->regs + offset);
+ }
+ static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset)
+ {
+       return readb(hdmi->regs + offset);
+ }
+ static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
+ {
+       u8 val = hdmi_readb(hdmi, reg) & ~mask;
+       val |= data & mask;
+       hdmi_writeb(hdmi, val, reg);
+ }
+ static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg,
+                     u8 shift, u8 mask)
+ {
+       hdmi_modb(hdmi, data << shift, mask, reg);
+ }
+ static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi,
+                                        unsigned int value)
+ {
+       hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
+       hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
+       hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
+       /* nshift factor = 0 */
+       hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
+ }
+ static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts)
+ {
+       /* Must be set/cleared first */
+       hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+       hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
+       hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
+       hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
+                   HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
+ }
+ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
+                                  unsigned int ratio)
+ {
+       unsigned int n = (128 * freq) / 1000;
+       switch (freq) {
+       case 32000:
+               if (pixel_clk == 25170000)
+                       n = (ratio == 150) ? 9152 : 4576;
+               else if (pixel_clk == 27020000)
+                       n = (ratio == 150) ? 8192 : 4096;
+               else if (pixel_clk == 74170000 || pixel_clk == 148350000)
+                       n = 11648;
+               else
+                       n = 4096;
+               break;
+       case 44100:
+               if (pixel_clk == 25170000)
+                       n = 7007;
+               else if (pixel_clk == 74170000)
+                       n = 17836;
+               else if (pixel_clk == 148350000)
+                       n = (ratio == 150) ? 17836 : 8918;
+               else
+                       n = 6272;
+               break;
+       case 48000:
+               if (pixel_clk == 25170000)
+                       n = (ratio == 150) ? 9152 : 6864;
+               else if (pixel_clk == 27020000)
+                       n = (ratio == 150) ? 8192 : 6144;
+               else if (pixel_clk == 74170000)
+                       n = 11648;
+               else if (pixel_clk == 148350000)
+                       n = (ratio == 150) ? 11648 : 5824;
+               else
+                       n = 6144;
+               break;
+       case 88200:
+               n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
+               break;
+       case 96000:
+               n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
+               break;
+       case 176400:
+               n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
+               break;
+       case 192000:
+               n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
+               break;
+       default:
+               break;
+       }
+       return n;
+ }
+ static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
+                                    unsigned int ratio)
+ {
+       unsigned int cts = 0;
+       pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
+                pixel_clk, ratio);
+       switch (freq) {
+       case 32000:
+               if (pixel_clk == 297000000) {
+                       cts = 222750;
+                       break;
+               }
+       case 48000:
+       case 96000:
+       case 192000:
+               switch (pixel_clk) {
+               case 25200000:
+               case 27000000:
+               case 54000000:
+               case 74250000:
+               case 148500000:
+                       cts = pixel_clk / 1000;
+                       break;
+               case 297000000:
+                       cts = 247500;
+                       break;
+               /*
+                * All other TMDS clocks are not supported by
+                * DWC_hdmi_tx. The TMDS clocks divided or
+                * multiplied by 1,001 coefficients are not
+                * supported.
+                */
+               default:
+                       break;
+               }
+               break;
+       case 44100:
+       case 88200:
+       case 176400:
+               switch (pixel_clk) {
+               case 25200000:
+                       cts = 28000;
+                       break;
+               case 27000000:
+                       cts = 30000;
+                       break;
+               case 54000000:
+                       cts = 60000;
+                       break;
+               case 74250000:
+                       cts = 82500;
+                       break;
+               case 148500000:
+                       cts = 165000;
+                       break;
+               case 297000000:
+                       cts = 247500;
+                       break;
+               default:
+                       break;
+               }
+               break;
+       default:
+               break;
+       }
+       if (ratio == 100)
+               return cts;
+       return (cts * ratio) / 100;
+ }
+ static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi,
+       unsigned long pixel_clk)
+ {
+       unsigned int clk_n, clk_cts;
+       clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
+                              hdmi->ratio);
+       clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
+                                  hdmi->ratio);
+       if (!clk_cts) {
+               dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
+                        __func__, pixel_clk);
+               return;
+       }
+       dev_dbg(hdmi->dev, "%s: samplerate=%d  ratio=%d  pixelclk=%lu  N=%d cts=%d\n",
+               __func__, hdmi->sample_rate, hdmi->ratio,
+               pixel_clk, clk_n, clk_cts);
+       hdmi_set_clock_regenerator_n(hdmi, clk_n);
+       hdmi_regenerate_cts(hdmi, clk_cts);
+ }
+ static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi)
+ {
+       hdmi_set_clk_regenerator(hdmi, 74250000);
+ }
+ static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi)
+ {
+       hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
+ }
+ /*
+  * this submodule is responsible for the video data synchronization.
+  * for example, for RGB 4:4:4 input, the data map is defined as
+  *                    pin{47~40} <==> R[7:0]
+  *                    pin{31~24} <==> G[7:0]
+  *                    pin{15~8}  <==> B[7:0]
+  */
+ static void hdmi_video_sample(struct imx_hdmi *hdmi)
+ {
+       int color_format = 0;
+       u8 val;
+       if (hdmi->hdmi_data.enc_in_format == RGB) {
+               if (hdmi->hdmi_data.enc_color_depth == 8)
+                       color_format = 0x01;
+               else if (hdmi->hdmi_data.enc_color_depth == 10)
+                       color_format = 0x03;
+               else if (hdmi->hdmi_data.enc_color_depth == 12)
+                       color_format = 0x05;
+               else if (hdmi->hdmi_data.enc_color_depth == 16)
+                       color_format = 0x07;
+               else
+                       return;
+       } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
+               if (hdmi->hdmi_data.enc_color_depth == 8)
+                       color_format = 0x09;
+               else if (hdmi->hdmi_data.enc_color_depth == 10)
+                       color_format = 0x0B;
+               else if (hdmi->hdmi_data.enc_color_depth == 12)
+                       color_format = 0x0D;
+               else if (hdmi->hdmi_data.enc_color_depth == 16)
+                       color_format = 0x0F;
+               else
+                       return;
+       } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
+               if (hdmi->hdmi_data.enc_color_depth == 8)
+                       color_format = 0x16;
+               else if (hdmi->hdmi_data.enc_color_depth == 10)
+                       color_format = 0x14;
+               else if (hdmi->hdmi_data.enc_color_depth == 12)
+                       color_format = 0x12;
+               else
+                       return;
+       }
+       val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
+               ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
+               HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
+       hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
+       /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
+       val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
+               HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
+               HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
+       hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
+       hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
+       hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
+       hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
+       hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
+       hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
+       hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
+ }
+ static int is_color_space_conversion(struct imx_hdmi *hdmi)
+ {
+       return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
+ }
+ static int is_color_space_decimation(struct imx_hdmi *hdmi)
+ {
+       if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
+               return 0;
+       if (hdmi->hdmi_data.enc_in_format == RGB ||
+           hdmi->hdmi_data.enc_in_format == YCBCR444)
+               return 1;
+       return 0;
+ }
+ static int is_color_space_interpolation(struct imx_hdmi *hdmi)
+ {
+       if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
+               return 0;
+       if (hdmi->hdmi_data.enc_out_format == RGB ||
+           hdmi->hdmi_data.enc_out_format == YCBCR444)
+               return 1;
+       return 0;
+ }
+ static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi)
+ {
+       const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
+       unsigned i;
+       u32 csc_scale = 1;
+       if (is_color_space_conversion(hdmi)) {
+               if (hdmi->hdmi_data.enc_out_format == RGB) {
+                       if (hdmi->hdmi_data.colorimetry ==
+                                       HDMI_COLORIMETRY_ITU_601)
+                               csc_coeff = &csc_coeff_rgb_out_eitu601;
+                       else
+                               csc_coeff = &csc_coeff_rgb_out_eitu709;
+               } else if (hdmi->hdmi_data.enc_in_format == RGB) {
+                       if (hdmi->hdmi_data.colorimetry ==
+                                       HDMI_COLORIMETRY_ITU_601)
+                               csc_coeff = &csc_coeff_rgb_in_eitu601;
+                       else
+                               csc_coeff = &csc_coeff_rgb_in_eitu709;
+                       csc_scale = 0;
+               }
+       }
+       /* The CSC registers are sequential, alternating MSB then LSB */
+       for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
+               u16 coeff_a = (*csc_coeff)[0][i];
+               u16 coeff_b = (*csc_coeff)[1][i];
+               u16 coeff_c = (*csc_coeff)[2][i];
+               hdmi_writeb(hdmi, coeff_a & 0xff,
+                       HDMI_CSC_COEF_A1_LSB + i * 2);
+               hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
+               hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
+               hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
+               hdmi_writeb(hdmi, coeff_c & 0xff,
+                       HDMI_CSC_COEF_C1_LSB + i * 2);
+               hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
+       }
+       hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
+                 HDMI_CSC_SCALE);
+ }
+ static void hdmi_video_csc(struct imx_hdmi *hdmi)
+ {
+       int color_depth = 0;
+       int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
+       int decimation = 0;
+       /* YCC422 interpolation to 444 mode */
+       if (is_color_space_interpolation(hdmi))
+               interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
+       else if (is_color_space_decimation(hdmi))
+               decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
+       if (hdmi->hdmi_data.enc_color_depth == 8)
+               color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
+       else if (hdmi->hdmi_data.enc_color_depth == 10)
+               color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
+       else if (hdmi->hdmi_data.enc_color_depth == 12)
+               color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
+       else if (hdmi->hdmi_data.enc_color_depth == 16)
+               color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
+       else
+               return;
+       /* Configure the CSC registers */
+       hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
+       hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
+                 HDMI_CSC_SCALE);
+       imx_hdmi_update_csc_coeffs(hdmi);
+ }
+ /*
+  * HDMI video packetizer is used to packetize the data.
+  * for example, if input is YCC422 mode or repeater is used,
+  * data should be repacked this module can be bypassed.
+  */
+ static void hdmi_video_packetize(struct imx_hdmi *hdmi)
+ {
+       unsigned int color_depth = 0;
+       unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
+       unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
+       struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
+       u8 val, vp_conf;
+       if (hdmi_data->enc_out_format == RGB
+               || hdmi_data->enc_out_format == YCBCR444) {
+               if (!hdmi_data->enc_color_depth)
+                       output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+               else if (hdmi_data->enc_color_depth == 8) {
+                       color_depth = 4;
+                       output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
+               } else if (hdmi_data->enc_color_depth == 10)
+                       color_depth = 5;
+               else if (hdmi_data->enc_color_depth == 12)
+                       color_depth = 6;
+               else if (hdmi_data->enc_color_depth == 16)
+                       color_depth = 7;
+               else
+                       return;
+       } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
+               if (!hdmi_data->enc_color_depth ||
+                   hdmi_data->enc_color_depth == 8)
+                       remap_size = HDMI_VP_REMAP_YCC422_16bit;
+               else if (hdmi_data->enc_color_depth == 10)
+                       remap_size = HDMI_VP_REMAP_YCC422_20bit;
+               else if (hdmi_data->enc_color_depth == 12)
+                       remap_size = HDMI_VP_REMAP_YCC422_24bit;
+               else
+                       return;
+               output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
+       } else
+               return;
+       /* set the packetizer registers */
+       val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
+               HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
+               ((hdmi_data->pix_repet_factor <<
+               HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
+               HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
+       hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
+       hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
+                 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
+       /* Data from pixel repeater block */
+       if (hdmi_data->pix_repet_factor > 1) {
+               vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
+                         HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
+       } else { /* data from packetizer block */
+               vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
+                         HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
+       }
+       hdmi_modb(hdmi, vp_conf,
+                 HDMI_VP_CONF_PR_EN_MASK |
+                 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
+       hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
+                 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
+       hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
+       if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
+               vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
+                         HDMI_VP_CONF_PP_EN_ENABLE |
+                         HDMI_VP_CONF_YCC422_EN_DISABLE;
+       } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
+               vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
+                         HDMI_VP_CONF_PP_EN_DISABLE |
+                         HDMI_VP_CONF_YCC422_EN_ENABLE;
+       } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
+               vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
+                         HDMI_VP_CONF_PP_EN_DISABLE |
+                         HDMI_VP_CONF_YCC422_EN_DISABLE;
+       } else {
+               return;
+       }
+       hdmi_modb(hdmi, vp_conf,
+                 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
+                 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
+       hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
+                       HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
+                 HDMI_VP_STUFF_PP_STUFFING_MASK |
+                 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
+       hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
+                 HDMI_VP_CONF);
+ }
+ static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi,
+                                               unsigned char bit)
+ {
+       hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
+                 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
+ }
+ static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi,
+                                               unsigned char bit)
+ {
+       hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
+                 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
+ }
+ static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi,
+                                               unsigned char bit)
+ {
+       hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
+                 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
+ }
+ static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi,
+                                               unsigned char bit)
+ {
+       hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
+ }
+ static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
+                                               unsigned char bit)
+ {
+       hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
+ }
+ static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
+ {
+       while ((hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
+               if (msec-- == 0)
+                       return false;
+               udelay(1000);
+       }
+       return true;
+ }
+ static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
+                             unsigned char addr)
+ {
+       hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
+       hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
+       hdmi_writeb(hdmi, (unsigned char)(data >> 8),
+               HDMI_PHY_I2CM_DATAO_1_ADDR);
+       hdmi_writeb(hdmi, (unsigned char)(data >> 0),
+               HDMI_PHY_I2CM_DATAO_0_ADDR);
+       hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
+               HDMI_PHY_I2CM_OPERATION_ADDR);
+       hdmi_phy_wait_i2c_done(hdmi, 1000);
+ }
+ static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
+                                    unsigned char addr)
+ {
+       __hdmi_phy_i2c_write(hdmi, data, addr);
+       return 0;
+ }
+ static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable)
+ {
+       hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+                        HDMI_PHY_CONF0_PDZ_OFFSET,
+                        HDMI_PHY_CONF0_PDZ_MASK);
+ }
+ static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable)
+ {
+       hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+                        HDMI_PHY_CONF0_ENTMDS_OFFSET,
+                        HDMI_PHY_CONF0_ENTMDS_MASK);
+ }
+ static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable)
+ {
+       hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+                        HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
+                        HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
+ }
+ static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable)
+ {
+       hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+                        HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
+                        HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
+ }
+ static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable)
+ {
+       hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+                        HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
+                        HDMI_PHY_CONF0_SELDATAENPOL_MASK);
+ }
+ static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
+ {
+       hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
+                        HDMI_PHY_CONF0_SELDIPIF_OFFSET,
+                        HDMI_PHY_CONF0_SELDIPIF_MASK);
+ }
+ enum {
+       RES_8,
+       RES_10,
+       RES_12,
+       RES_MAX,
+ };
+ struct mpll_config {
+       unsigned long mpixelclock;
+       struct {
+               u16 cpce;
+               u16 gmp;
+       } res[RES_MAX];
+ };
+ static const struct mpll_config mpll_config[] = {
+       {
+               45250000, {
+                       { 0x01e0, 0x0000 },
+                       { 0x21e1, 0x0000 },
+                       { 0x41e2, 0x0000 }
+               },
+       }, {
+               92500000, {
+                       { 0x0140, 0x0005 },
+                       { 0x2141, 0x0005 },
+                       { 0x4142, 0x0005 },
+               },
+       }, {
+               148500000, {
+                       { 0x00a0, 0x000a },
+                       { 0x20a1, 0x000a },
+                       { 0x40a2, 0x000a },
+               },
+       }, {
+               ~0UL, {
+                       { 0x00a0, 0x000a },
+                       { 0x2001, 0x000f },
+                       { 0x4002, 0x000f },
+               },
+       }
+ };
+ struct curr_ctrl {
+       unsigned long mpixelclock;
+       u16 curr[RES_MAX];
+ };
+ static const struct curr_ctrl curr_ctrl[] = {
+       /*      pixelclk     bpp8    bpp10   bpp12 */
+       {
+                54000000, { 0x091c, 0x091c, 0x06dc },
+       }, {
+                58400000, { 0x091c, 0x06dc, 0x06dc },
+       }, {
+                72000000, { 0x06dc, 0x06dc, 0x091c },
+       }, {
+                74250000, { 0x06dc, 0x0b5c, 0x091c },
+       }, {
+               118800000, { 0x091c, 0x091c, 0x06dc },
+       }, {
+               216000000, { 0x06dc, 0x0b5c, 0x091c },
+       }
+ };
+ static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
+                             unsigned char res, int cscon)
+ {
+       unsigned res_idx, i;
+       u8 val, msec;
+       if (prep)
+               return -EINVAL;
+       switch (res) {
+       case 0: /* color resolution 0 is 8 bit colour depth */
+       case 8:
+               res_idx = RES_8;
+               break;
+       case 10:
+               res_idx = RES_10;
+               break;
+       case 12:
+               res_idx = RES_12;
+               break;
+       default:
+               return -EINVAL;
+       }
+       /* Enable csc path */
+       if (cscon)
+               val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
+       else
+               val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
+       hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
+       /* gen2 tx power off */
+       imx_hdmi_phy_gen2_txpwron(hdmi, 0);
+       /* gen2 pddq */
+       imx_hdmi_phy_gen2_pddq(hdmi, 1);
+       /* PHY reset */
+       hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
+       hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
+       hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
+       hdmi_phy_test_clear(hdmi, 1);
+       hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
+                       HDMI_PHY_I2CM_SLAVE_ADDR);
+       hdmi_phy_test_clear(hdmi, 0);
+       /* PLL/MPLL Cfg - always match on final entry */
+       for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
+               if (hdmi->hdmi_data.video_mode.mpixelclock <=
+                   mpll_config[i].mpixelclock)
+                       break;
+       hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
+       hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
+       for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
+               if (hdmi->hdmi_data.video_mode.mpixelclock <=
+                   curr_ctrl[i].mpixelclock)
+                       break;
+       if (i >= ARRAY_SIZE(curr_ctrl)) {
+               dev_err(hdmi->dev,
+                               "Pixel clock %d - unsupported by HDMI\n",
+                               hdmi->hdmi_data.video_mode.mpixelclock);
+               return -EINVAL;
+       }
+       /* CURRCTRL */
+       hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
+       hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
+       hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
+       /* RESISTANCE TERM 133Ohm Cfg */
+       hdmi_phy_i2c_write(hdmi, 0x0005, 0x19);  /* TXTERM */
+       /* PREEMP Cgf 0.00 */
+       hdmi_phy_i2c_write(hdmi, 0x800d, 0x09);  /* CKSYMTXCTRL */
+       /* TX/CK LVL 10 */
+       hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */
+       /* REMOVE CLK TERM */
+       hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
+       imx_hdmi_phy_enable_power(hdmi, 1);
+       /* toggle TMDS enable */
+       imx_hdmi_phy_enable_tmds(hdmi, 0);
+       imx_hdmi_phy_enable_tmds(hdmi, 1);
+       /* gen2 tx power on */
+       imx_hdmi_phy_gen2_txpwron(hdmi, 1);
+       imx_hdmi_phy_gen2_pddq(hdmi, 0);
+       /*Wait for PHY PLL lock */
+       msec = 5;
+       do {
+               val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
+               if (!val)
+                       break;
+               if (msec == 0) {
+                       dev_err(hdmi->dev, "PHY PLL not locked\n");
+                       return -ETIMEDOUT;
+               }
+               udelay(1000);
+               msec--;
+       } while (1);
+       return 0;
+ }
+ static int imx_hdmi_phy_init(struct imx_hdmi *hdmi)
+ {
+       int i, ret;
+       bool cscon = false;
+       /*check csc whether needed activated in HDMI mode */
+       cscon = (is_color_space_conversion(hdmi) &&
+                       !hdmi->hdmi_data.video_mode.mdvi);
+       /* HDMI Phy spec says to do the phy initialization sequence twice */
+       for (i = 0; i < 2; i++) {
+               imx_hdmi_phy_sel_data_en_pol(hdmi, 1);
+               imx_hdmi_phy_sel_interface_control(hdmi, 0);
+               imx_hdmi_phy_enable_tmds(hdmi, 0);
+               imx_hdmi_phy_enable_power(hdmi, 0);
+               /* Enable CSC */
+               ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
+               if (ret)
+                       return ret;
+       }
+       hdmi->phy_enabled = true;
+       return 0;
+ }
+ static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi)
+ {
+       u8 de;
+       if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
+               de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
+       else
+               de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
+       /* disable rx detect */
+       hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
+                 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
+       hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
+       hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
+                 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
+ }
+ static void hdmi_config_AVI(struct imx_hdmi *hdmi)
+ {
+       u8 val, pix_fmt, under_scan;
+       u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
+       bool aspect_16_9;
+       aspect_16_9 = false; /* FIXME */
+       /* AVI Data Byte 1 */
+       if (hdmi->hdmi_data.enc_out_format == YCBCR444)
+               pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
+       else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
+               pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
+       else
+               pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
+               under_scan =  HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
+       /*
+        * Active format identification data is present in the AVI InfoFrame.
+        * Under scan info, no bar data
+        */
+       val = pix_fmt | under_scan |
+               HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
+               HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
+       hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
+       /* AVI Data Byte 2 -Set the Aspect Ratio */
+       if (aspect_16_9) {
+               act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
+               coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
+       } else {
+               act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
+               coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
+       }
+       /* Set up colorimetry */
+       if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
+               colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
+               if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
+                       ext_colorimetry =
+                               HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
+               else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
+                       ext_colorimetry =
+                               HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
+       } else if (hdmi->hdmi_data.enc_out_format != RGB) {
+               if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
+                       colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
+               else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
+                       colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
+               ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
+       } else { /* Carries no data */
+               colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
+               ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
+       }
+       val = colorimetry | coded_ratio | act_ratio;
+       hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
+       /* AVI Data Byte 3 */
+       val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
+               HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
+               HDMI_FC_AVICONF2_SCALING_NONE;
+       hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
+       /* AVI Data Byte 4 */
+       hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
+       /* AVI Data Byte 5- set up input and output pixel repetition */
+       val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
+               HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
+               HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
+               ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
+               HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
+               HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
+       hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
+       /* IT Content and quantization range = don't care */
+       val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
+               HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
+       hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
+       /* AVI Data Bytes 6-13 */
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
+       hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
+ }
+ static void hdmi_av_composer(struct imx_hdmi *hdmi,
+                            const struct drm_display_mode *mode)
+ {
+       u8 inv_val;
+       struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
+       int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
+       vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
+       vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
+       vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+       vmode->mpixelclock = mode->clock * 1000;
+       dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
+       /* Set up HDMI_FC_INVIDCONF */
+       inv_val = (hdmi->hdmi_data.hdcp_enable ?
+               HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
+               HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
+       inv_val |= (vmode->mvsyncpolarity ?
+               HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
+               HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
+       inv_val |= (vmode->mhsyncpolarity ?
+               HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
+               HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
+       inv_val |= (vmode->mdataenablepolarity ?
+               HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
+               HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
+       if (hdmi->vic == 39)
+               inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
+       else
+               inv_val |= (vmode->minterlaced ?
+                       HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
+                       HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
+       inv_val |= (vmode->minterlaced ?
+               HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
+               HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
+       inv_val |= (vmode->mdvi ?
+               HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
+               HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
+       hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
+       /* Set up horizontal active pixel width */
+       hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
+       hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
+       /* Set up vertical active lines */
+       hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
+       hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
+       /* Set up horizontal blanking pixel region width */
+       hblank = mode->htotal - mode->hdisplay;
+       hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
+       hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
+       /* Set up vertical blanking pixel region width */
+       vblank = mode->vtotal - mode->vdisplay;
+       hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
+       /* Set up HSYNC active edge delay width (in pixel clks) */
+       h_de_hs = mode->hsync_start - mode->hdisplay;
+       hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
+       hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
+       /* Set up VSYNC active edge delay (in lines) */
+       v_de_vs = mode->vsync_start - mode->vdisplay;
+       hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
+       /* Set up HSYNC active pulse width (in pixel clks) */
+       hsync_len = mode->hsync_end - mode->hsync_start;
+       hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
+       hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
+       /* Set up VSYNC active edge delay (in lines) */
+       vsync_len = mode->vsync_end - mode->vsync_start;
+       hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
+ }
+ static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi)
+ {
+       if (!hdmi->phy_enabled)
+               return;
+       imx_hdmi_phy_enable_tmds(hdmi, 0);
+       imx_hdmi_phy_enable_power(hdmi, 0);
+       hdmi->phy_enabled = false;
+ }
+ /* HDMI Initialization Step B.4 */
+ static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi)
+ {
+       u8 clkdis;
+       /* control period minimum duration */
+       hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
+       hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
+       hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
+       /* Set to fill TMDS data channels */
+       hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
+       hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
+       hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
+       /* Enable pixel clock and tmds data path */
+       clkdis = 0x7F;
+       clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
+       hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
+       clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
+       hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
+       /* Enable csc path */
+       if (is_color_space_conversion(hdmi)) {
+               clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
+               hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
+       }
+ }
+ static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi)
+ {
+       hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
+ }
+ /* Workaround to clear the overflow condition */
+ static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi)
+ {
+       int count;
+       u8 val;
+       /* TMDS software reset */
+       hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
+       val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
+       if (hdmi->dev_type == IMX6DL_HDMI) {
+               hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
+               return;
+       }
+       for (count = 0; count < 4; count++)
+               hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
+ }
+ static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi)
+ {
+       hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
+       hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
+ }
+ static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi)
+ {
+       hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
+                   HDMI_IH_MUTE_FC_STAT2);
+ }
+ static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode)
+ {
+       int ret;
+       hdmi_disable_overflow_interrupts(hdmi);
+       hdmi->vic = drm_match_cea_mode(mode);
+       if (!hdmi->vic) {
+               dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
+               hdmi->hdmi_data.video_mode.mdvi = true;
+       } else {
+               dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
+               hdmi->hdmi_data.video_mode.mdvi = false;
+       }
+       if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
+               (hdmi->vic == 21) || (hdmi->vic == 22) ||
+               (hdmi->vic == 2) || (hdmi->vic == 3) ||
+               (hdmi->vic == 17) || (hdmi->vic == 18))
+               hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
+       else
+               hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
+       if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
+               (hdmi->vic == 12) || (hdmi->vic == 13) ||
+               (hdmi->vic == 14) || (hdmi->vic == 15) ||
+               (hdmi->vic == 25) || (hdmi->vic == 26) ||
+               (hdmi->vic == 27) || (hdmi->vic == 28) ||
+               (hdmi->vic == 29) || (hdmi->vic == 30) ||
+               (hdmi->vic == 35) || (hdmi->vic == 36) ||
+               (hdmi->vic == 37) || (hdmi->vic == 38))
+               hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
+       else
+               hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
+       hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
+       /* TODO: Get input format from IPU (via FB driver interface) */
+       hdmi->hdmi_data.enc_in_format = RGB;
+       hdmi->hdmi_data.enc_out_format = RGB;
+       hdmi->hdmi_data.enc_color_depth = 8;
+       hdmi->hdmi_data.pix_repet_factor = 0;
+       hdmi->hdmi_data.hdcp_enable = 0;
+       hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
+       /* HDMI Initialization Step B.1 */
+       hdmi_av_composer(hdmi, mode);
+       /* HDMI Initializateion Step B.2 */
+       ret = imx_hdmi_phy_init(hdmi);
+       if (ret)
+               return ret;
+       /* HDMI Initialization Step B.3 */
+       imx_hdmi_enable_video_path(hdmi);
+       /* not for DVI mode */
+       if (hdmi->hdmi_data.video_mode.mdvi)
+               dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
+       else {
+               dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
+               /* HDMI Initialization Step E - Configure audio */
+               hdmi_clk_regenerator_update_pixel_clock(hdmi);
+               hdmi_enable_audio_clk(hdmi);
+               /* HDMI Initialization Step F - Configure AVI InfoFrame */
+               hdmi_config_AVI(hdmi);
+       }
+       hdmi_video_packetize(hdmi);
+       hdmi_video_csc(hdmi);
+       hdmi_video_sample(hdmi);
+       hdmi_tx_hdcp_config(hdmi);
+       imx_hdmi_clear_overflow(hdmi);
+       if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
+               hdmi_enable_overflow_interrupts(hdmi);
+       return 0;
+ }
+ /* Wait until we are registered to enable interrupts */
+ static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi)
+ {
+       hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
+                   HDMI_PHY_I2CM_INT_ADDR);
+       hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
+                   HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
+                   HDMI_PHY_I2CM_CTLINT_ADDR);
+       /* enable cable hot plug irq */
+       hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
+       /* Clear Hotplug interrupts */
+       hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+       return 0;
+ }
+ static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi)
+ {
+       u8 ih_mute;
+       /*
+        * Boot up defaults are:
+        * HDMI_IH_MUTE   = 0x03 (disabled)
+        * HDMI_IH_MUTE_* = 0x00 (enabled)
+        *
+        * Disable top level interrupt bits in HDMI block
+        */
+       ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
+                 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+                 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
+       hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
+       /* by default mask all interrupts */
+       hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
+       hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
+       hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
+       hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
+       hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
+       hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
+       hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
+       hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
+       hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
+       hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
+       hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
+       hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
+       hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
+       hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
+       hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
+       /* Disable interrupts in the IH_MUTE_* registers */
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
+       hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
+       /* Enable top level interrupt bits in HDMI block */
+       ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
+                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
+       hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
+ }
+ static void imx_hdmi_poweron(struct imx_hdmi *hdmi)
+ {
+       imx_hdmi_setup(hdmi, &hdmi->previous_mode);
+ }
+ static void imx_hdmi_poweroff(struct imx_hdmi *hdmi)
+ {
+       imx_hdmi_phy_disable(hdmi);
+ }
+ static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector
+                                                       *connector, bool force)
+ {
+       struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
+                                            connector);
+       return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
+               connector_status_connected : connector_status_disconnected;
+ }
+ static int imx_hdmi_connector_get_modes(struct drm_connector *connector)
+ {
+       struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
+                                            connector);
+       struct edid *edid;
+       int ret;
+       if (!hdmi->ddc)
+               return 0;
+       edid = drm_get_edid(connector, hdmi->ddc);
+       if (edid) {
+               dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
+                       edid->width_cm, edid->height_cm);
+               drm_mode_connector_update_edid_property(connector, edid);
+               ret = drm_add_edid_modes(connector, edid);
+               kfree(edid);
+       } else {
+               dev_dbg(hdmi->dev, "failed to get edid\n");
+       }
+       return 0;
+ }
+ static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector
+                                                          *connector)
+ {
+       struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
+                                            connector);
+       return &hdmi->encoder;
+ }
+ static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+                       struct drm_display_mode *mode,
+                       struct drm_display_mode *adjusted_mode)
+ {
+       struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
+       imx_hdmi_setup(hdmi, mode);
+       /* Store the display mode for plugin/DKMS poweron events */
+       memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
+ }
+ static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
+                       const struct drm_display_mode *mode,
+                       struct drm_display_mode *adjusted_mode)
+ {
+       return true;
+ }
+ static void imx_hdmi_encoder_disable(struct drm_encoder *encoder)
+ {
+ }
+ static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
+ {
+       struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
+       if (mode)
+               imx_hdmi_poweroff(hdmi);
+       else
+               imx_hdmi_poweron(hdmi);
+ }
+ static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
+ {
+       struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
+       imx_hdmi_poweroff(hdmi);
+       imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24);
+ }
+ static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
+ {
+       struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
+       int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
+       imx_hdmi_set_ipu_di_mux(hdmi, mux);
+       imx_hdmi_poweron(hdmi);
+ }
+ static struct drm_encoder_funcs imx_hdmi_encoder_funcs = {
+       .destroy = imx_drm_encoder_destroy,
+ };
+ static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = {
+       .dpms = imx_hdmi_encoder_dpms,
+       .prepare = imx_hdmi_encoder_prepare,
+       .commit = imx_hdmi_encoder_commit,
+       .mode_set = imx_hdmi_encoder_mode_set,
+       .mode_fixup = imx_hdmi_encoder_mode_fixup,
+       .disable = imx_hdmi_encoder_disable,
+ };
+ static struct drm_connector_funcs imx_hdmi_connector_funcs = {
+       .dpms = drm_helper_connector_dpms,
+       .fill_modes = drm_helper_probe_single_connector_modes,
+       .detect = imx_hdmi_connector_detect,
+       .destroy = imx_drm_connector_destroy,
+ };
+ static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = {
+       .get_modes = imx_hdmi_connector_get_modes,
+       .best_encoder = imx_hdmi_connector_best_encoder,
+ };
+ static irqreturn_t imx_hdmi_hardirq(int irq, void *dev_id)
+ {
+       struct imx_hdmi *hdmi = dev_id;
+       u8 intr_stat;
+       intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
+       if (intr_stat)
+               hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
+       return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
+ }
+ static irqreturn_t imx_hdmi_irq(int irq, void *dev_id)
+ {
+       struct imx_hdmi *hdmi = dev_id;
+       u8 intr_stat;
+       u8 phy_int_pol;
+       intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
+       phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
+       if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
+               if (phy_int_pol & HDMI_PHY_HPD) {
+                       dev_dbg(hdmi->dev, "EVENT=plugin\n");
+                       hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
+                       imx_hdmi_poweron(hdmi);
+               } else {
+                       dev_dbg(hdmi->dev, "EVENT=plugout\n");
+                       hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
+                               HDMI_PHY_POL0);
+                       imx_hdmi_poweroff(hdmi);
+               }
+               drm_helper_hpd_irq_event(hdmi->connector.dev);
+       }
+       hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
+       hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
+       return IRQ_HANDLED;
+ }
+ static int imx_hdmi_register(struct drm_device *drm, struct imx_hdmi *hdmi)
+ {
+       int ret;
+       ret = imx_drm_encoder_parse_of(drm, &hdmi->encoder,
+                                      hdmi->dev->of_node);
+       if (ret)
+               return ret;
+       hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
+       drm_encoder_helper_add(&hdmi->encoder, &imx_hdmi_encoder_helper_funcs);
+       drm_encoder_init(drm, &hdmi->encoder, &imx_hdmi_encoder_funcs,
+                        DRM_MODE_ENCODER_TMDS);
+       drm_connector_helper_add(&hdmi->connector,
+                       &imx_hdmi_connector_helper_funcs);
+       drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs,
+                          DRM_MODE_CONNECTOR_HDMIA);
+       hdmi->connector.encoder = &hdmi->encoder;
+       drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
+       return 0;
+ }
+ static struct platform_device_id imx_hdmi_devtype[] = {
+       {
+               .name = "imx6q-hdmi",
+               .driver_data = IMX6Q_HDMI,
+       }, {
+               .name = "imx6dl-hdmi",
+               .driver_data = IMX6DL_HDMI,
+       }, { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
+ static const struct of_device_id imx_hdmi_dt_ids[] = {
+ { .compatible = "fsl,imx6q-hdmi", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
+ { .compatible = "fsl,imx6dl-hdmi", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
+ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
+ {
+       struct platform_device *pdev = to_platform_device(dev);
+       const struct of_device_id *of_id =
+                               of_match_device(imx_hdmi_dt_ids, dev);
+       struct drm_device *drm = data;
+       struct device_node *np = dev->of_node;
+       struct device_node *ddc_node;
+       struct imx_hdmi *hdmi;
+       struct resource *iores;
+       int ret, irq;
+       hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
+       if (!hdmi)
+               return -ENOMEM;
+       hdmi->dev = dev;
+       hdmi->sample_rate = 48000;
+       hdmi->ratio = 100;
+       if (of_id) {
+               const struct platform_device_id *device_id = of_id->data;
+               hdmi->dev_type = device_id->driver_data;
+       }
+       ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
+       if (ddc_node) {
+               hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
+               if (!hdmi->ddc)
+                       dev_dbg(hdmi->dev, "failed to read ddc node\n");
+               of_node_put(ddc_node);
+       } else {
+               dev_dbg(hdmi->dev, "no ddc property found\n");
+       }
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0)
+               return irq;
+       ret = devm_request_threaded_irq(dev, irq, imx_hdmi_hardirq,
+                                       imx_hdmi_irq, IRQF_SHARED,
+                                       dev_name(dev), hdmi);
+       if (ret)
+               return ret;
+       iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       hdmi->regs = devm_ioremap_resource(dev, iores);
+       if (IS_ERR(hdmi->regs))
+               return PTR_ERR(hdmi->regs);
+       hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
+       if (IS_ERR(hdmi->regmap))
+               return PTR_ERR(hdmi->regmap);
+       hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
+       if (IS_ERR(hdmi->isfr_clk)) {
+               ret = PTR_ERR(hdmi->isfr_clk);
+               dev_err(hdmi->dev,
+                       "Unable to get HDMI isfr clk: %d\n", ret);
+               return ret;
+       }
+       ret = clk_prepare_enable(hdmi->isfr_clk);
+       if (ret) {
+               dev_err(hdmi->dev,
+                       "Cannot enable HDMI isfr clock: %d\n", ret);
+               return ret;
+       }
+       hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
+       if (IS_ERR(hdmi->iahb_clk)) {
+               ret = PTR_ERR(hdmi->iahb_clk);
+               dev_err(hdmi->dev,
+                       "Unable to get HDMI iahb clk: %d\n", ret);
+               goto err_isfr;
+       }
+       ret = clk_prepare_enable(hdmi->iahb_clk);
+       if (ret) {
+               dev_err(hdmi->dev,
+                       "Cannot enable HDMI iahb clock: %d\n", ret);
+               goto err_isfr;
+       }
+       /* Product and revision IDs */
+       dev_info(dev,
+               "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
+               hdmi_readb(hdmi, HDMI_DESIGN_ID),
+               hdmi_readb(hdmi, HDMI_REVISION_ID),
+               hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
+               hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
+       initialize_hdmi_ih_mutes(hdmi);
+       /*
+        * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
+        * N and cts values before enabling phy
+        */
+       hdmi_init_clk_regenerator(hdmi);
+       /*
+        * Configure registers related to HDMI interrupt
+        * generation before registering IRQ.
+        */
+       hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
+       /* Clear Hotplug interrupts */
+       hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+       ret = imx_hdmi_fb_registered(hdmi);
+       if (ret)
+               goto err_iahb;
+       ret = imx_hdmi_register(drm, hdmi);
+       if (ret)
+               goto err_iahb;
+       /* Unmute interrupts */
+       hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
+       dev_set_drvdata(dev, hdmi);
+       return 0;
+ err_iahb:
+       clk_disable_unprepare(hdmi->iahb_clk);
+ err_isfr:
+       clk_disable_unprepare(hdmi->isfr_clk);
+       return ret;
+ }
+ static void imx_hdmi_unbind(struct device *dev, struct device *master,
+       void *data)
+ {
+       struct imx_hdmi *hdmi = dev_get_drvdata(dev);
+       /* Disable all interrupts */
+       hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
+       hdmi->connector.funcs->destroy(&hdmi->connector);
+       hdmi->encoder.funcs->destroy(&hdmi->encoder);
+       clk_disable_unprepare(hdmi->iahb_clk);
+       clk_disable_unprepare(hdmi->isfr_clk);
+       i2c_put_adapter(hdmi->ddc);
+ }
+ static const struct component_ops hdmi_ops = {
+       .bind   = imx_hdmi_bind,
+       .unbind = imx_hdmi_unbind,
+ };
+ static int imx_hdmi_platform_probe(struct platform_device *pdev)
+ {
+       return component_add(&pdev->dev, &hdmi_ops);
+ }
+ static int imx_hdmi_platform_remove(struct platform_device *pdev)
+ {
+       component_del(&pdev->dev, &hdmi_ops);
+       return 0;
+ }
+ static struct platform_driver imx_hdmi_driver = {
+       .probe  = imx_hdmi_platform_probe,
+       .remove = imx_hdmi_platform_remove,
+       .driver = {
+               .name = "imx-hdmi",
+               .of_match_table = imx_hdmi_dt_ids,
+       },
+ };
+ module_platform_driver(imx_hdmi_driver);
+ MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+ MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver");
+ MODULE_LICENSE("GPL");
+ MODULE_ALIAS("platform:imx-hdmi");
index 0000000000000000000000000000000000000000,4662e00b456a25d4c08b755bc68b6bdbf37e8ed2..2638dc1671d0a60126e9c8c6bf011556a92ffd11
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,616 +1,615 @@@
 -              .owner  = THIS_MODULE,
+ /*
+  * i.MX drm driver - LVDS display bridge
+  *
+  * Copyright (C) 2012 Sascha Hauer, Pengutronix
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License
+  * as published by the Free Software Foundation; either version 2
+  * of the License, or (at your option) any later version.
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+  * MA 02110-1301, USA.
+  */
+ #include <linux/module.h>
+ #include <linux/clk.h>
+ #include <linux/component.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <video/of_videomode.h>
+ #include <linux/regmap.h>
+ #include <linux/videodev2.h>
+ #include "imx-drm.h"
+ #define DRIVER_NAME "imx-ldb"
+ #define LDB_CH0_MODE_EN_TO_DI0                (1 << 0)
+ #define LDB_CH0_MODE_EN_TO_DI1                (3 << 0)
+ #define LDB_CH0_MODE_EN_MASK          (3 << 0)
+ #define LDB_CH1_MODE_EN_TO_DI0                (1 << 2)
+ #define LDB_CH1_MODE_EN_TO_DI1                (3 << 2)
+ #define LDB_CH1_MODE_EN_MASK          (3 << 2)
+ #define LDB_SPLIT_MODE_EN             (1 << 4)
+ #define LDB_DATA_WIDTH_CH0_24         (1 << 5)
+ #define LDB_BIT_MAP_CH0_JEIDA         (1 << 6)
+ #define LDB_DATA_WIDTH_CH1_24         (1 << 7)
+ #define LDB_BIT_MAP_CH1_JEIDA         (1 << 8)
+ #define LDB_DI0_VS_POL_ACT_LOW                (1 << 9)
+ #define LDB_DI1_VS_POL_ACT_LOW                (1 << 10)
+ #define LDB_BGREF_RMODE_INT           (1 << 15)
+ #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
+ #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
+ struct imx_ldb;
+ struct imx_ldb_channel {
+       struct imx_ldb *ldb;
+       struct drm_connector connector;
+       struct drm_encoder encoder;
+       struct device_node *child;
+       int chno;
+       void *edid;
+       int edid_len;
+       struct drm_display_mode mode;
+       int mode_valid;
+ };
+ struct bus_mux {
+       int reg;
+       int shift;
+       int mask;
+ };
+ struct imx_ldb {
+       struct regmap *regmap;
+       struct device *dev;
+       struct imx_ldb_channel channel[2];
+       struct clk *clk[2]; /* our own clock */
+       struct clk *clk_sel[4]; /* parent of display clock */
+       struct clk *clk_pll[2]; /* upstream clock we can adjust */
+       u32 ldb_ctrl;
+       const struct bus_mux *lvds_mux;
+ };
+ static enum drm_connector_status imx_ldb_connector_detect(
+               struct drm_connector *connector, bool force)
+ {
+       return connector_status_connected;
+ }
+ static int imx_ldb_connector_get_modes(struct drm_connector *connector)
+ {
+       struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
+       int num_modes = 0;
+       if (imx_ldb_ch->edid) {
+               drm_mode_connector_update_edid_property(connector,
+                                                       imx_ldb_ch->edid);
+               num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
+       }
+       if (imx_ldb_ch->mode_valid) {
+               struct drm_display_mode *mode;
+               mode = drm_mode_create(connector->dev);
+               if (!mode)
+                       return -EINVAL;
+               drm_mode_copy(mode, &imx_ldb_ch->mode);
+               mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+               drm_mode_probed_add(connector, mode);
+               num_modes++;
+       }
+       return num_modes;
+ }
+ static struct drm_encoder *imx_ldb_connector_best_encoder(
+               struct drm_connector *connector)
+ {
+       struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
+       return &imx_ldb_ch->encoder;
+ }
+ static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
+ {
+ }
+ static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
+                          const struct drm_display_mode *mode,
+                          struct drm_display_mode *adjusted_mode)
+ {
+       return true;
+ }
+ static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
+               unsigned long serial_clk, unsigned long di_clk)
+ {
+       int ret;
+       dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
+                       clk_get_rate(ldb->clk_pll[chno]), serial_clk);
+       clk_set_rate(ldb->clk_pll[chno], serial_clk);
+       dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
+                       clk_get_rate(ldb->clk_pll[chno]));
+       dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
+                       clk_get_rate(ldb->clk[chno]),
+                       (long int)di_clk);
+       clk_set_rate(ldb->clk[chno], di_clk);
+       dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
+                       clk_get_rate(ldb->clk[chno]));
+       /* set display clock mux to LDB input clock */
+       ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
+       if (ret)
+               dev_err(ldb->dev,
+                       "unable to set di%d parent clock to ldb_di%d\n", mux,
+                       chno);
+ }
+ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
+ {
+       struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+       struct imx_ldb *ldb = imx_ldb_ch->ldb;
+       struct drm_display_mode *mode = &encoder->crtc->mode;
+       u32 pixel_fmt;
+       unsigned long serial_clk;
+       unsigned long di_clk = mode->clock * 1000;
+       int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
+       if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
+               /* dual channel LVDS mode */
+               serial_clk = 3500UL * mode->clock;
+               imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
+               imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
+       } else {
+               serial_clk = 7000UL * mode->clock;
+               imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
+                               di_clk);
+       }
+       switch (imx_ldb_ch->chno) {
+       case 0:
+               pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
+                       V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
+               break;
+       case 1:
+               pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
+                       V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
+               break;
+       default:
+               dev_err(ldb->dev, "unable to config di%d panel format\n",
+                       imx_ldb_ch->chno);
+               pixel_fmt = V4L2_PIX_FMT_RGB24;
+       }
+       imx_drm_panel_format(encoder, pixel_fmt);
+ }
+ static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
+ {
+       struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+       struct imx_ldb *ldb = imx_ldb_ch->ldb;
+       int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+       int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
+       if (dual) {
+               clk_prepare_enable(ldb->clk[0]);
+               clk_prepare_enable(ldb->clk[1]);
+       }
+       if (imx_ldb_ch == &ldb->channel[0] || dual) {
+               ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+               if (mux == 0 || ldb->lvds_mux)
+                       ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
+               else if (mux == 1)
+                       ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
+       }
+       if (imx_ldb_ch == &ldb->channel[1] || dual) {
+               ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+               if (mux == 1 || ldb->lvds_mux)
+                       ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
+               else if (mux == 0)
+                       ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
+       }
+       if (ldb->lvds_mux) {
+               const struct bus_mux *lvds_mux = NULL;
+               if (imx_ldb_ch == &ldb->channel[0])
+                       lvds_mux = &ldb->lvds_mux[0];
+               else if (imx_ldb_ch == &ldb->channel[1])
+                       lvds_mux = &ldb->lvds_mux[1];
+               regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
+                                  mux << lvds_mux->shift);
+       }
+       regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
+ }
+ static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
+                        struct drm_display_mode *mode,
+                        struct drm_display_mode *adjusted_mode)
+ {
+       struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+       struct imx_ldb *ldb = imx_ldb_ch->ldb;
+       int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
+       if (mode->clock > 170000) {
+               dev_warn(ldb->dev,
+                        "%s: mode exceeds 170 MHz pixel clock\n", __func__);
+       }
+       if (mode->clock > 85000 && !dual) {
+               dev_warn(ldb->dev,
+                        "%s: mode exceeds 85 MHz pixel clock\n", __func__);
+       }
+       /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
+       if (imx_ldb_ch == &ldb->channel[0]) {
+               if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+                       ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
+               else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+                       ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
+       }
+       if (imx_ldb_ch == &ldb->channel[1]) {
+               if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+                       ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
+               else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+                       ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
+       }
+ }
+ static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
+ {
+       struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
+       struct imx_ldb *ldb = imx_ldb_ch->ldb;
+       /*
+        * imx_ldb_encoder_disable is called by
+        * drm_helper_disable_unused_functions without
+        * the encoder being enabled before.
+        */
+       if (imx_ldb_ch == &ldb->channel[0] &&
+           (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
+               return;
+       else if (imx_ldb_ch == &ldb->channel[1] &&
+                (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
+               return;
+       if (imx_ldb_ch == &ldb->channel[0])
+               ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+       else if (imx_ldb_ch == &ldb->channel[1])
+               ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+       regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
+       if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
+               clk_disable_unprepare(ldb->clk[0]);
+               clk_disable_unprepare(ldb->clk[1]);
+       }
+ }
+ static struct drm_connector_funcs imx_ldb_connector_funcs = {
+       .dpms = drm_helper_connector_dpms,
+       .fill_modes = drm_helper_probe_single_connector_modes,
+       .detect = imx_ldb_connector_detect,
+       .destroy = imx_drm_connector_destroy,
+ };
+ static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
+       .get_modes = imx_ldb_connector_get_modes,
+       .best_encoder = imx_ldb_connector_best_encoder,
+ };
+ static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
+       .destroy = imx_drm_encoder_destroy,
+ };
+ static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
+       .dpms = imx_ldb_encoder_dpms,
+       .mode_fixup = imx_ldb_encoder_mode_fixup,
+       .prepare = imx_ldb_encoder_prepare,
+       .commit = imx_ldb_encoder_commit,
+       .mode_set = imx_ldb_encoder_mode_set,
+       .disable = imx_ldb_encoder_disable,
+ };
+ static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
+ {
+       char clkname[16];
+       snprintf(clkname, sizeof(clkname), "di%d", chno);
+       ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
+       if (IS_ERR(ldb->clk[chno]))
+               return PTR_ERR(ldb->clk[chno]);
+       snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
+       ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
+       return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
+ }
+ static int imx_ldb_register(struct drm_device *drm,
+       struct imx_ldb_channel *imx_ldb_ch)
+ {
+       struct imx_ldb *ldb = imx_ldb_ch->ldb;
+       int ret;
+       ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
+                                      imx_ldb_ch->child);
+       if (ret)
+               return ret;
+       ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
+       if (ret)
+               return ret;
+       if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
+               ret = imx_ldb_get_clk(ldb, 1);
+               if (ret)
+                       return ret;
+       }
+       drm_encoder_helper_add(&imx_ldb_ch->encoder,
+                       &imx_ldb_encoder_helper_funcs);
+       drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
+                        DRM_MODE_ENCODER_LVDS);
+       drm_connector_helper_add(&imx_ldb_ch->connector,
+                       &imx_ldb_connector_helper_funcs);
+       drm_connector_init(drm, &imx_ldb_ch->connector,
+                          &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
+       drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
+                       &imx_ldb_ch->encoder);
+       return 0;
+ }
+ enum {
+       LVDS_BIT_MAP_SPWG,
+       LVDS_BIT_MAP_JEIDA
+ };
+ static const char * const imx_ldb_bit_mappings[] = {
+       [LVDS_BIT_MAP_SPWG]  = "spwg",
+       [LVDS_BIT_MAP_JEIDA] = "jeida",
+ };
+ static const int of_get_data_mapping(struct device_node *np)
+ {
+       const char *bm;
+       int ret, i;
+       ret = of_property_read_string(np, "fsl,data-mapping", &bm);
+       if (ret < 0)
+               return ret;
+       for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
+               if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
+                       return i;
+       return -EINVAL;
+ }
+ static struct bus_mux imx6q_lvds_mux[2] = {
+       {
+               .reg = IOMUXC_GPR3,
+               .shift = 6,
+               .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
+       }, {
+               .reg = IOMUXC_GPR3,
+               .shift = 8,
+               .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
+       }
+ };
+ /*
+  * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
+  * of_match_device will walk through this list and take the first entry
+  * matching any of its compatible values. Therefore, the more generic
+  * entries (in this case fsl,imx53-ldb) need to be ordered last.
+  */
+ static const struct of_device_id imx_ldb_dt_ids[] = {
+       { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
+       { .compatible = "fsl,imx53-ldb", .data = NULL, },
+       { }
+ };
+ MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
+ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
+ {
+       struct drm_device *drm = data;
+       struct device_node *np = dev->of_node;
+       const struct of_device_id *of_id =
+                       of_match_device(imx_ldb_dt_ids, dev);
+       struct device_node *child;
+       const u8 *edidp;
+       struct imx_ldb *imx_ldb;
+       int datawidth;
+       int mapping;
+       int dual;
+       int ret;
+       int i;
+       imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
+       if (!imx_ldb)
+               return -ENOMEM;
+       imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
+       if (IS_ERR(imx_ldb->regmap)) {
+               dev_err(dev, "failed to get parent regmap\n");
+               return PTR_ERR(imx_ldb->regmap);
+       }
+       imx_ldb->dev = dev;
+       if (of_id)
+               imx_ldb->lvds_mux = of_id->data;
+       dual = of_property_read_bool(np, "fsl,dual-channel");
+       if (dual)
+               imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
+       /*
+        * There are three different possible clock mux configurations:
+        * i.MX53:  ipu1_di0_sel, ipu1_di1_sel
+        * i.MX6q:  ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
+        * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
+        * Map them all to di0_sel...di3_sel.
+        */
+       for (i = 0; i < 4; i++) {
+               char clkname[16];
+               sprintf(clkname, "di%d_sel", i);
+               imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
+               if (IS_ERR(imx_ldb->clk_sel[i])) {
+                       ret = PTR_ERR(imx_ldb->clk_sel[i]);
+                       imx_ldb->clk_sel[i] = NULL;
+                       break;
+               }
+       }
+       if (i == 0)
+               return ret;
+       for_each_child_of_node(np, child) {
+               struct imx_ldb_channel *channel;
+               ret = of_property_read_u32(child, "reg", &i);
+               if (ret || i < 0 || i > 1)
+                       return -EINVAL;
+               if (dual && i > 0) {
+                       dev_warn(dev, "dual-channel mode, ignoring second output\n");
+                       continue;
+               }
+               if (!of_device_is_available(child))
+                       continue;
+               channel = &imx_ldb->channel[i];
+               channel->ldb = imx_ldb;
+               channel->chno = i;
+               channel->child = child;
+               edidp = of_get_property(child, "edid", &channel->edid_len);
+               if (edidp) {
+                       channel->edid = kmemdup(edidp, channel->edid_len,
+                                               GFP_KERNEL);
+               } else {
+                       ret = of_get_drm_display_mode(child, &channel->mode, 0);
+                       if (!ret)
+                               channel->mode_valid = 1;
+               }
+               ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
+               if (ret)
+                       datawidth = 0;
+               else if (datawidth != 18 && datawidth != 24)
+                       return -EINVAL;
+               mapping = of_get_data_mapping(child);
+               switch (mapping) {
+               case LVDS_BIT_MAP_SPWG:
+                       if (datawidth == 24) {
+                               if (i == 0 || dual)
+                                       imx_ldb->ldb_ctrl |=
+                                               LDB_DATA_WIDTH_CH0_24;
+                               if (i == 1 || dual)
+                                       imx_ldb->ldb_ctrl |=
+                                               LDB_DATA_WIDTH_CH1_24;
+                       }
+                       break;
+               case LVDS_BIT_MAP_JEIDA:
+                       if (datawidth == 18) {
+                               dev_err(dev, "JEIDA standard only supported in 24 bit\n");
+                               return -EINVAL;
+                       }
+                       if (i == 0 || dual)
+                               imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
+                                       LDB_BIT_MAP_CH0_JEIDA;
+                       if (i == 1 || dual)
+                               imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
+                                       LDB_BIT_MAP_CH1_JEIDA;
+                       break;
+               default:
+                       dev_err(dev, "data mapping not specified or invalid\n");
+                       return -EINVAL;
+               }
+               ret = imx_ldb_register(drm, channel);
+               if (ret)
+                       return ret;
+       }
+       dev_set_drvdata(dev, imx_ldb);
+       return 0;
+ }
+ static void imx_ldb_unbind(struct device *dev, struct device *master,
+       void *data)
+ {
+       struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
+       int i;
+       for (i = 0; i < 2; i++) {
+               struct imx_ldb_channel *channel = &imx_ldb->channel[i];
+               if (!channel->connector.funcs)
+                       continue;
+               channel->connector.funcs->destroy(&channel->connector);
+               channel->encoder.funcs->destroy(&channel->encoder);
+       }
+ }
+ static const struct component_ops imx_ldb_ops = {
+       .bind   = imx_ldb_bind,
+       .unbind = imx_ldb_unbind,
+ };
+ static int imx_ldb_probe(struct platform_device *pdev)
+ {
+       return component_add(&pdev->dev, &imx_ldb_ops);
+ }
+ static int imx_ldb_remove(struct platform_device *pdev)
+ {
+       component_del(&pdev->dev, &imx_ldb_ops);
+       return 0;
+ }
+ static struct platform_driver imx_ldb_driver = {
+       .probe          = imx_ldb_probe,
+       .remove         = imx_ldb_remove,
+       .driver         = {
+               .of_match_table = imx_ldb_dt_ids,
+               .name   = DRIVER_NAME,
+       },
+ };
+ module_platform_driver(imx_ldb_driver);
+ MODULE_DESCRIPTION("i.MX LVDS driver");
+ MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+ MODULE_LICENSE("GPL");
+ MODULE_ALIAS("platform:" DRIVER_NAME);
index 0000000000000000000000000000000000000000,42c651be6c2068955df736c05520d1765cad8773..64b54d7f996cbd2ebf331a2e09b44a26f69bbde4
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,736 +1,735 @@@
 -              .owner  = THIS_MODULE,
+ /*
+  * i.MX drm driver - Television Encoder (TVEv2)
+  *
+  * Copyright (C) 2013 Philipp Zabel, Pengutronix
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License
+  * as published by the Free Software Foundation; either version 2
+  * of the License, or (at your option) any later version.
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+  * MA 02110-1301, USA.
+  */
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+ #include <linux/component.h>
+ #include <linux/module.h>
+ #include <linux/i2c.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/spinlock.h>
+ #include <linux/videodev2.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <video/imx-ipu-v3.h>
+ #include "imx-drm.h"
+ #define TVE_COM_CONF_REG      0x00
+ #define TVE_TVDAC0_CONT_REG   0x28
+ #define TVE_TVDAC1_CONT_REG   0x2c
+ #define TVE_TVDAC2_CONT_REG   0x30
+ #define TVE_CD_CONT_REG               0x34
+ #define TVE_INT_CONT_REG      0x64
+ #define TVE_STAT_REG          0x68
+ #define TVE_TST_MODE_REG      0x6c
+ #define TVE_MV_CONT_REG               0xdc
+ /* TVE_COM_CONF_REG */
+ #define TVE_SYNC_CH_2_EN      BIT(22)
+ #define TVE_SYNC_CH_1_EN      BIT(21)
+ #define TVE_SYNC_CH_0_EN      BIT(20)
+ #define TVE_TV_OUT_MODE_MASK  (0x7 << 12)
+ #define TVE_TV_OUT_DISABLE    (0x0 << 12)
+ #define TVE_TV_OUT_CVBS_0     (0x1 << 12)
+ #define TVE_TV_OUT_CVBS_2     (0x2 << 12)
+ #define TVE_TV_OUT_CVBS_0_2   (0x3 << 12)
+ #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
+ #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
+ #define TVE_TV_OUT_YPBPR      (0x6 << 12)
+ #define TVE_TV_OUT_RGB                (0x7 << 12)
+ #define TVE_TV_STAND_MASK     (0xf << 8)
+ #define TVE_TV_STAND_HD_1080P30       (0xc << 8)
+ #define TVE_P2I_CONV_EN               BIT(7)
+ #define TVE_INP_VIDEO_FORM    BIT(6)
+ #define TVE_INP_YCBCR_422     (0x0 << 6)
+ #define TVE_INP_YCBCR_444     (0x1 << 6)
+ #define TVE_DATA_SOURCE_MASK  (0x3 << 4)
+ #define TVE_DATA_SOURCE_BUS1  (0x0 << 4)
+ #define TVE_DATA_SOURCE_BUS2  (0x1 << 4)
+ #define TVE_DATA_SOURCE_EXT   (0x2 << 4)
+ #define TVE_DATA_SOURCE_TESTGEN       (0x3 << 4)
+ #define TVE_IPU_CLK_EN_OFS    3
+ #define TVE_IPU_CLK_EN                BIT(3)
+ #define TVE_DAC_SAMP_RATE_OFS 1
+ #define TVE_DAC_SAMP_RATE_WIDTH       2
+ #define TVE_DAC_SAMP_RATE_MASK        (0x3 << 1)
+ #define TVE_DAC_FULL_RATE     (0x0 << 1)
+ #define TVE_DAC_DIV2_RATE     (0x1 << 1)
+ #define TVE_DAC_DIV4_RATE     (0x2 << 1)
+ #define TVE_EN                        BIT(0)
+ /* TVE_TVDACx_CONT_REG */
+ #define TVE_TVDAC_GAIN_MASK   (0x3f << 0)
+ /* TVE_CD_CONT_REG */
+ #define TVE_CD_CH_2_SM_EN     BIT(22)
+ #define TVE_CD_CH_1_SM_EN     BIT(21)
+ #define TVE_CD_CH_0_SM_EN     BIT(20)
+ #define TVE_CD_CH_2_LM_EN     BIT(18)
+ #define TVE_CD_CH_1_LM_EN     BIT(17)
+ #define TVE_CD_CH_0_LM_EN     BIT(16)
+ #define TVE_CD_CH_2_REF_LVL   BIT(10)
+ #define TVE_CD_CH_1_REF_LVL   BIT(9)
+ #define TVE_CD_CH_0_REF_LVL   BIT(8)
+ #define TVE_CD_EN             BIT(0)
+ /* TVE_INT_CONT_REG */
+ #define TVE_FRAME_END_IEN     BIT(13)
+ #define TVE_CD_MON_END_IEN    BIT(2)
+ #define TVE_CD_SM_IEN         BIT(1)
+ #define TVE_CD_LM_IEN         BIT(0)
+ /* TVE_TST_MODE_REG */
+ #define TVE_TVDAC_TEST_MODE_MASK      (0x7 << 0)
+ #define con_to_tve(x) container_of(x, struct imx_tve, connector)
+ #define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
+ enum {
+       TVE_MODE_TVOUT,
+       TVE_MODE_VGA,
+ };
+ struct imx_tve {
+       struct drm_connector connector;
+       struct drm_encoder encoder;
+       struct device *dev;
+       spinlock_t lock;        /* register lock */
+       bool enabled;
+       int mode;
+       struct regmap *regmap;
+       struct regulator *dac_reg;
+       struct i2c_adapter *ddc;
+       struct clk *clk;
+       struct clk *di_sel_clk;
+       struct clk_hw clk_hw_di;
+       struct clk *di_clk;
+       int vsync_pin;
+       int hsync_pin;
+ };
+ static void tve_lock(void *__tve)
+ __acquires(&tve->lock)
+ {
+       struct imx_tve *tve = __tve;
+       spin_lock(&tve->lock);
+ }
+ static void tve_unlock(void *__tve)
+ __releases(&tve->lock)
+ {
+       struct imx_tve *tve = __tve;
+       spin_unlock(&tve->lock);
+ }
+ static void tve_enable(struct imx_tve *tve)
+ {
+       int ret;
+       if (!tve->enabled) {
+               tve->enabled = true;
+               clk_prepare_enable(tve->clk);
+               ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+                                        TVE_IPU_CLK_EN | TVE_EN,
+                                        TVE_IPU_CLK_EN | TVE_EN);
+       }
+       /* clear interrupt status register */
+       regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
+       /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
+       if (tve->mode == TVE_MODE_VGA)
+               regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
+       else
+               regmap_write(tve->regmap, TVE_INT_CONT_REG,
+                            TVE_CD_SM_IEN |
+                            TVE_CD_LM_IEN |
+                            TVE_CD_MON_END_IEN);
+ }
+ static void tve_disable(struct imx_tve *tve)
+ {
+       int ret;
+       if (tve->enabled) {
+               tve->enabled = false;
+               ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+                                        TVE_IPU_CLK_EN | TVE_EN, 0);
+               clk_disable_unprepare(tve->clk);
+       }
+ }
+ static int tve_setup_tvout(struct imx_tve *tve)
+ {
+       return -ENOTSUPP;
+ }
+ static int tve_setup_vga(struct imx_tve *tve)
+ {
+       unsigned int mask;
+       unsigned int val;
+       int ret;
+       /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
+       ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
+                                TVE_TVDAC_GAIN_MASK, 0x0a);
+       ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
+                                TVE_TVDAC_GAIN_MASK, 0x0a);
+       ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
+                                TVE_TVDAC_GAIN_MASK, 0x0a);
+       /* set configuration register */
+       mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
+       val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
+       mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
+       val  |= TVE_TV_STAND_HD_1080P30 | 0;
+       mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
+       val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
+       ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
+       if (ret < 0) {
+               dev_err(tve->dev, "failed to set configuration: %d\n", ret);
+               return ret;
+       }
+       /* set test mode (as documented) */
+       ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
+                                TVE_TVDAC_TEST_MODE_MASK, 1);
+       return 0;
+ }
+ static enum drm_connector_status imx_tve_connector_detect(
+                               struct drm_connector *connector, bool force)
+ {
+       return connector_status_connected;
+ }
+ static int imx_tve_connector_get_modes(struct drm_connector *connector)
+ {
+       struct imx_tve *tve = con_to_tve(connector);
+       struct edid *edid;
+       int ret = 0;
+       if (!tve->ddc)
+               return 0;
+       edid = drm_get_edid(connector, tve->ddc);
+       if (edid) {
+               drm_mode_connector_update_edid_property(connector, edid);
+               ret = drm_add_edid_modes(connector, edid);
+               kfree(edid);
+       }
+       return ret;
+ }
+ static int imx_tve_connector_mode_valid(struct drm_connector *connector,
+                                       struct drm_display_mode *mode)
+ {
+       struct imx_tve *tve = con_to_tve(connector);
+       unsigned long rate;
+       /* pixel clock with 2x oversampling */
+       rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
+       if (rate == mode->clock)
+               return MODE_OK;
+       /* pixel clock without oversampling */
+       rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
+       if (rate == mode->clock)
+               return MODE_OK;
+       dev_warn(tve->dev, "ignoring mode %dx%d\n",
+                mode->hdisplay, mode->vdisplay);
+       return MODE_BAD;
+ }
+ static struct drm_encoder *imx_tve_connector_best_encoder(
+               struct drm_connector *connector)
+ {
+       struct imx_tve *tve = con_to_tve(connector);
+       return &tve->encoder;
+ }
+ static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
+ {
+       struct imx_tve *tve = enc_to_tve(encoder);
+       int ret;
+       ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+                                TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
+       if (ret < 0)
+               dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
+ }
+ static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
+                                      const struct drm_display_mode *mode,
+                                      struct drm_display_mode *adjusted_mode)
+ {
+       return true;
+ }
+ static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
+ {
+       struct imx_tve *tve = enc_to_tve(encoder);
+       tve_disable(tve);
+       switch (tve->mode) {
+       case TVE_MODE_VGA:
+               imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
+                               tve->hsync_pin, tve->vsync_pin);
+               break;
+       case TVE_MODE_TVOUT:
+               imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
+               break;
+       }
+ }
+ static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
+                                    struct drm_display_mode *mode,
+                                    struct drm_display_mode *adjusted_mode)
+ {
+       struct imx_tve *tve = enc_to_tve(encoder);
+       unsigned long rounded_rate;
+       unsigned long rate;
+       int div = 1;
+       int ret;
+       /*
+        * FIXME
+        * we should try 4k * mode->clock first,
+        * and enable 4x oversampling for lower resolutions
+        */
+       rate = 2000UL * mode->clock;
+       clk_set_rate(tve->clk, rate);
+       rounded_rate = clk_get_rate(tve->clk);
+       if (rounded_rate >= rate)
+               div = 2;
+       clk_set_rate(tve->di_clk, rounded_rate / div);
+       ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
+       if (ret < 0) {
+               dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
+                       ret);
+       }
+       if (tve->mode == TVE_MODE_VGA)
+               tve_setup_vga(tve);
+       else
+               tve_setup_tvout(tve);
+ }
+ static void imx_tve_encoder_commit(struct drm_encoder *encoder)
+ {
+       struct imx_tve *tve = enc_to_tve(encoder);
+       tve_enable(tve);
+ }
+ static void imx_tve_encoder_disable(struct drm_encoder *encoder)
+ {
+       struct imx_tve *tve = enc_to_tve(encoder);
+       tve_disable(tve);
+ }
+ static struct drm_connector_funcs imx_tve_connector_funcs = {
+       .dpms = drm_helper_connector_dpms,
+       .fill_modes = drm_helper_probe_single_connector_modes,
+       .detect = imx_tve_connector_detect,
+       .destroy = imx_drm_connector_destroy,
+ };
+ static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
+       .get_modes = imx_tve_connector_get_modes,
+       .best_encoder = imx_tve_connector_best_encoder,
+       .mode_valid = imx_tve_connector_mode_valid,
+ };
+ static struct drm_encoder_funcs imx_tve_encoder_funcs = {
+       .destroy = imx_drm_encoder_destroy,
+ };
+ static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
+       .dpms = imx_tve_encoder_dpms,
+       .mode_fixup = imx_tve_encoder_mode_fixup,
+       .prepare = imx_tve_encoder_prepare,
+       .mode_set = imx_tve_encoder_mode_set,
+       .commit = imx_tve_encoder_commit,
+       .disable = imx_tve_encoder_disable,
+ };
+ static irqreturn_t imx_tve_irq_handler(int irq, void *data)
+ {
+       struct imx_tve *tve = data;
+       unsigned int val;
+       regmap_read(tve->regmap, TVE_STAT_REG, &val);
+       /* clear interrupt status register */
+       regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
+       return IRQ_HANDLED;
+ }
+ static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
+                                           unsigned long parent_rate)
+ {
+       struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
+       unsigned int val;
+       int ret;
+       ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
+       if (ret < 0)
+               return 0;
+       switch (val & TVE_DAC_SAMP_RATE_MASK) {
+       case TVE_DAC_DIV4_RATE:
+               return parent_rate / 4;
+       case TVE_DAC_DIV2_RATE:
+               return parent_rate / 2;
+       case TVE_DAC_FULL_RATE:
+       default:
+               return parent_rate;
+       }
+       return 0;
+ }
+ static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *prate)
+ {
+       unsigned long div;
+       div = *prate / rate;
+       if (div >= 4)
+               return *prate / 4;
+       else if (div >= 2)
+               return *prate / 2;
+       return *prate;
+ }
+ static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+ {
+       struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
+       unsigned long div;
+       u32 val;
+       int ret;
+       div = parent_rate / rate;
+       if (div >= 4)
+               val = TVE_DAC_DIV4_RATE;
+       else if (div >= 2)
+               val = TVE_DAC_DIV2_RATE;
+       else
+               val = TVE_DAC_FULL_RATE;
+       ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+                                TVE_DAC_SAMP_RATE_MASK, val);
+       if (ret < 0) {
+               dev_err(tve->dev, "failed to set divider: %d\n", ret);
+               return ret;
+       }
+       return 0;
+ }
+ static struct clk_ops clk_tve_di_ops = {
+       .round_rate = clk_tve_di_round_rate,
+       .set_rate = clk_tve_di_set_rate,
+       .recalc_rate = clk_tve_di_recalc_rate,
+ };
+ static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
+ {
+       const char *tve_di_parent[1];
+       struct clk_init_data init = {
+               .name = "tve_di",
+               .ops = &clk_tve_di_ops,
+               .num_parents = 1,
+               .flags = 0,
+       };
+       tve_di_parent[0] = __clk_get_name(tve->clk);
+       init.parent_names = (const char **)&tve_di_parent;
+       tve->clk_hw_di.init = &init;
+       tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
+       if (IS_ERR(tve->di_clk)) {
+               dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
+                       PTR_ERR(tve->di_clk));
+               return PTR_ERR(tve->di_clk);
+       }
+       return 0;
+ }
+ static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
+ {
+       int encoder_type;
+       int ret;
+       encoder_type = tve->mode == TVE_MODE_VGA ?
+                               DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
+       ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
+                                      tve->dev->of_node);
+       if (ret)
+               return ret;
+       drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
+       drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
+                        encoder_type);
+       drm_connector_helper_add(&tve->connector,
+                       &imx_tve_connector_helper_funcs);
+       drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
+                          DRM_MODE_CONNECTOR_VGA);
+       drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
+       return 0;
+ }
+ static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
+ {
+       return (reg % 4 == 0) && (reg <= 0xdc);
+ }
+ static struct regmap_config tve_regmap_config = {
+       .reg_bits = 32,
+       .val_bits = 32,
+       .reg_stride = 4,
+       .readable_reg = imx_tve_readable_reg,
+       .lock = tve_lock,
+       .unlock = tve_unlock,
+       .max_register = 0xdc,
+ };
+ static const char * const imx_tve_modes[] = {
+       [TVE_MODE_TVOUT]  = "tvout",
+       [TVE_MODE_VGA] = "vga",
+ };
+ static const int of_get_tve_mode(struct device_node *np)
+ {
+       const char *bm;
+       int ret, i;
+       ret = of_property_read_string(np, "fsl,tve-mode", &bm);
+       if (ret < 0)
+               return ret;
+       for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
+               if (!strcasecmp(bm, imx_tve_modes[i]))
+                       return i;
+       return -EINVAL;
+ }
+ static int imx_tve_bind(struct device *dev, struct device *master, void *data)
+ {
+       struct platform_device *pdev = to_platform_device(dev);
+       struct drm_device *drm = data;
+       struct device_node *np = dev->of_node;
+       struct device_node *ddc_node;
+       struct imx_tve *tve;
+       struct resource *res;
+       void __iomem *base;
+       unsigned int val;
+       int irq;
+       int ret;
+       tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
+       if (!tve)
+               return -ENOMEM;
+       tve->dev = dev;
+       spin_lock_init(&tve->lock);
+       ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
+       if (ddc_node) {
+               tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
+               of_node_put(ddc_node);
+       }
+       tve->mode = of_get_tve_mode(np);
+       if (tve->mode != TVE_MODE_VGA) {
+               dev_err(dev, "only VGA mode supported, currently\n");
+               return -EINVAL;
+       }
+       if (tve->mode == TVE_MODE_VGA) {
+               ret = of_property_read_u32(np, "fsl,hsync-pin",
+                                          &tve->hsync_pin);
+               if (ret < 0) {
+                       dev_err(dev, "failed to get vsync pin\n");
+                       return ret;
+               }
+               ret |= of_property_read_u32(np, "fsl,vsync-pin",
+                                           &tve->vsync_pin);
+               if (ret < 0) {
+                       dev_err(dev, "failed to get vsync pin\n");
+                       return ret;
+               }
+       }
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       base = devm_ioremap_resource(dev, res);
+       if (IS_ERR(base))
+               return PTR_ERR(base);
+       tve_regmap_config.lock_arg = tve;
+       tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
+                                               &tve_regmap_config);
+       if (IS_ERR(tve->regmap)) {
+               dev_err(dev, "failed to init regmap: %ld\n",
+                       PTR_ERR(tve->regmap));
+               return PTR_ERR(tve->regmap);
+       }
+       irq = platform_get_irq(pdev, 0);
+       if (irq < 0) {
+               dev_err(dev, "failed to get irq\n");
+               return irq;
+       }
+       ret = devm_request_threaded_irq(dev, irq, NULL,
+                                       imx_tve_irq_handler, IRQF_ONESHOT,
+                                       "imx-tve", tve);
+       if (ret < 0) {
+               dev_err(dev, "failed to request irq: %d\n", ret);
+               return ret;
+       }
+       tve->dac_reg = devm_regulator_get(dev, "dac");
+       if (!IS_ERR(tve->dac_reg)) {
+               regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
+               ret = regulator_enable(tve->dac_reg);
+               if (ret)
+                       return ret;
+       }
+       tve->clk = devm_clk_get(dev, "tve");
+       if (IS_ERR(tve->clk)) {
+               dev_err(dev, "failed to get high speed tve clock: %ld\n",
+                       PTR_ERR(tve->clk));
+               return PTR_ERR(tve->clk);
+       }
+       /* this is the IPU DI clock input selector, can be parented to tve_di */
+       tve->di_sel_clk = devm_clk_get(dev, "di_sel");
+       if (IS_ERR(tve->di_sel_clk)) {
+               dev_err(dev, "failed to get ipu di mux clock: %ld\n",
+                       PTR_ERR(tve->di_sel_clk));
+               return PTR_ERR(tve->di_sel_clk);
+       }
+       ret = tve_clk_init(tve, base);
+       if (ret < 0)
+               return ret;
+       ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
+       if (ret < 0) {
+               dev_err(dev, "failed to read configuration register: %d\n", ret);
+               return ret;
+       }
+       if (val != 0x00100000) {
+               dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
+               return -ENODEV;
+       }
+       /* disable cable detection for VGA mode */
+       ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
+       ret = imx_tve_register(drm, tve);
+       if (ret)
+               return ret;
+       dev_set_drvdata(dev, tve);
+       return 0;
+ }
+ static void imx_tve_unbind(struct device *dev, struct device *master,
+       void *data)
+ {
+       struct imx_tve *tve = dev_get_drvdata(dev);
+       tve->connector.funcs->destroy(&tve->connector);
+       tve->encoder.funcs->destroy(&tve->encoder);
+       if (!IS_ERR(tve->dac_reg))
+               regulator_disable(tve->dac_reg);
+ }
+ static const struct component_ops imx_tve_ops = {
+       .bind   = imx_tve_bind,
+       .unbind = imx_tve_unbind,
+ };
+ static int imx_tve_probe(struct platform_device *pdev)
+ {
+       return component_add(&pdev->dev, &imx_tve_ops);
+ }
+ static int imx_tve_remove(struct platform_device *pdev)
+ {
+       component_del(&pdev->dev, &imx_tve_ops);
+       return 0;
+ }
+ static const struct of_device_id imx_tve_dt_ids[] = {
+       { .compatible = "fsl,imx53-tve", },
+       { /* sentinel */ }
+ };
+ static struct platform_driver imx_tve_driver = {
+       .probe          = imx_tve_probe,
+       .remove         = imx_tve_remove,
+       .driver         = {
+               .of_match_table = imx_tve_dt_ids,
+               .name   = "imx-tve",
+       },
+ };
+ module_platform_driver(imx_tve_driver);
+ MODULE_DESCRIPTION("i.MX Television Encoder driver");
+ MODULE_AUTHOR("Philipp Zabel, Pengutronix");
+ MODULE_LICENSE("GPL");
+ MODULE_ALIAS("platform:imx-tve");
index 0000000000000000000000000000000000000000,015a454b87e16ac1475b56d0d477069bd4b4bdc0..8a76a5c1c34bcb190b579ca351cdd79b03347926
mode 000000,100644..100644
--- /dev/null
@@@ -1,0 -1,296 +1,295 @@@
 -              .owner  = THIS_MODULE,
+ /*
+  * i.MX drm driver - parallel display implementation
+  *
+  * Copyright (C) 2012 Sascha Hauer, Pengutronix
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License
+  * as published by the Free Software Foundation; either version 2
+  * of the License, or (at your option) any later version.
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+  * MA 02110-1301, USA.
+  */
+ #include <linux/component.h>
+ #include <linux/module.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <drm/drm_panel.h>
+ #include <linux/videodev2.h>
+ #include <video/of_display_timing.h>
+ #include "imx-drm.h"
+ #define con_to_imxpd(x) container_of(x, struct imx_parallel_display, connector)
+ #define enc_to_imxpd(x) container_of(x, struct imx_parallel_display, encoder)
+ struct imx_parallel_display {
+       struct drm_connector connector;
+       struct drm_encoder encoder;
+       struct device *dev;
+       void *edid;
+       int edid_len;
+       u32 interface_pix_fmt;
+       int mode_valid;
+       struct drm_display_mode mode;
+       struct drm_panel *panel;
+ };
+ static enum drm_connector_status imx_pd_connector_detect(
+               struct drm_connector *connector, bool force)
+ {
+       return connector_status_connected;
+ }
+ static int imx_pd_connector_get_modes(struct drm_connector *connector)
+ {
+       struct imx_parallel_display *imxpd = con_to_imxpd(connector);
+       struct device_node *np = imxpd->dev->of_node;
+       int num_modes = 0;
+       if (imxpd->panel && imxpd->panel->funcs &&
+           imxpd->panel->funcs->get_modes) {
+               num_modes = imxpd->panel->funcs->get_modes(imxpd->panel);
+               if (num_modes > 0)
+                       return num_modes;
+       }
+       if (imxpd->edid) {
+               drm_mode_connector_update_edid_property(connector, imxpd->edid);
+               num_modes = drm_add_edid_modes(connector, imxpd->edid);
+       }
+       if (imxpd->mode_valid) {
+               struct drm_display_mode *mode = drm_mode_create(connector->dev);
+               if (!mode)
+                       return -EINVAL;
+               drm_mode_copy(mode, &imxpd->mode);
+               mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+               drm_mode_probed_add(connector, mode);
+               num_modes++;
+       }
+       if (np) {
+               struct drm_display_mode *mode = drm_mode_create(connector->dev);
+               if (!mode)
+                       return -EINVAL;
+               of_get_drm_display_mode(np, &imxpd->mode, OF_USE_NATIVE_MODE);
+               drm_mode_copy(mode, &imxpd->mode);
+               mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+               drm_mode_probed_add(connector, mode);
+               num_modes++;
+       }
+       return num_modes;
+ }
+ static struct drm_encoder *imx_pd_connector_best_encoder(
+               struct drm_connector *connector)
+ {
+       struct imx_parallel_display *imxpd = con_to_imxpd(connector);
+       return &imxpd->encoder;
+ }
+ static void imx_pd_encoder_dpms(struct drm_encoder *encoder, int mode)
+ {
+       struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
+       if (mode != DRM_MODE_DPMS_ON)
+               drm_panel_disable(imxpd->panel);
+       else
+               drm_panel_enable(imxpd->panel);
+ }
+ static bool imx_pd_encoder_mode_fixup(struct drm_encoder *encoder,
+                          const struct drm_display_mode *mode,
+                          struct drm_display_mode *adjusted_mode)
+ {
+       return true;
+ }
+ static void imx_pd_encoder_prepare(struct drm_encoder *encoder)
+ {
+       struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
+       imx_drm_panel_format(encoder, imxpd->interface_pix_fmt);
+ }
+ static void imx_pd_encoder_commit(struct drm_encoder *encoder)
+ {
+ }
+ static void imx_pd_encoder_mode_set(struct drm_encoder *encoder,
+                        struct drm_display_mode *mode,
+                        struct drm_display_mode *adjusted_mode)
+ {
+ }
+ static void imx_pd_encoder_disable(struct drm_encoder *encoder)
+ {
+ }
+ static struct drm_connector_funcs imx_pd_connector_funcs = {
+       .dpms = drm_helper_connector_dpms,
+       .fill_modes = drm_helper_probe_single_connector_modes,
+       .detect = imx_pd_connector_detect,
+       .destroy = imx_drm_connector_destroy,
+ };
+ static struct drm_connector_helper_funcs imx_pd_connector_helper_funcs = {
+       .get_modes = imx_pd_connector_get_modes,
+       .best_encoder = imx_pd_connector_best_encoder,
+ };
+ static struct drm_encoder_funcs imx_pd_encoder_funcs = {
+       .destroy = imx_drm_encoder_destroy,
+ };
+ static struct drm_encoder_helper_funcs imx_pd_encoder_helper_funcs = {
+       .dpms = imx_pd_encoder_dpms,
+       .mode_fixup = imx_pd_encoder_mode_fixup,
+       .prepare = imx_pd_encoder_prepare,
+       .commit = imx_pd_encoder_commit,
+       .mode_set = imx_pd_encoder_mode_set,
+       .disable = imx_pd_encoder_disable,
+ };
+ static int imx_pd_register(struct drm_device *drm,
+       struct imx_parallel_display *imxpd)
+ {
+       int ret;
+       ret = imx_drm_encoder_parse_of(drm, &imxpd->encoder,
+                                      imxpd->dev->of_node);
+       if (ret)
+               return ret;
+       /* set the connector's dpms to OFF so that
+        * drm_helper_connector_dpms() won't return
+        * immediately since the current state is ON
+        * at this point.
+        */
+       imxpd->connector.dpms = DRM_MODE_DPMS_OFF;
+       drm_encoder_helper_add(&imxpd->encoder, &imx_pd_encoder_helper_funcs);
+       drm_encoder_init(drm, &imxpd->encoder, &imx_pd_encoder_funcs,
+                        DRM_MODE_ENCODER_NONE);
+       drm_connector_helper_add(&imxpd->connector,
+                       &imx_pd_connector_helper_funcs);
+       drm_connector_init(drm, &imxpd->connector, &imx_pd_connector_funcs,
+                          DRM_MODE_CONNECTOR_VGA);
+       if (imxpd->panel)
+               drm_panel_attach(imxpd->panel, &imxpd->connector);
+       drm_mode_connector_attach_encoder(&imxpd->connector, &imxpd->encoder);
+       imxpd->connector.encoder = &imxpd->encoder;
+       return 0;
+ }
+ static int imx_pd_bind(struct device *dev, struct device *master, void *data)
+ {
+       struct drm_device *drm = data;
+       struct device_node *np = dev->of_node;
+       struct device_node *panel_node;
+       const u8 *edidp;
+       struct imx_parallel_display *imxpd;
+       int ret;
+       const char *fmt;
+       imxpd = devm_kzalloc(dev, sizeof(*imxpd), GFP_KERNEL);
+       if (!imxpd)
+               return -ENOMEM;
+       edidp = of_get_property(np, "edid", &imxpd->edid_len);
+       if (edidp)
+               imxpd->edid = kmemdup(edidp, imxpd->edid_len, GFP_KERNEL);
+       ret = of_property_read_string(np, "interface-pix-fmt", &fmt);
+       if (!ret) {
+               if (!strcmp(fmt, "rgb24"))
+                       imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB24;
+               else if (!strcmp(fmt, "rgb565"))
+                       imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB565;
+               else if (!strcmp(fmt, "bgr666"))
+                       imxpd->interface_pix_fmt = V4L2_PIX_FMT_BGR666;
+               else if (!strcmp(fmt, "lvds666"))
+                       imxpd->interface_pix_fmt =
+                                       v4l2_fourcc('L', 'V', 'D', '6');
+       }
+       panel_node = of_parse_phandle(np, "fsl,panel", 0);
+       if (panel_node)
+               imxpd->panel = of_drm_find_panel(panel_node);
+       imxpd->dev = dev;
+       ret = imx_pd_register(drm, imxpd);
+       if (ret)
+               return ret;
+       dev_set_drvdata(dev, imxpd);
+       return 0;
+ }
+ static void imx_pd_unbind(struct device *dev, struct device *master,
+       void *data)
+ {
+       struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
+       imxpd->encoder.funcs->destroy(&imxpd->encoder);
+       imxpd->connector.funcs->destroy(&imxpd->connector);
+ }
+ static const struct component_ops imx_pd_ops = {
+       .bind   = imx_pd_bind,
+       .unbind = imx_pd_unbind,
+ };
+ static int imx_pd_probe(struct platform_device *pdev)
+ {
+       return component_add(&pdev->dev, &imx_pd_ops);
+ }
+ static int imx_pd_remove(struct platform_device *pdev)
+ {
+       component_del(&pdev->dev, &imx_pd_ops);
+       return 0;
+ }
+ static const struct of_device_id imx_pd_dt_ids[] = {
+       { .compatible = "fsl,imx-parallel-display", },
+       { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, imx_pd_dt_ids);
+ static struct platform_driver imx_pd_driver = {
+       .probe          = imx_pd_probe,
+       .remove         = imx_pd_remove,
+       .driver         = {
+               .of_match_table = imx_pd_dt_ids,
+               .name   = "imx-parallel-display",
+       },
+ };
+ module_platform_driver(imx_pd_driver);
+ MODULE_DESCRIPTION("i.MX parallel display driver");
+ MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+ MODULE_LICENSE("GPL");
+ MODULE_ALIAS("platform:imx-parallel-display");
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
diff --cc mm/fremap.c
Simple merge
Simple merge
diff --cc mm/hugetlb.c
index 47f6070d7c46fa5d631c5ceeb64b9a31ab2553cf,2e6add04fa1b37bd451f8bbd89e6cec6ab26f614..85032de5e20f88bdef36f8fa54b71ae826f53f13
@@@ -3376,7 -3378,8 +3380,8 @@@ unsigned long hugetlb_change_protection
         * and that page table be reused and filled with junk.
         */
        flush_tlb_range(vma, start, end);
 -      mutex_unlock(&vma->vm_file->f_mapping->i_mmap_mutex);
+       mmu_notifier_invalidate_range(mm, start, end);
 +      i_mmap_unlock_write(vma->vm_file->f_mapping);
        mmu_notifier_invalidate_range_end(mm, start, end);
  
        return pages << h->order;
diff --cc mm/memory.c
index fbf74112de5bfa39496ae491bd39ea9ef38ae00d,d3cb2ef66ee21325e8d4230efe18d2f2fbef1314..c3b9097251c5769959b044e74ed1da6de35392e6
@@@ -235,10 -236,9 +235,11 @@@ void tlb_gather_mmu(struct mmu_gather *
  
  static void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb)
  {
 -      tlb->need_flush = 0;
 +      if (!tlb->end)
 +              return;
 +
        tlb_flush(tlb);
+       mmu_notifier_invalidate_range(tlb->mm, tlb->start, tlb->end);
  #ifdef CONFIG_HAVE_RCU_TABLE_FREE
        tlb_table_flush(tlb);
  #endif
diff --cc mm/migrate.c
Simple merge
diff --cc mm/rmap.c
Simple merge