bnx2x,cnic: use FW 7.8.2
authorYuval Mintz <yuvalmin@broadcom.com>
Mon, 1 Oct 2012 03:46:19 +0000 (03:46 +0000)
committerDavid S. Miller <davem@davemloft.net>
Mon, 1 Oct 2012 20:43:17 +0000 (16:43 -0400)
This patch moves the bnx2x and cnic drivers into using FW 7.8.2
which was recently submitted into the linux-firmware tree.

A short summary of minor bugs fixed by this FW:
 1. In switch dependent mode, fix several issues regarding inner vlan
    vs. DCB priorities.
 2. iSCSI - not all packets were completed on a forward channel.
 3. DCB - fixed for 4-port devices.
 4. Fixed false parity reported in CAM memories when operating near -5%
    on the 1.0V core supply.
 5. ETS default settings are set to fairness between traffic classes
    (rather than strict priority), and uses the same chip receive buffer
    configuration for both PFC and pause.

For a complete list of fixes made by this FW, see commit 236367db
in the linux-firmware git repository.

Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Ariel Elior <ariele@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
drivers/net/ethernet/broadcom/cnic.c
drivers/net/ethernet/broadcom/cnic_defs.h
drivers/net/ethernet/broadcom/cnic_if.h

index f67e700fe59d0244b1cd1b76bc544a6e432d530f..30f04a389227bbfcb9cdaf29b563c005afbfa26a 100644 (file)
@@ -3026,8 +3026,9 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
        first_bd = tx_start_bd;
 
        tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
-       SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_ETH_ADDR_TYPE,
-                mac_type);
+       SET_FLAG(tx_start_bd->general_data,
+                ETH_TX_START_BD_PARSE_NBDS,
+                0);
 
        /* header nbd */
        SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1);
@@ -3077,13 +3078,20 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                                              &pbd_e2->dst_mac_addr_lo,
                                              eth->h_dest);
                }
+
+               SET_FLAG(pbd_e2_parsing_data,
+                        ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
        } else {
+               u16 global_data = 0;
                pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
                memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
                /* Set PBD in checksum offload case */
                if (xmit_type & XMIT_CSUM)
                        hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
 
+               SET_FLAG(global_data,
+                        ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
+               pbd_e1x->global_data |= cpu_to_le16(global_data);
        }
 
        /* Setup the data pointer of the first BD of the packet */
index 8a73374e52a763ba16d8526a2d3f1aa8b80fb11e..2245c3895409d149c402fa70bdff529790046e28 100644 (file)
@@ -91,25 +91,21 @@ static void bnx2x_pfc_set(struct bnx2x *bp)
        /*
         * Rx COS configuration
         * Changing PFC RX configuration .
-        * In RX COS0 will always be configured to lossy and COS1 to lossless
+        * In RX COS0 will always be configured to lossless and COS1 to lossy
         */
        for (i = 0 ; i < MAX_PFC_PRIORITIES ; i++) {
                pri_bit = 1 << i;
 
-               if (pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp))
+               if (!(pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp)))
                        val |= 1 << (i * 4);
        }
 
        pfc_params.pkt_priority_to_cos = val;
 
        /* RX COS0 */
-       pfc_params.llfc_low_priority_classes = 0;
+       pfc_params.llfc_low_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp);
        /* RX COS1 */
-       pfc_params.llfc_high_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp);
-
-       /* BRB configuration */
-       pfc_params.cos0_pauseable = false;
-       pfc_params.cos1_pauseable = true;
+       pfc_params.llfc_high_priority_classes = 0;
 
        bnx2x_acquire_phy_lock(bp);
        bp->link_params.feature_config_flags |= FEATURE_CONFIG_PFC_ENABLED;
index a19c9e08827858a4ed64eee99a8b7fdbcee63409..c65295dded39aa5b1965a9dd07e00974863ca297 100644 (file)
@@ -2040,8 +2040,6 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
        u16 pkt_prod, bd_prod;
        struct sw_tx_bd *tx_buf;
        struct eth_tx_start_bd *tx_start_bd;
-       struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
-       struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
        dma_addr_t mapping;
        union eth_rx_cqe *cqe;
        u8 cqe_fp_flags, cqe_fp_type;
@@ -2132,22 +2130,33 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
        tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
        tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
        tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
-       SET_FLAG(tx_start_bd->general_data,
-                ETH_TX_START_BD_ETH_ADDR_TYPE,
-                UNICAST_ADDRESS);
        SET_FLAG(tx_start_bd->general_data,
                 ETH_TX_START_BD_HDR_NBDS,
                 1);
+       SET_FLAG(tx_start_bd->general_data,
+                ETH_TX_START_BD_PARSE_NBDS,
+                0);
 
        /* turn on parsing and get a BD */
        bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
 
-       pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
-       pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
-
-       memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
-       memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
-
+       if (CHIP_IS_E1x(bp)) {
+               u16 global_data = 0;
+               struct eth_tx_parse_bd_e1x  *pbd_e1x =
+                       &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
+               memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
+               SET_FLAG(global_data,
+                        ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
+               pbd_e1x->global_data = cpu_to_le16(global_data);
+       } else {
+               u32 parsing_data = 0;
+               struct eth_tx_parse_bd_e2  *pbd_e2 =
+                       &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
+               memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
+               SET_FLAG(parsing_data,
+                        ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
+               pbd_e2->parsing_data = cpu_to_le32(parsing_data);
+       }
        wmb();
 
        txdata->tx_db.data.prod += 2;
index bbc66ced9c25af262f4884de5549c20659f9bc6e..620fe939ecfd357ed1e852bd0350c3687886a8b5 100644 (file)
@@ -88,9 +88,6 @@
 #define TSTORM_ASSERT_LIST_INDEX_OFFSET        (IRO[102].base)
 #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
        (IRO[101].base + ((assertListEntry) * IRO[101].m1))
-#define TSTORM_COMMON_SAFC_WORKAROUND_ENABLE_OFFSET (IRO[107].base)
-#define TSTORM_COMMON_SAFC_WORKAROUND_TIMEOUT_10USEC_OFFSET \
-       (IRO[108].base)
 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
        (IRO[201].base + ((pfId) * IRO[201].m1))
 #define TSTORM_FUNC_EN_OFFSET(funcId) \
index c795cfc5a545ee43841466c7ef90270166e3961f..18704929e6422ec15f0c59ec8c4abcee8802e532 100644 (file)
@@ -2789,8 +2789,8 @@ struct afex_stats {
 };
 
 #define BCM_5710_FW_MAJOR_VERSION                      7
-#define BCM_5710_FW_MINOR_VERSION                      2
-#define BCM_5710_FW_REVISION_VERSION                   51
+#define BCM_5710_FW_MINOR_VERSION                      8
+#define BCM_5710_FW_REVISION_VERSION           2
 #define BCM_5710_FW_ENGINEERING_VERSION                        0
 #define BCM_5710_FW_COMPILE_FLAGS                      1
 
@@ -3912,10 +3912,8 @@ struct eth_rss_update_ramrod_data {
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
-#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
-#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
        u8 rss_result_mask;
        u8 rss_mode;
        __le32 __reserved2;
@@ -4131,27 +4129,29 @@ struct eth_tx_start_bd {
 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
-#define ETH_TX_START_BD_RESREVED (0x1<<5)
-#define ETH_TX_START_BD_RESREVED_SHIFT 5
-#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
-#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
+#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
+#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
+#define ETH_TX_START_BD_RESREVED (0x1<<7)
+#define ETH_TX_START_BD_RESREVED_SHIFT 7
 };
 
 /*
  * Tx parsing BD structure for ETH E1/E1h
  */
 struct eth_tx_parse_bd_e1x {
-       u8 global_data;
+       __le16 global_data;
 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
-#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
-#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
-#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
-#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
-#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
-#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
-#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
+#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
+#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
+#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
+#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
+#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
+#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
+#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
        u8 tcp_flags;
 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
@@ -4170,7 +4170,6 @@ struct eth_tx_parse_bd_e1x {
 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
        u8 ip_hlen_w;
-       s8 reserved;
        __le16 total_hlen_w;
        __le16 tcp_pseudo_csum;
        __le16 lso_mss;
@@ -4189,14 +4188,16 @@ struct eth_tx_parse_bd_e2 {
        __le16 src_mac_addr_mid;
        __le16 src_mac_addr_hi;
        __le32 parsing_data;
-#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x7FF<<0)
 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
-#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
-#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
-#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
-#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
-#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
+#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
+#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
+#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
+#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
+#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
 };
 
 /*
@@ -4964,7 +4965,8 @@ struct flow_control_configuration {
  *
  */
 struct function_start_data {
-       __le16 function_mode;
+       u8 function_mode;
+       u8 reserved;
        __le16 sd_vlan_tag;
        __le16 vif_id;
        u8 path_id;
index 559c396d45cce465ae77999fa0d22508b6d60624..c8f10f0e8a0dea6db58e412989f2d35eddc6528d 100644 (file)
@@ -566,7 +566,7 @@ static const struct {
                u32 e2;         /* 57712 */
                u32 e3;         /* 578xx */
        } reg_mask;             /* Register mask (all valid bits) */
-       char name[7];           /* Block's longest name is 6 characters long
+       char name[8];           /* Block's longest name is 7 characters long
                                 * (name + suffix)
                                 */
 } bnx2x_blocks_parity_data[] = {
index bcc112b82831253a5d85af99a60a18df688c6402..e2e45ee5df33fcc75c491c78643dfe406297aabb 100644 (file)
 #define EDC_MODE_LIMITING                              0x0044
 #define EDC_MODE_PASSIVE_DAC                   0x0055
 
-/* BRB default for class 0 E2 */
-#define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR     170
-#define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR              250
-#define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR              10
-#define DEFAULT0_E2_BRB_MAC_FULL_XON_THR               50
-
-/* BRB thresholds for E2*/
-#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE            170
-#define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE                0
-
-#define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE             250
-#define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE         0
-
-#define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE             10
-#define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE         90
-
-#define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                      50
-#define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE          250
-
-/* BRB default for class 0 E3A0 */
-#define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR   290
-#define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR    410
-#define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR    10
-#define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR     50
-
-/* BRB thresholds for E3A0 */
-#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE          290
-#define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE              0
-
-#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE           410
-#define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE               0
-
-#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE           10
-#define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE               170
-
-#define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE            50
-#define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE                410
-
-/* BRB default for E3B0 */
-#define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR   330
-#define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR    490
-#define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR    15
-#define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR     55
-
-/* BRB thresholds for E3B0 2 port mode*/
-#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE               1025
-#define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE   0
-
-#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE                1025
-#define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE    0
-
-#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE                10
-#define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE    1025
-
-#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE         50
-#define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE     1025
-
-/* only for E3B0*/
-#define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                       1025
-#define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                        1025
-
-/* Lossy +Lossless GUARANTIED == GUART */
-#define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                 284
-/* Lossless +Lossless*/
-#define PFC_E3B0_2P_PAUSE_LB_GUART                     236
-/* Lossy +Lossy*/
-#define PFC_E3B0_2P_NON_PAUSE_LB_GUART                 342
-
-/* Lossy +Lossless*/
-#define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART              284
-/* Lossless +Lossless*/
-#define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART          236
-/* Lossy +Lossy*/
-#define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART              336
-#define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST               80
-
-#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART            0
-#define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST               0
-
-/* BRB thresholds for E3B0 4 port mode */
-#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE               304
-#define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE   0
-
-#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE                384
-#define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE    0
-
-#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE                10
-#define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE    304
-
-#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE         50
-#define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE     384
-
-/* only for E3B0*/
-#define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                       304
-#define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                        384
-#define PFC_E3B0_4P_LB_GUART           120
-
-#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART            120
-#define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST       80
-
-#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART            80
-#define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST       120
-
-/* Pause defines*/
-#define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR                      330
-#define DEFAULT_E3B0_BRB_FULL_LB_XON_THR                       490
-#define DEFAULT_E3B0_LB_GUART          40
-
-#define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART           40
-#define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST      0
-
-#define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART           40
-#define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST      0
-
 /* ETS defines*/
 #define DCBX_INVALID_COS                                       (0xFF)
 
@@ -2144,391 +2030,6 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
        REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
 }
 
-/* PFC BRB internal port configuration params */
-struct bnx2x_pfc_brb_threshold_val {
-       u32 pause_xoff;
-       u32 pause_xon;
-       u32 full_xoff;
-       u32 full_xon;
-};
-
-struct bnx2x_pfc_brb_e3b0_val {
-       u32 per_class_guaranty_mode;
-       u32 lb_guarantied_hyst;
-       u32 full_lb_xoff_th;
-       u32 full_lb_xon_threshold;
-       u32 lb_guarantied;
-       u32 mac_0_class_t_guarantied;
-       u32 mac_0_class_t_guarantied_hyst;
-       u32 mac_1_class_t_guarantied;
-       u32 mac_1_class_t_guarantied_hyst;
-};
-
-struct bnx2x_pfc_brb_th_val {
-       struct bnx2x_pfc_brb_threshold_val pauseable_th;
-       struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
-       struct bnx2x_pfc_brb_threshold_val default_class0;
-       struct bnx2x_pfc_brb_threshold_val default_class1;
-
-};
-static int bnx2x_pfc_brb_get_config_params(
-                               struct link_params *params,
-                               struct bnx2x_pfc_brb_th_val *config_val)
-{
-       struct bnx2x *bp = params->bp;
-       DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
-
-       config_val->default_class1.pause_xoff = 0;
-       config_val->default_class1.pause_xon = 0;
-       config_val->default_class1.full_xoff = 0;
-       config_val->default_class1.full_xon = 0;
-
-       if (CHIP_IS_E2(bp)) {
-               /* Class0 defaults */
-               config_val->default_class0.pause_xoff =
-                       DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
-               config_val->default_class0.pause_xon =
-                       DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR;
-               config_val->default_class0.full_xoff =
-                       DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
-               config_val->default_class0.full_xon =
-                       DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
-               /* Pause able*/
-               config_val->pauseable_th.pause_xoff =
-                       PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
-               config_val->pauseable_th.pause_xon =
-                       PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
-               config_val->pauseable_th.full_xoff =
-                       PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
-               config_val->pauseable_th.full_xon =
-                       PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
-               /* Non pause able*/
-               config_val->non_pauseable_th.pause_xoff =
-                       PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
-               config_val->non_pauseable_th.pause_xon =
-                       PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
-               config_val->non_pauseable_th.full_xoff =
-                       PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
-               config_val->non_pauseable_th.full_xon =
-                       PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
-       } else if (CHIP_IS_E3A0(bp)) {
-               /* Class0 defaults */
-               config_val->default_class0.pause_xoff =
-                       DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
-               config_val->default_class0.pause_xon =
-                       DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR;
-               config_val->default_class0.full_xoff =
-                       DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
-               config_val->default_class0.full_xon =
-                       DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
-               /* Pause able */
-               config_val->pauseable_th.pause_xoff =
-                       PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
-               config_val->pauseable_th.pause_xon =
-                       PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
-               config_val->pauseable_th.full_xoff =
-                       PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
-               config_val->pauseable_th.full_xon =
-                       PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
-               /* Non pause able*/
-               config_val->non_pauseable_th.pause_xoff =
-                       PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
-               config_val->non_pauseable_th.pause_xon =
-                       PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
-               config_val->non_pauseable_th.full_xoff =
-                       PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
-               config_val->non_pauseable_th.full_xon =
-                       PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
-       } else if (CHIP_IS_E3B0(bp)) {
-               /* Class0 defaults */
-               config_val->default_class0.pause_xoff =
-                       DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
-               config_val->default_class0.pause_xon =
-                   DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR;
-               config_val->default_class0.full_xoff =
-                   DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR;
-               config_val->default_class0.full_xon =
-                   DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR;
-
-               if (params->phy[INT_PHY].flags &
-                   FLAGS_4_PORT_MODE) {
-                       config_val->pauseable_th.pause_xoff =
-                               PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
-                       config_val->pauseable_th.pause_xon =
-                               PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
-                       config_val->pauseable_th.full_xoff =
-                               PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
-                       config_val->pauseable_th.full_xon =
-                               PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
-                       /* Non pause able*/
-                       config_val->non_pauseable_th.pause_xoff =
-                       PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
-                       config_val->non_pauseable_th.pause_xon =
-                       PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
-                       config_val->non_pauseable_th.full_xoff =
-                       PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
-                       config_val->non_pauseable_th.full_xon =
-                       PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
-               } else {
-                       config_val->pauseable_th.pause_xoff =
-                               PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
-                       config_val->pauseable_th.pause_xon =
-                               PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
-                       config_val->pauseable_th.full_xoff =
-                               PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
-                       config_val->pauseable_th.full_xon =
-                               PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
-                       /* Non pause able*/
-                       config_val->non_pauseable_th.pause_xoff =
-                               PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
-                       config_val->non_pauseable_th.pause_xon =
-                               PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
-                       config_val->non_pauseable_th.full_xoff =
-                               PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
-                       config_val->non_pauseable_th.full_xon =
-                               PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
-               }
-       } else
-           return -EINVAL;
-
-       return 0;
-}
-
-static void bnx2x_pfc_brb_get_e3b0_config_params(
-               struct link_params *params,
-               struct bnx2x_pfc_brb_e3b0_val
-               *e3b0_val,
-               struct bnx2x_nig_brb_pfc_port_params *pfc_params,
-               const u8 pfc_enabled)
-{
-       if (pfc_enabled && pfc_params) {
-               e3b0_val->per_class_guaranty_mode = 1;
-               e3b0_val->lb_guarantied_hyst = 80;
-
-               if (params->phy[INT_PHY].flags &
-                   FLAGS_4_PORT_MODE) {
-                       e3b0_val->full_lb_xoff_th =
-                               PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
-                       e3b0_val->full_lb_xon_threshold =
-                               PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
-                       e3b0_val->lb_guarantied =
-                               PFC_E3B0_4P_LB_GUART;
-                       e3b0_val->mac_0_class_t_guarantied =
-                               PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
-                       e3b0_val->mac_0_class_t_guarantied_hyst =
-                               PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
-                       e3b0_val->mac_1_class_t_guarantied =
-                               PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
-                       e3b0_val->mac_1_class_t_guarantied_hyst =
-                               PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
-               } else {
-                       e3b0_val->full_lb_xoff_th =
-                               PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
-                       e3b0_val->full_lb_xon_threshold =
-                               PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
-                       e3b0_val->mac_0_class_t_guarantied_hyst =
-                               PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
-                       e3b0_val->mac_1_class_t_guarantied =
-                               PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
-                       e3b0_val->mac_1_class_t_guarantied_hyst =
-                               PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
-
-                       if (pfc_params->cos0_pauseable !=
-                               pfc_params->cos1_pauseable) {
-                               /* Nonpauseable= Lossy + pauseable = Lossless*/
-                               e3b0_val->lb_guarantied =
-                                       PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
-                               e3b0_val->mac_0_class_t_guarantied =
-                              PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
-                       } else if (pfc_params->cos0_pauseable) {
-                               /* Lossless +Lossless*/
-                               e3b0_val->lb_guarantied =
-                                       PFC_E3B0_2P_PAUSE_LB_GUART;
-                               e3b0_val->mac_0_class_t_guarantied =
-                                  PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
-                       } else {
-                               /* Lossy +Lossy*/
-                               e3b0_val->lb_guarantied =
-                                       PFC_E3B0_2P_NON_PAUSE_LB_GUART;
-                               e3b0_val->mac_0_class_t_guarantied =
-                              PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
-                       }
-               }
-       } else {
-               e3b0_val->per_class_guaranty_mode = 0;
-               e3b0_val->lb_guarantied_hyst = 0;
-               e3b0_val->full_lb_xoff_th =
-                       DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR;
-               e3b0_val->full_lb_xon_threshold =
-                       DEFAULT_E3B0_BRB_FULL_LB_XON_THR;
-               e3b0_val->lb_guarantied =
-                       DEFAULT_E3B0_LB_GUART;
-               e3b0_val->mac_0_class_t_guarantied =
-                       DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART;
-               e3b0_val->mac_0_class_t_guarantied_hyst =
-                       DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST;
-               e3b0_val->mac_1_class_t_guarantied =
-                       DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART;
-               e3b0_val->mac_1_class_t_guarantied_hyst =
-                       DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST;
-       }
-}
-static int bnx2x_update_pfc_brb(struct link_params *params,
-                               struct link_vars *vars,
-                               struct bnx2x_nig_brb_pfc_port_params
-                               *pfc_params)
-{
-       struct bnx2x *bp = params->bp;
-       struct bnx2x_pfc_brb_th_val config_val = { {0} };
-       struct bnx2x_pfc_brb_threshold_val *reg_th_config =
-               &config_val.pauseable_th;
-       struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
-       const int set_pfc = params->feature_config_flags &
-               FEATURE_CONFIG_PFC_ENABLED;
-       const u8 pfc_enabled = (set_pfc && pfc_params);
-       int bnx2x_status = 0;
-       u8 port = params->port;
-
-       /* default - pause configuration */
-       reg_th_config = &config_val.pauseable_th;
-       bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
-       if (bnx2x_status)
-               return bnx2x_status;
-
-       if (pfc_enabled) {
-               /* First COS */
-               if (pfc_params->cos0_pauseable)
-                       reg_th_config = &config_val.pauseable_th;
-               else
-                       reg_th_config = &config_val.non_pauseable_th;
-       } else
-               reg_th_config = &config_val.default_class0;
-       /* The number of free blocks below which the pause signal to class 0
-        * of MAC #n is asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
-              BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
-              reg_th_config->pause_xoff);
-       /* The number of free blocks above which the pause signal to class 0
-        * of MAC #n is de-asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
-              BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
-       /* The number of free blocks below which the full signal to class 0
-        * of MAC #n is asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
-              BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
-       /* The number of free blocks above which the full signal to class 0
-        * of MAC #n is de-asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
-              BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
-
-       if (pfc_enabled) {
-               /* Second COS */
-               if (pfc_params->cos1_pauseable)
-                       reg_th_config = &config_val.pauseable_th;
-               else
-                       reg_th_config = &config_val.non_pauseable_th;
-       } else
-               reg_th_config = &config_val.default_class1;
-       /* The number of free blocks below which the pause signal to
-        * class 1 of MAC #n is asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
-              BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
-              reg_th_config->pause_xoff);
-
-       /* The number of free blocks above which the pause signal to
-        * class 1 of MAC #n is de-asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
-              BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
-              reg_th_config->pause_xon);
-       /* The number of free blocks below which the full signal to
-        * class 1 of MAC #n is asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
-              BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
-              reg_th_config->full_xoff);
-       /* The number of free blocks above which the full signal to
-        * class 1 of MAC #n is de-asserted. n=0,1
-        */
-       REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
-              BRB1_REG_FULL_1_XON_THRESHOLD_0,
-              reg_th_config->full_xon);
-
-       if (CHIP_IS_E3B0(bp)) {
-               bnx2x_pfc_brb_get_e3b0_config_params(
-                       params,
-                       &e3b0_val,
-                       pfc_params,
-                       pfc_enabled);
-
-               REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
-                          e3b0_val.per_class_guaranty_mode);
-
-               /* The hysteresis on the guarantied buffer space for the Lb
-                * port before signaling XON.
-                */
-               REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
-                          e3b0_val.lb_guarantied_hyst);
-
-               /* The number of free blocks below which the full signal to the
-                * LB port is asserted.
-                */
-               REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
-                      e3b0_val.full_lb_xoff_th);
-               /* The number of free blocks above which the full signal to the
-                * LB port is de-asserted.
-                */
-               REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
-                      e3b0_val.full_lb_xon_threshold);
-               /* The number of blocks guarantied for the MAC #n port. n=0,1
-                */
-
-               /* The number of blocks guarantied for the LB port. */
-               REG_WR(bp, BRB1_REG_LB_GUARANTIED,
-                      e3b0_val.lb_guarantied);
-
-               /* The number of blocks guarantied for the MAC #n port. */
-               REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
-                      2 * e3b0_val.mac_0_class_t_guarantied);
-               REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
-                      2 * e3b0_val.mac_1_class_t_guarantied);
-               /* The number of blocks guarantied for class #t in MAC0. t=0,1
-                */
-               REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
-                      e3b0_val.mac_0_class_t_guarantied);
-               REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
-                      e3b0_val.mac_0_class_t_guarantied);
-               /* The hysteresis on the guarantied buffer space for class in
-                * MAC0.  t=0,1
-                */
-               REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
-                      e3b0_val.mac_0_class_t_guarantied_hyst);
-               REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
-                      e3b0_val.mac_0_class_t_guarantied_hyst);
-
-               /* The number of blocks guarantied for class #t in MAC1.t=0,1
-                */
-               REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
-                      e3b0_val.mac_1_class_t_guarantied);
-               REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
-                      e3b0_val.mac_1_class_t_guarantied);
-               /* The hysteresis on the guarantied buffer space for class #t
-                * in MAC1.  t=0,1
-                */
-               REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
-                      e3b0_val.mac_1_class_t_guarantied_hyst);
-               REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
-                      e3b0_val.mac_1_class_t_guarantied_hyst);
-       }
-
-       return bnx2x_status;
-}
-
 /******************************************************************************
 * Description:
 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
@@ -2705,11 +2206,6 @@ int bnx2x_update_pfc(struct link_params *params,
        /* Update NIG params */
        bnx2x_update_pfc_nig(params, vars, pfc_params);
 
-       /* Update BRB params */
-       bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
-       if (bnx2x_status)
-               return bnx2x_status;
-
        if (!vars->link_up)
                return bnx2x_status;
 
index 5a5fbf57c4b4fdce4d15000113ef9987e67ec5f5..71971a161bd199746595d501691f19300c5ff2ad 100644 (file)
@@ -5619,7 +5619,7 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
        memset(rdata, 0, sizeof(*rdata));
 
        /* Fill the ramrod data with provided parameters */
-       rdata->function_mode = cpu_to_le16(start_params->mf_mode);
+       rdata->function_mode = (u8)start_params->mf_mode;
        rdata->sd_vlan_tag   = cpu_to_le16(start_params->sd_vlan_tag);
        rdata->path_id       = BP_PATH(bp);
        rdata->network_cos_mode = start_params->network_cos_mode;
index 2107d79d69b37ca3f6740735e0971f31c0e3bbe0..cc8434fd606e2a089e20708f4ee12794fdfdd1e1 100644 (file)
@@ -4891,6 +4891,9 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
        buf_map = udev->l2_buf_map;
        for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
                struct eth_tx_start_bd *start_bd = &txbd->start_bd;
+               struct eth_tx_parse_bd_e1x *pbd_e1x =
+                       &((txbd + 1)->parse_bd_e1x);
+               struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
                struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
 
                start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
@@ -4900,10 +4903,15 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
                start_bd->nbytes = cpu_to_le16(0x10);
                start_bd->nbd = cpu_to_le16(3);
                start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
-               start_bd->general_data = (UNICAST_ADDRESS <<
-                       ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
+               start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
                start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
 
+               if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
+                       pbd_e2->parsing_data = (UNICAST_ADDRESS <<
+                                ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
+               else
+                        pbd_e1x->global_data = (UNICAST_ADDRESS <<
+                               ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
        }
 
        val = (u64) ring_map >> 32;
index 382c98b0cc0c6feb959cd0f4e9dca7a078159c84..ede3db35d757e9c51a5f07cef320ecf323515295 100644 (file)
@@ -896,7 +896,7 @@ struct tstorm_tcp_tcp_ag_context_section {
        u32 snd_nxt;
        u32 rtt_seq;
        u32 rtt_time;
-       u32 __reserved66;
+       u32 wnd_right_edge_local;
        u32 wnd_right_edge;
        u32 tcp_agg_vars1;
 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
index 2e92c348083e04d955ea6702092dd3c2c4d90e0c..865095aad1f6494d985f4dbe15ab1ae198e7e74f 100644 (file)
@@ -14,8 +14,8 @@
 
 #include "bnx2x/bnx2x_mfw_req.h"
 
-#define CNIC_MODULE_VERSION    "2.5.13"
-#define CNIC_MODULE_RELDATE    "Sep 07, 2012"
+#define CNIC_MODULE_VERSION    "2.5.14"
+#define CNIC_MODULE_RELDATE    "Sep 30, 2012"
 
 #define CNIC_ULP_RDMA          0
 #define CNIC_ULP_ISCSI         1