drm/nouveau/nvif: split out fifo interface definitions
authorBen Skeggs <bskeggs@redhat.com>
Sun, 8 Nov 2015 01:28:26 +0000 (11:28 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Mon, 11 Jan 2016 01:17:40 +0000 (11:17 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
23 files changed:
drivers/gpu/drm/nouveau/include/nvif/cl006b.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvif/cl506e.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvif/cl506f.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvif/cl826e.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvif/cl826f.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvif/cl906f.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvif/cla06f.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvif/class.h
drivers/gpu/drm/nouveau/nouveau_abi16.c
drivers/gpu/drm/nouveau/nouveau_chan.c
drivers/gpu/drm/nouveau/nouveau_drm.c
drivers/gpu/drm/nouveau/nouveau_fence.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c

diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl006b.h b/drivers/gpu/drm/nouveau/include/nvif/cl006b.h
new file mode 100644 (file)
index 0000000..309ab8a
--- /dev/null
@@ -0,0 +1,11 @@
+#ifndef __NVIF_CL006B_H__
+#define __NVIF_CL006B_H__
+
+struct nv03_channel_dma_v0 {
+       __u8  version;
+       __u8  chid;
+       __u8  pad02[2];
+       __u32 offset;
+       __u64 pushbuf;
+};
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506e.h b/drivers/gpu/drm/nouveau/include/nvif/cl506e.h
new file mode 100644 (file)
index 0000000..aa94b8c
--- /dev/null
@@ -0,0 +1,12 @@
+#ifndef __NVIF_CL506E_H__
+#define __NVIF_CL506E_H__
+
+struct nv50_channel_dma_v0 {
+       __u8  version;
+       __u8  chid;
+       __u8  pad02[6];
+       __u64 vm;
+       __u64 pushbuf;
+       __u64 offset;
+};
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506f.h b/drivers/gpu/drm/nouveau/include/nvif/cl506f.h
new file mode 100644 (file)
index 0000000..3b71019
--- /dev/null
@@ -0,0 +1,13 @@
+#ifndef __NVIF_CL506F_H__
+#define __NVIF_CL506F_H__
+
+struct nv50_channel_gpfifo_v0 {
+       __u8  version;
+       __u8  chid;
+       __u8  pad02[2];
+       __u32 ilength;
+       __u64 ioffset;
+       __u64 pushbuf;
+       __u64 vm;
+};
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h
new file mode 100644 (file)
index 0000000..05e6ef7
--- /dev/null
@@ -0,0 +1,14 @@
+#ifndef __NVIF_CL826E_H__
+#define __NVIF_CL826E_H__
+
+struct g82_channel_dma_v0 {
+       __u8  version;
+       __u8  chid;
+       __u8  pad02[6];
+       __u64 vm;
+       __u64 pushbuf;
+       __u64 offset;
+};
+
+#define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h
new file mode 100644 (file)
index 0000000..cecafcb
--- /dev/null
@@ -0,0 +1,15 @@
+#ifndef __NVIF_CL826F_H__
+#define __NVIF_CL826F_H__
+
+struct g82_channel_gpfifo_v0 {
+       __u8  version;
+       __u8  chid;
+       __u8  pad02[2];
+       __u32 ilength;
+       __u64 ioffset;
+       __u64 pushbuf;
+       __u64 vm;
+};
+
+#define G82_CHANNEL_GPFIFO_V0_NTFY_UEVENT                                  0x00
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h
new file mode 100644 (file)
index 0000000..2caf083
--- /dev/null
@@ -0,0 +1,14 @@
+#ifndef __NVIF_CL906F_H__
+#define __NVIF_CL906F_H__
+
+struct fermi_channel_gpfifo_v0 {
+       __u8  version;
+       __u8  chid;
+       __u8  pad02[2];
+       __u32 ilength;
+       __u64 ioffset;
+       __u64 vm;
+};
+
+#define FERMI_CHANNEL_GPFIFO_V0_NTFY_UEVENT                                0x00
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h
new file mode 100644 (file)
index 0000000..85b7827
--- /dev/null
@@ -0,0 +1,21 @@
+#ifndef __NVIF_CLA06F_H__
+#define __NVIF_CLA06F_H__
+
+struct kepler_channel_gpfifo_a_v0 {
+       __u8  version;
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC                           0x02
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
+       __u8  engine;
+       __u16 chid;
+       __u32 ilength;
+       __u64 ioffset;
+       __u64 vm;
+};
+
+#define KEPLER_CHANNEL_GPFIFO_A_V0_NTFY_UEVENT                             0x00
+#endif
index aa1e0634a28b26df85676198fb3b552c94e00ce3..9076aa7e326870057850ec217f54553e3bc2f009 100644 (file)
 
 #define NV04_DISP                                     /* cl0046.h */ 0x00000046
 
-#define NV03_CHANNEL_DMA                                             0x0000006b
-#define NV10_CHANNEL_DMA                                             0x0000006e
-#define NV17_CHANNEL_DMA                                             0x0000176e
-#define NV40_CHANNEL_DMA                                             0x0000406e
-#define NV50_CHANNEL_DMA                                             0x0000506e
-#define G82_CHANNEL_DMA                                              0x0000826e
-
-#define NV50_CHANNEL_GPFIFO                                          0x0000506f
-#define G82_CHANNEL_GPFIFO                                           0x0000826f
-#define FERMI_CHANNEL_GPFIFO                                         0x0000906f
-#define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
-#define MAXWELL_CHANNEL_GPFIFO_A                                     0x0000b06f
+#define NV03_CHANNEL_DMA                              /* cl506b.h */ 0x0000006b
+#define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e
+#define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e
+#define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e
+#define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e
+#define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e
+
+#define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f
+#define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f
+#define FERMI_CHANNEL_GPFIFO                          /* cl906f.h */ 0x0000906f
+#define KEPLER_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000a06f
+#define MAXWELL_CHANNEL_GPFIFO_A                      /* cla06f.h */ 0x0000b06f
 
 #define NV50_DISP                                     /* cl5070.h */ 0x00005070
 #define G82_DISP                                      /* cl5070.h */ 0x00008270
@@ -389,67 +389,4 @@ struct nvif_control_pstate_user_v0 {
        __s8  pwrsrc; /*  in: target power source */
        __u8  pad03[5];
 };
-
-
-/*******************************************************************************
- * DMA FIFO channels
- ******************************************************************************/
-
-struct nv03_channel_dma_v0 {
-       __u8  version;
-       __u8  chid;
-       __u8  pad02[2];
-       __u32 offset;
-       __u64 pushbuf;
-};
-
-struct nv50_channel_dma_v0 {
-       __u8  version;
-       __u8  chid;
-       __u8  pad02[6];
-       __u64 vm;
-       __u64 pushbuf;
-       __u64 offset;
-};
-
-#define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00
-
-/*******************************************************************************
- * GPFIFO channels
- ******************************************************************************/
-
-struct nv50_channel_gpfifo_v0 {
-       __u8  version;
-       __u8  chid;
-       __u8  pad02[2];
-       __u32 ilength;
-       __u64 ioffset;
-       __u64 pushbuf;
-       __u64 vm;
-};
-
-struct fermi_channel_gpfifo_v0 {
-       __u8  version;
-       __u8  chid;
-       __u8  pad02[2];
-       __u32 ilength;
-       __u64 ioffset;
-       __u64 vm;
-};
-
-struct kepler_channel_gpfifo_a_v0 {
-       __u8  version;
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC                           0x02
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
-       __u8  engine;
-       __u16 chid;
-       __u32 ilength;
-       __u64 ioffset;
-       __u64 vm;
-};
 #endif
index a6afeaf17f15d2e364f4dffa57ac462bb21aeda9..6efb149c952617e72977c63445368b34b635f900 100644 (file)
@@ -25,6 +25,7 @@
 #include <nvif/driver.h>
 #include <nvif/ioctl.h>
 #include <nvif/class.h>
+#include <nvif/cla06f.h>
 #include <nvif/unpack.h>
 
 #include "nouveau_drm.h"
index 0a853ad5a21fddfaaf917ed9897197bd3715c292..d9c784c5db4a345ca72ad2f9bd2f5764342d2e01 100644 (file)
 
 #include <nvif/os.h>
 #include <nvif/class.h>
+#include <nvif/cl006b.h>
+#include <nvif/cl506f.h>
+#include <nvif/cl906f.h>
+#include <nvif/cla06f.h>
 #include <nvif/ioctl.h>
 
 /*XXX*/
index e82545cde01185c800c74ba7b998c2947393a9d0..fc45bde85d64643ca28352f75abc23384d9a2b09 100644 (file)
@@ -37,6 +37,7 @@
 #include <core/pci.h>
 #include <core/tegra.h>
 
+#include <nvif/cla06f.h>
 #include <nvif/if0004.h>
 
 #include "nouveau_drm.h"
index 574c36b492ee4556568f836e48bf7798aff467d0..9a8c5b727f59d39235fc844f6ab8fbfc692009f3 100644 (file)
@@ -30,6 +30,7 @@
 #include <linux/hrtimer.h>
 #include <trace/events/fence.h>
 
+#include <nvif/cl826e.h>
 #include <nvif/notify.h>
 #include <nvif/event.h>
 
index 04305241ceed3ad4b84d448b8d6e2fa7d00f35fc..aeb3387a3fb0c09f7af3fe31a0e6a650c2f9fda4 100644 (file)
@@ -28,7 +28,7 @@
 #include <subdev/mmu.h>
 #include <subdev/timer.h>
 
-#include <nvif/class.h>
+#include <nvif/cl826e.h>
 
 int
 g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
index a5ca52c7b74ffdebb92bd850785ab762bbaa1411..4091727d07edb1e30a789c1a4b0499a449158673 100644 (file)
@@ -27,6 +27,7 @@
 #include <core/ramht.h>
 
 #include <nvif/class.h>
+#include <nvif/cl826e.h>
 #include <nvif/unpack.h>
 
 static int
@@ -35,7 +36,7 @@ g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
 {
        struct nvkm_object *parent = oclass->parent;
        union {
-               struct nv50_channel_dma_v0 v0;
+               struct g82_channel_dma_v0 v0;
        } *args = data;
        struct nv50_fifo *fifo = nv50_fifo(base);
        struct nv50_fifo_chan *chan;
index bfcc6408a77203a88de81b7d1938f558de1039ab..51af281a0b14c755b262b2a81dfa940a02ab35e7 100644 (file)
@@ -29,6 +29,7 @@
 #include <subdev/instmem.h>
 
 #include <nvif/class.h>
+#include <nvif/cl006b.h>
 #include <nvif/unpack.h>
 
 void
index 34f68e5bd0404ed565e2bbbc7de59b7f0b0485b5..e676af4504c2dec945c2e58e3e3d3be0ab5d6e71 100644 (file)
@@ -29,6 +29,7 @@
 #include <subdev/instmem.h>
 
 #include <nvif/class.h>
+#include <nvif/cl006b.h>
 #include <nvif/unpack.h>
 
 static int
index ed7cc9f2b540347bc02d7752c51808674df96d61..ee364e287d0a1fd160a91452224a57a3df394171 100644 (file)
@@ -29,6 +29,7 @@
 #include <subdev/instmem.h>
 
 #include <nvif/class.h>
+#include <nvif/cl006b.h>
 #include <nvif/unpack.h>
 
 static int
index 043b6c325949962a0800082eee7e02b1eea2f9ad..c75a41eaaa24436f4a7aaa8d9dd1b14ec7a787a1 100644 (file)
@@ -29,6 +29,7 @@
 #include <subdev/instmem.h>
 
 #include <nvif/class.h>
+#include <nvif/cl006b.h>
 #include <nvif/unpack.h>
 
 static bool
index 6b3b15f12c392f5e0c1cdf4072c2c6d3494eed67..982bed04c6a4f317cc1de6f5e45f0fb80fa324b1 100644 (file)
@@ -27,6 +27,7 @@
 #include <core/ramht.h>
 
 #include <nvif/class.h>
+#include <nvif/cl506e.h>
 #include <nvif/unpack.h>
 
 static int
index 820132363f68f61c7cca40e2bf7c640796db17ce..e463100f74da559ad36dea9989d107cdd5581cb6 100644 (file)
@@ -27,6 +27,7 @@
 #include <core/ramht.h>
 
 #include <nvif/class.h>
+#include <nvif/cl826f.h>
 #include <nvif/unpack.h>
 
 static int
@@ -35,7 +36,7 @@ g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
 {
        struct nvkm_object *parent = oclass->parent;
        union {
-               struct nv50_channel_gpfifo_v0 v0;
+               struct g82_channel_gpfifo_v0 v0;
        } *args = data;
        struct nv50_fifo *fifo = nv50_fifo(base);
        struct nv50_fifo_chan *chan;
index 3f3767518558b1b2e93b8251d226925870bb6cc6..8db9cf018c890b63ed4b3a9545be88ebf5dd6a2a 100644 (file)
@@ -29,6 +29,7 @@
 #include <subdev/timer.h>
 
 #include <nvif/class.h>
+#include <nvif/cl906f.h>
 #include <nvif/unpack.h>
 
 static u32
index 500e7d2f2df79cdba3b9ff1d6f39dd49cf1e110d..ba2bfe59c041a61d67e763235c00b4a3ca7bfa86 100644 (file)
@@ -30,6 +30,7 @@
 #include <subdev/timer.h>
 
 #include <nvif/class.h>
+#include <nvif/cla06f.h>
 #include <nvif/unpack.h>
 
 static int
index a8c69f878221127beb788f72d406de0418308b4b..94456cad3ef0dd65bed9da63f6145f49568f210d 100644 (file)
@@ -27,6 +27,7 @@
 #include <core/ramht.h>
 
 #include <nvif/class.h>
+#include <nvif/cl506f.h>
 #include <nvif/unpack.h>
 
 static int