MIPS: MSP71xx: Fix build error
authorStefan Hengelein <stefan.hengelein@fau.de>
Sun, 19 Oct 2014 18:04:26 +0000 (20:04 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 24 Oct 2014 00:37:18 +0000 (02:37 +0200)
When CONFIG_MIPS_MT_SMP is enabled, the following compilation error
occurs:

arch/mips/pmcs-msp71xx/msp_irq_cic.c:134: error: ‘irq’ undeclared

This code clearly never saw a compiler.
The surrounding code suggests, that 'd->irq' was intended, not
'irq'.

This error was found with vampyr.

Signed-off-by: Stefan Hengelein <stefan.hengelein@fau.de>
Fixes: d7881fbdf866d7d0 ("MIPS: msp71xx: Convert to new irq_chip functions")
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8116/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pmcs-msp71xx/msp_irq_cic.c

index b8df2f7b3328e61f8fc7d9da9f78b777bf829632..1207ec4dfb77021a6a114d776684ccfbe696ea00 100644 (file)
@@ -131,11 +131,11 @@ static int msp_cic_irq_set_affinity(struct irq_data *d,
        int cpu;
        unsigned long flags;
        unsigned int  mtflags;
-       unsigned long imask = (1 << (irq - MSP_CIC_INTBASE));
+       unsigned long imask = (1 << (d->irq - MSP_CIC_INTBASE));
        volatile u32 *cic_mask = (volatile u32 *)CIC_VPE0_MSK_REG;
 
        /* timer balancing should be disabled in kernel code */
-       BUG_ON(irq == MSP_INT_VPE0_TIMER || irq == MSP_INT_VPE1_TIMER);
+       BUG_ON(d->irq == MSP_INT_VPE0_TIMER || d->irq == MSP_INT_VPE1_TIMER);
 
        LOCK_CORE(flags, mtflags);
        /* enable if any of each VPE's TCs require this IRQ */