ENGR00301552-1 ARM: imx6sx: Correct audio_clk in the clock tree

We currently has asrc_* clocks in the imx6sx clock tree while actually,
according to the Reference Manual, all of them should be named after the
audio_clk that controls the external MCLK output from MCLK pad of AUDMUX.

Thus fix it along with its gate clock missing in the current clock tree.

Meanwhile, this patch also configures a default clock rate for it -- 24MHz.

Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>

diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index dd370cbcb6c5d5d6412e11ff0e9a8f710ee10a52..1bc072c0d7993657f4c582d599e30de42999bb44 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -226,7 +226,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clks[IMX6SX_CLK_UART_SEL]           = imx_clk_mux("uart_sel",         base + 0x24,  6,      1,      uart_sels,         ARRAY_SIZE(uart_sels));
        clks[IMX6SX_CLK_QSPI2_SEL]          = imx_clk_mux_flags_reparent("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT);
        clks[IMX6SX_CLK_SPDIF_SEL]          = imx_clk_mux("spdif_sel",        base + 0x30,  20,     2,      audio_sels,        ARRAY_SIZE(audio_sels));
-       clks[IMX6SX_CLK_ASRC_SEL]           = imx_clk_mux("asrc_sel",         base + 0x30,  7,      2,      audio_sels,        ARRAY_SIZE(audio_sels));
+       clks[IMX6SX_CLK_AUDIO_SEL]          = imx_clk_mux("audio_sel",        base + 0x30,  7,      2,      audio_sels,        ARRAY_SIZE(audio_sels));
        clks[IMX6SX_CLK_ENET_PRE_SEL]       = imx_clk_mux("enet_pre_sel",     base + 0x34,  15,     3,      enet_pre_sels,     ARRAY_SIZE(enet_pre_sels));
        clks[IMX6SX_CLK_ENET_SEL]           = imx_clk_mux("enet_sel",         base + 0x34,  9,      3,      enet_sels,         ARRAY_SIZE(enet_sels));
        clks[IMX6SX_CLK_M4_PRE_SEL]         = imx_clk_mux("m4_pre_sel",       base + 0x34,  6,      3,      m4_pre_sels,       ARRAY_SIZE(m4_pre_sels));
@@ -277,8 +277,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clks[IMX6SX_CLK_SSI2_PODF]          = imx_clk_divider("ssi2_podf",      "ssi2_pred",         base + 0x2c, 0,    6);
        clks[IMX6SX_CLK_SPDIF_PRED]         = imx_clk_divider("spdif_pred",     "spdif_sel",         base + 0x30, 25,   3);
        clks[IMX6SX_CLK_SPDIF_PODF]         = imx_clk_divider("spdif_podf",     "spdif_pred",        base + 0x30, 22,   3);
-       clks[IMX6SX_CLK_ASRC_PRED]          = imx_clk_divider("asrc_pred",      "asrc_sel",          base + 0x30, 12,   3);
-       clks[IMX6SX_CLK_ASRC_PODF]          = imx_clk_divider("asrc_podf",      "asrc_pred",         base + 0x30, 9,    3);
+       clks[IMX6SX_CLK_AUDIO_PRED]         = imx_clk_divider("audio_pred",     "audio_sel",         base + 0x30, 12,   3);
+       clks[IMX6SX_CLK_AUDIO_PODF]         = imx_clk_divider("audio_podf",     "audio_pred",        base + 0x30, 9,    3);
        clks[IMX6SX_CLK_ENET_PODF]          = imx_clk_divider("enet_podf",      "enet_pre_sel",      base + 0x34, 12,   3);
        clks[IMX6SX_CLK_M4_PODF]            = imx_clk_divider("m4_podf",        "m4_sel",            base + 0x34, 3,    3);
        clks[IMX6SX_CLK_ECSPI_PODF]         = imx_clk_divider("ecspi_podf",     "ecspi_sel",         base + 0x38, 19,   6);
@@ -382,6 +382,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clks[IMX6SX_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
        clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
        clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
+       clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2("audio",         "audio_podf",        base + 0x7c, 14);
        clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
        clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
        clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
@@ -444,6 +445,11 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
        clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
 
+       /* Audio clocks */
+       clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+       clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 24000000);
+       clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
+
        /* default parent of can_sel clock is invalid, manually set it here */
        clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
 

diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 49db3fb9f1888183975853ccf1c1db9e74c96834..2dab46136aca61f7f080f5d3cf8ba23dfff8f4af 100644 (file)
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -75,7 +75,7 @@
 #define IMX6SX_CLK_LDB_DI1_SEL         62
 #define IMX6SX_CLK_LDB_DI0_SEL         63
 #define IMX6SX_CLK_SPDIF_SEL           64
-#define IMX6SX_CLK_ASRC_SEL            65
+#define IMX6SX_CLK_AUDIO_SEL           65
 #define IMX6SX_CLK_ENET_PRE_SEL                66
 #define IMX6SX_CLK_ENET_SEL            67
 #define IMX6SX_CLK_M4_PRE_SEL          68
@@ -119,8 +119,8 @@
 #define IMX6SX_CLK_SSI2_PODF           106
 #define IMX6SX_CLK_SPDIF_PRED          107
 #define IMX6SX_CLK_SPDIF_PODF          108
-#define IMX6SX_CLK_ASRC_PRED           109
-#define IMX6SX_CLK_ASRC_PODF           110
+#define IMX6SX_CLK_AUDIO_PRED          109
+#define IMX6SX_CLK_AUDIO_PODF          110
 #define IMX6SX_CLK_ENET_PODF           111
 #define IMX6SX_CLK_M4_PODF             112
 #define IMX6SX_CLK_ECSPI_PODF          113
@@ -242,6 +242,7 @@
 #define IMX6SX_CLK_ENET_PTP_REF                229
 #define IMX6SX_CLK_ENET2_REF           230
 #define IMX6SX_CLK_ENET2_REF_125M      231
-#define IMX6SX_CLK_CLK_END             232
+#define IMX6SX_CLK_AUDIO               232
+#define IMX6SX_CLK_CLK_END             233
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */