ENGR00303122-3 ARM: imx6sx: fix ASRC related clocks in the clock tree
authorNicolin Chen <Guangyu.Chen@freescale.com>
Tue, 11 Mar 2014 08:21:44 +0000 (16:21 +0800)
committerNitin Garg <nitin.garg@freescale.com>
Wed, 16 Apr 2014 13:57:54 +0000 (08:57 -0500)
According to imx6sx RM, there are three clock providers for ASRC:
Module clock    Clock root      Gate
asrck_clock_d   spdif0_clk_root N/A
ipg_clk         ahb_clk_root    asrc_clk_enable
mem_clk         ahb_clk_root    asrc_clk_enable

while the current clock tree describes a clock named 'ASRC' that only
describes the asrc_clk_enable function.

Thus this patch first adds the other missing clocks to ASRC.

[ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk
  to ASRC in the devicetree directly. ]

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
arch/arm/mach-imx/clk-imx6sx.c
include/dt-bindings/clock/imx6sx-clock.h

index b95988383e02e835ee77ba20f4bc5c25e0ea9e6a..3d6958ba8e62126b5982a086cc9b280ac2dd9a1c 100644 (file)
@@ -318,7 +318,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clks[IMX6SX_CLK_AIPS_TZ1]     = imx_clk_gate2("aips_tz1",      "ahb",               base + 0x68, 0);
        clks[IMX6SX_CLK_AIPS_TZ2]     = imx_clk_gate2("aips_tz2",      "ahb",               base + 0x68, 2);
        clks[IMX6SX_CLK_APBH_DMA]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
-       clks[IMX6SX_CLK_ASRC]         = imx_clk_gate2("asrc",          "ahb",               base + 0x68, 6);
+       clks[IMX6SX_CLK_ASRC_GATE]    = imx_clk_gate2("asrc_gate",     "ahb",               base + 0x68, 6);
+       clks[IMX6SX_CLK_ASRC_MEM]     = imx_clk_fixed_factor("asrc_mem", "asrc_gate", 1, 1);
+       clks[IMX6SX_CLK_ASRC_IPG]     = imx_clk_fixed_factor("asrc_ipg", "asrc_gate", 1, 1);
        clks[IMX6SX_CLK_CAAM_MEM]     = imx_clk_gate2("caam_mem",      "ahb",               base + 0x68, 8);
        clks[IMX6SX_CLK_CAAM_ACLK]    = imx_clk_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
        clks[IMX6SX_CLK_CAAM_IPG]     = imx_clk_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
index 9f75dbc34b528dfd82ee46dfadb2205e3675a19a..38f5f147e3399895071897b718169726573236cb 100644 (file)
 #define IMX6SX_CLK_AIPS_TZ1            130
 #define IMX6SX_CLK_AIPS_TZ2            131
 #define IMX6SX_CLK_APBH_DMA            132
-#define IMX6SX_CLK_ASRC                        133
+#define IMX6SX_CLK_ASRC_GATE           133
 #define IMX6SX_CLK_CAAM_MEM            134
 #define IMX6SX_CLK_CAAM_ACLK           135
 #define IMX6SX_CLK_CAAM_IPG            136
 #define IMX6SX_CLK_AUDIO               232
 #define IMX6SX_CLK_LVDS1_SEL           233
 #define IMX6SX_CLK_LVDS1_OUT           234
-#define IMX6SX_CLK_CLK_END             235
+#define IMX6SX_CLK_ASRC_IPG            235
+#define IMX6SX_CLK_ASRC_MEM            236
+#define IMX6SX_CLK_CLK_END             237
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */