clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
- clks[IMX6SX_CLK_ASRC] = imx_clk_gate2("asrc", "ahb", base + 0x68, 6);
+ clks[IMX6SX_CLK_ASRC_GATE] = imx_clk_gate2("asrc_gate", "ahb", base + 0x68, 6);
+ clks[IMX6SX_CLK_ASRC_MEM] = imx_clk_fixed_factor("asrc_mem", "asrc_gate", 1, 1);
+ clks[IMX6SX_CLK_ASRC_IPG] = imx_clk_fixed_factor("asrc_ipg", "asrc_gate", 1, 1);
clks[IMX6SX_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
clks[IMX6SX_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
clks[IMX6SX_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
#define IMX6SX_CLK_AIPS_TZ1 130
#define IMX6SX_CLK_AIPS_TZ2 131
#define IMX6SX_CLK_APBH_DMA 132
-#define IMX6SX_CLK_ASRC 133
+#define IMX6SX_CLK_ASRC_GATE 133
#define IMX6SX_CLK_CAAM_MEM 134
#define IMX6SX_CLK_CAAM_ACLK 135
#define IMX6SX_CLK_CAAM_IPG 136
#define IMX6SX_CLK_AUDIO 232
#define IMX6SX_CLK_LVDS1_SEL 233
#define IMX6SX_CLK_LVDS1_OUT 234
-#define IMX6SX_CLK_CLK_END 235
+#define IMX6SX_CLK_ASRC_IPG 235
+#define IMX6SX_CLK_ASRC_MEM 236
+#define IMX6SX_CLK_CLK_END 237
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */