ENGR00305648-2 ARM: imx6sx: Add SAI ipg clock to the clock tree

There's one clock for SAI memory access missing in the clock tree. Thus add it.

Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>

diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 95ca30b8de0d36ddac2b8aeb997424cd4d5d4319..c4b333bdef8d1fdae689e5df4a9eea92aeb92c84 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -403,6 +403,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clks[IMX6SX_CLK_SSI3]         = imx_clk_gate2("ssi3",          "ssi3_podf",         base + 0x7c, 22);
        clks[IMX6SX_CLK_UART_IPG]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
        clks[IMX6SX_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",   "uart_podf",         base + 0x7c, 26);
+       clks[IMX6SX_CLK_SAI1_IPG]     = imx_clk_gate2("sai1_ipg",      "ipg",               base + 0x7c, 28);
+       clks[IMX6SX_CLK_SAI2_IPG]     = imx_clk_gate2("sai2_ipg",      "ipg",               base + 0x7c, 30);
        clks[IMX6SX_CLK_SAI1]         = imx_clk_gate2("sai1",          "ssi1_podf",         base + 0x7c, 28);
        clks[IMX6SX_CLK_SAI2]         = imx_clk_gate2("sai2",          "ssi2_podf",         base + 0x7c, 30);
 

diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index 38f5f147e3399895071897b718169726573236cb..0cc658b7e436b5006915a08c9ea68100b9840d1d 100644 (file)
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -247,6 +247,8 @@
 #define IMX6SX_CLK_LVDS1_OUT           234
 #define IMX6SX_CLK_ASRC_IPG            235
 #define IMX6SX_CLK_ASRC_MEM            236
-#define IMX6SX_CLK_CLK_END             237
+#define IMX6SX_CLK_SAI1_IPG            237
+#define IMX6SX_CLK_SAI2_IPG            238
+#define IMX6SX_CLK_CLK_END             239
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */