--- /dev/null
- This adds support for the internal SDHC2 used on CPUIMX27 used
+ config IMX_HAVE_DMA_V1
+ bool
+
+ if ARCH_MX1
+
+ config SOC_IMX1
+ select CPU_ARM920T
+ select IMX_HAVE_DMA_V1
+ select IMX_HAVE_IOMUX_V1
+ bool
+
+ comment "MX1 platforms:"
+ config MACH_MXLADS
+ bool
+
+ config ARCH_MX1ADS
+ bool "MX1ADS platform"
+ select MACH_MXLADS
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ help
+ Say Y here if you are using Motorola MX1ADS/MXLADS boards
+
+ config MACH_SCB9328
+ bool "Synertronixx scb9328"
+ select IMX_HAVE_PLATFORM_IMX_UART
+ help
+ Say Y here if you are using a Synertronixx scb9328 board
+
+ endif
+
+ if ARCH_MX2
+
+ config SOC_IMX21
+ select CPU_ARM926T
+ select ARCH_MXC_AUDMUX_V1
+ select IMX_HAVE_DMA_V1
+ select IMX_HAVE_IOMUX_V1
+ bool
+
+ config SOC_IMX27
+ select CPU_ARM926T
+ select ARCH_MXC_AUDMUX_V1
+ select IMX_HAVE_DMA_V1
+ select IMX_HAVE_IOMUX_V1
+ bool
+
+ choice
+ prompt "CPUs:"
+ default MACH_MX21
+
+ config MACH_MX21
+ bool "i.MX21 support"
+ select SOC_IMX21
+ help
+ This enables support for Freescale's MX2 based i.MX21 processor.
+
+ config MACH_MX27
+ bool "i.MX27 support"
+ select SOC_IMX27
+ help
+ This enables support for Freescale's MX2 based i.MX27 processor.
+
+ endchoice
+
+ endif
+
+ if MACH_MX21
+
+ comment "MX21 platforms:"
+
+ config MACH_MX21ADS
+ bool "MX21ADS platform"
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ help
+ Include support for MX21ADS platform. This includes specific
+ configurations for the board and its peripherals.
+
+ endif
+
+ if MACH_MX27
+
+ comment "MX27 platforms:"
+
+ config MACH_MX27ADS
+ bool "MX27ADS platform"
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ help
+ Include support for MX27ADS platform. This includes specific
+ configurations for the board and its peripherals.
+
+ config MACH_PCM038
+ bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for phyCORE-i.MX27 (aka pcm038) platform. This
+ includes specific configurations for the module and its peripherals.
+
+ choice
+ prompt "Baseboard"
+ depends on MACH_PCM038
+ default MACH_PCM970_BASEBOARD
+
+ config MACH_PCM970_BASEBOARD
+ prompt "PHYTEC PCM970 development board"
+ bool
+ help
+ This adds board specific devices that can be found on Phytec's
+ PCM970 evaluation board.
+
+ endchoice
+
+ config MACH_CPUIMX27
+ bool "Eukrea CPUIMX27 module"
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ help
+ Include support for Eukrea CPUIMX27 platform. This includes
+ specific configurations for the module and its peripherals.
+
+ config MACH_EUKREA_CPUIMX27_USESDHC2
+ bool "CPUIMX27 integrates SDHC2 module"
+ depends on MACH_CPUIMX27
+ help
++ This adds support for the internal SDHC2 used on CPUIMX27
+ for wifi or eMMC.
+
++config MACH_EUKREA_CPUIMX27_USEUART4
++ bool "CPUIMX27 integrates UART4 module"
++ depends on MACH_CPUIMX27
++ help
++ This adds support for the internal UART4 used on CPUIMX27
++ for bluetooth.
++
+ choice
+ prompt "Baseboard"
+ depends on MACH_CPUIMX27
+ default MACH_EUKREA_MBIMX27_BASEBOARD
+
+ config MACH_EUKREA_MBIMX27_BASEBOARD
+ prompt "Eukrea MBIMX27 development board"
+ bool
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ help
+ This adds board specific devices that can be found on Eukrea's
+ MBIMX27 evaluation board.
+
+ endchoice
+
+ config MACH_MX27_3DS
+ bool "MX27PDK platform"
+ select IMX_HAVE_PLATFORM_IMX_UART
+ help
+ Include support for MX27PDK platform. This includes specific
+ configurations for the board and its peripherals.
+
+ config MACH_IMX27LITE
+ bool "LogicPD MX27 LITEKIT platform"
+ select IMX_HAVE_PLATFORM_IMX_UART
+ help
+ Include support for MX27 LITEKIT platform. This includes specific
+ configurations for the board and its peripherals.
+
+ config MACH_PCA100
+ bool "Phytec phyCARD-s (pca100)"
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for phyCARD-s (aka pca100) platform. This
+ includes specific configurations for the module and its peripherals.
+
+ config MACH_MXT_TD60
+ bool "Maxtrack i-MXT TD60"
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ help
+ Include support for i-MXT (aka td60) platform. This
+ includes specific configurations for the module and its peripherals.
+
+ endif
--- /dev/null
-obj-$(CONFIG_MACH_MX27) += cpu-imx27.o
+ #
+ # Makefile for the linux kernel.
+ #
+
+ # Object file lists.
+
+ obj-y := devices.o
+
+ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
+
+ obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
+ obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+
++obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
+ obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
+
+ # Support for CMOS sensor interface
+ obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+
+ obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
+ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
+
+ obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+
+ obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
+ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
+ obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
+ obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
+ obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
+ obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
+ obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
+ obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
+ obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
--- /dev/null
- _REGISTER_CLOCK(NULL, "csi", csi_clk)
+ /*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+ #include <linux/clk.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+
+ #include <asm/clkdev.h>
+ #include <asm/div64.h>
+
+ #include <mach/clock.h>
+ #include <mach/common.h>
+ #include <mach/hardware.h>
+
+ #define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
+
+ /* Register offsets */
+ #define CCM_CSCR IO_ADDR_CCM(0x0)
+ #define CCM_MPCTL0 IO_ADDR_CCM(0x4)
+ #define CCM_MPCTL1 IO_ADDR_CCM(0x8)
+ #define CCM_SPCTL0 IO_ADDR_CCM(0xc)
+ #define CCM_SPCTL1 IO_ADDR_CCM(0x10)
+ #define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
+ #define CCM_PCDR0 IO_ADDR_CCM(0x18)
+ #define CCM_PCDR1 IO_ADDR_CCM(0x1c)
+ #define CCM_PCCR0 IO_ADDR_CCM(0x20)
+ #define CCM_PCCR1 IO_ADDR_CCM(0x24)
+ #define CCM_CCSR IO_ADDR_CCM(0x28)
+ #define CCM_PMCTL IO_ADDR_CCM(0x2c)
+ #define CCM_PMCOUNT IO_ADDR_CCM(0x30)
+ #define CCM_WKGDCTL IO_ADDR_CCM(0x34)
+
+ #define CCM_CSCR_UPDATE_DIS (1 << 31)
+ #define CCM_CSCR_SSI2 (1 << 23)
+ #define CCM_CSCR_SSI1 (1 << 22)
+ #define CCM_CSCR_VPU (1 << 21)
+ #define CCM_CSCR_MSHC (1 << 20)
+ #define CCM_CSCR_SPLLRES (1 << 19)
+ #define CCM_CSCR_MPLLRES (1 << 18)
+ #define CCM_CSCR_SP (1 << 17)
+ #define CCM_CSCR_MCU (1 << 16)
+ #define CCM_CSCR_OSC26MDIV (1 << 4)
+ #define CCM_CSCR_OSC26M (1 << 3)
+ #define CCM_CSCR_FPM (1 << 2)
+ #define CCM_CSCR_SPEN (1 << 1)
+ #define CCM_CSCR_MPEN (1 << 0)
+
+ /* i.MX27 TO 2+ */
+ #define CCM_CSCR_ARM_SRC (1 << 15)
+
+ #define CCM_SPCTL1_LF (1 << 15)
+ #define CCM_SPCTL1_BRMO (1 << 6)
+
+ static struct clk mpll_main1_clk, mpll_main2_clk;
+
+ static int clk_pccr_enable(struct clk *clk)
+ {
+ unsigned long reg;
+
+ if (!clk->enable_reg)
+ return 0;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 1 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+ }
+
+ static void clk_pccr_disable(struct clk *clk)
+ {
+ unsigned long reg;
+
+ if (!clk->enable_reg)
+ return;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(1 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+ }
+
+ static int clk_spll_enable(struct clk *clk)
+ {
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg |= CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+
+ while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
+
+ return 0;
+ }
+
+ static void clk_spll_disable(struct clk *clk)
+ {
+ unsigned long reg;
+
+ reg = __raw_readl(CCM_CSCR);
+ reg &= ~CCM_CSCR_SPEN;
+ __raw_writel(reg, CCM_CSCR);
+ }
+
+ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
+ {
+ int cscr = __raw_readl(CCM_CSCR);
+
+ if (clk->parent == parent)
+ return 0;
+
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ if (parent == &mpll_main1_clk) {
+ cscr |= CCM_CSCR_ARM_SRC;
+ } else {
+ if (parent == &mpll_main2_clk)
+ cscr &= ~CCM_CSCR_ARM_SRC;
+ else
+ return -EINVAL;
+ }
+ __raw_writel(cscr, CCM_CSCR);
+ clk->parent = parent;
+ return 0;
+ }
+ return -ENODEV;
+ }
+
+ static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
+ {
+ int div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ if (div > 4)
+ div = 4;
+
+ return parent_rate / div;
+ }
+
+ static int set_rate_cpu(struct clk *clk, unsigned long rate)
+ {
+ unsigned int div;
+ uint32_t reg;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+
+ if (div > 4 || div < 1 || ((parent_rate / div) != rate))
+ return -EINVAL;
+
+ div--;
+
+ reg = __raw_readl(CCM_CSCR);
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ reg &= ~(3 << 12);
+ reg |= div << 12;
+ reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
+ __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
+ } else {
+ printk(KERN_ERR "Can't set CPU frequency!\n");
+ }
+
+ return 0;
+ }
+
+ static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
+ {
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ div = parent_rate / rate;
+ if (parent_rate % rate)
+ div++;
+
+ if (div > 64)
+ div = 64;
+
+ return parent_rate / div;
+ }
+
+ static int set_rate_per(struct clk *clk, unsigned long rate)
+ {
+ u32 reg;
+ u32 div;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (clk->id < 0 || clk->id > 3)
+ return -EINVAL;
+
+ div = parent_rate / rate;
+ if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+ return -EINVAL;
+ div--;
+
+ reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
+ reg |= div << (clk->id << 3);
+ __raw_writel(reg, CCM_PCDR1);
+
+ return 0;
+ }
+
+ static unsigned long get_rate_usb(struct clk *clk)
+ {
+ unsigned long usb_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
+
+ return parent_rate / (usb_pdf + 1U);
+ }
+
+ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
+ {
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ pdf += 4; /* MX27 TO2+ */
+ else
+ pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
+
+ return 2UL * parent_rate / pdf;
+ }
+
+ static unsigned long get_rate_ssi1(struct clk *clk)
+ {
+ return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
+ }
+
+ static unsigned long get_rate_ssi2(struct clk *clk)
+ {
+ return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
+ }
+
+ static unsigned long get_rate_nfc(struct clk *clk)
+ {
+ unsigned long nfc_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
+ else
+ nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
+
+ return parent_rate / (nfc_pdf + 1);
+ }
+
+ static unsigned long get_rate_vpu(struct clk *clk)
+ {
+ unsigned long vpu_pdf;
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
+ vpu_pdf += 4;
+ } else {
+ vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
+ vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
+ }
+
+ return 2UL * parent_rate / vpu_pdf;
+ }
+
+ static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
+ {
+ return clk->parent->round_rate(clk->parent, rate);
+ }
+
+ static unsigned long get_rate_parent(struct clk *clk)
+ {
+ return clk_get_rate(clk->parent);
+ }
+
+ static int set_rate_parent(struct clk *clk, unsigned long rate)
+ {
+ return clk->parent->set_rate(clk->parent, rate);
+ }
+
+ /* in Hz */
+ static unsigned long external_high_reference = 26000000;
+
+ static unsigned long get_rate_high_reference(struct clk *clk)
+ {
+ return external_high_reference;
+ }
+
+ /* in Hz */
+ static unsigned long external_low_reference = 32768;
+
+ static unsigned long get_rate_low_reference(struct clk *clk)
+ {
+ return external_low_reference;
+ }
+
+ static unsigned long get_rate_fpm(struct clk *clk)
+ {
+ return clk_get_rate(clk->parent) * 1024;
+ }
+
+ static unsigned long get_rate_mpll(struct clk *clk)
+ {
+ return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
+ clk_get_rate(clk->parent));
+ }
+
+ static unsigned long get_rate_mpll_main(struct clk *clk)
+ {
+ unsigned long parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ /* i.MX27 TO2:
+ * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
+ * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
+ */
+ if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+ return 2UL * parent_rate / 3UL;
+
+ return parent_rate;
+ }
+
+ static unsigned long get_rate_spll(struct clk *clk)
+ {
+ uint32_t reg;
+ unsigned long rate;
+
+ rate = clk_get_rate(clk->parent);
+
+ reg = __raw_readl(CCM_SPCTL0);
+
+ /* On TO2 we have to write the value back. Otherwise we
+ * read 0 from this register the next time.
+ */
+ if (mx27_revision() >= CHIP_REV_2_0)
+ __raw_writel(reg, CCM_SPCTL0);
+
+ return mxc_decode_pll(reg, rate);
+ }
+
+ static unsigned long get_rate_cpu(struct clk *clk)
+ {
+ u32 div;
+ unsigned long rate;
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
+ else
+ div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (div + 1);
+ }
+
+ static unsigned long get_rate_ahb(struct clk *clk)
+ {
+ unsigned long rate, bclk_pdf;
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
+ else
+ bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (bclk_pdf + 1);
+ }
+
+ static unsigned long get_rate_ipg(struct clk *clk)
+ {
+ unsigned long rate, ipg_pdf;
+
+ if (mx27_revision() >= CHIP_REV_2_0)
+ return clk_get_rate(clk->parent);
+ else
+ ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
+
+ rate = clk_get_rate(clk->parent);
+ return rate / (ipg_pdf + 1);
+ }
+
+ static unsigned long get_rate_per(struct clk *clk)
+ {
+ unsigned long perclk_pdf, parent_rate;
+
+ parent_rate = clk_get_rate(clk->parent);
+
+ if (clk->id < 0 || clk->id > 3)
+ return 0;
+
+ perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
+
+ return parent_rate / (perclk_pdf + 1);
+ }
+
+ /*
+ * the high frequency external clock reference
+ * Default case is 26MHz. Could be changed at runtime
+ * with a call to change_external_high_reference()
+ */
+ static struct clk ckih_clk = {
+ .get_rate = get_rate_high_reference,
+ };
+
+ static struct clk mpll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = get_rate_mpll,
+ };
+
+ /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+ * It provides the clock source whose rate is same as MPLL
+ */
+ static struct clk mpll_main1_clk = {
+ .id = 0,
+ .parent = &mpll_clk,
+ .get_rate = get_rate_mpll_main,
+ };
+
+ /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
+ * It provides the clock source whose rate is same MPLL * 2 / 3
+ */
+ static struct clk mpll_main2_clk = {
+ .id = 1,
+ .parent = &mpll_clk,
+ .get_rate = get_rate_mpll_main,
+ };
+
+ static struct clk ahb_clk = {
+ .parent = &mpll_main2_clk,
+ .get_rate = get_rate_ahb,
+ };
+
+ static struct clk ipg_clk = {
+ .parent = &ahb_clk,
+ .get_rate = get_rate_ipg,
+ };
+
+ static struct clk cpu_clk = {
+ .parent = &mpll_main2_clk,
+ .set_parent = clk_cpu_set_parent,
+ .round_rate = round_rate_cpu,
+ .get_rate = get_rate_cpu,
+ .set_rate = set_rate_cpu,
+ };
+
+ static struct clk spll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = get_rate_spll,
+ .enable = clk_spll_enable,
+ .disable = clk_spll_disable,
+ };
+
+ /*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz.
+ */
+ static struct clk ckil_clk = {
+ .get_rate = get_rate_low_reference,
+ };
+
+ /* Output of frequency pre multiplier */
+ static struct clk fpm_clk = {
+ .parent = &ckil_clk,
+ .get_rate = get_rate_fpm,
+ };
+
+ #define PCCR0 CCM_PCCR0
+ #define PCCR1 CCM_PCCR1
+
+ #define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
+ static struct clk name = { \
+ .id = i, \
+ .enable_reg = er, \
+ .enable_shift = es, \
+ .get_rate = gr, \
+ .enable = clk_pccr_enable, \
+ .disable = clk_pccr_disable, \
+ .secondary = s, \
+ .parent = p, \
+ }
+
+ #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
+ static struct clk name = { \
+ .id = i, \
+ .enable_reg = er, \
+ .enable_shift = es, \
+ .get_rate = get_rate_##getsetround, \
+ .set_rate = set_rate_##getsetround, \
+ .round_rate = round_rate_##getsetround, \
+ .enable = clk_pccr_enable, \
+ .disable = clk_pccr_disable, \
+ .secondary = s, \
+ .parent = p, \
+ }
+
+ /* Forward declaration to keep the following list in order */
+ static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
+ dma_clk1, lcdc_clk2, vpu_clk1;
+
+ /* All clocks we can gate through PCCRx in the order of PCCRx bits */
+ DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk);
+ DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk);
+ DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk);
+ DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
+ DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
+ DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
+ DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
+ DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk);
+
+ DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk);
+ DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk);
+ DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
+ DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
+ DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
+ DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk);
+ DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk);
+ DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk);
+ DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk);
+ DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk);
+ DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
+ DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
+ DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk);
+
+ /* Clocks we cannot directly gate, but drivers need their rates */
+ DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk);
+ DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk);
+ DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk);
+ DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk);
+ DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk);
+ DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk);
+ DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk);
+ DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk);
+ DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk);
+ DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk);
+ DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk);
+ DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk);
+ DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk);
+ DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk);
+ DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk);
+ DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk);
+ DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk);
+ DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk);
+ DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk);
+ DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk);
+ DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk);
+
+ #define _REGISTER_CLOCK(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = &c, \
+ },
+
+ static struct clk_lookup lookups[] = {
+ _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+ _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+ _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
+ _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
+ _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
+ _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
+ _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
+ _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
+ _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
+ _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
+ _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
+ _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
+ _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
+ _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+ _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+ _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+ _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
++ _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
+ _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
+ _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
+ _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
+ _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+ _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+ _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+ _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
+ _REGISTER_CLOCK(NULL, "dma", dma_clk)
+ _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+ _REGISTER_CLOCK(NULL, "brom", brom_clk)
+ _REGISTER_CLOCK(NULL, "emma", emma_clk)
+ _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
+ _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ _REGISTER_CLOCK(NULL, "emi", emi_clk)
+ _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
+ _REGISTER_CLOCK(NULL, "ata", ata_clk)
+ _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
+ _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
+ _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
+ _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+ _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+ _REGISTER_CLOCK(NULL, "iim", iim_clk)
+ _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+ _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
+ _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+ _REGISTER_CLOCK(NULL, "scc", scc_clk)
+ };
+
+ /* Adjust the clock path for TO2 and later */
+ static void __init to2_adjust_clocks(void)
+ {
+ unsigned long cscr = __raw_readl(CCM_CSCR);
+
+ if (mx27_revision() >= CHIP_REV_2_0) {
+ if (cscr & CCM_CSCR_ARM_SRC)
+ cpu_clk.parent = &mpll_main1_clk;
+
+ if (!(cscr & CCM_CSCR_SSI2))
+ ssi1_clk.parent = &spll_clk;
+
+ if (!(cscr & CCM_CSCR_SSI1))
+ ssi1_clk.parent = &spll_clk;
+
+ if (!(cscr & CCM_CSCR_VPU))
+ vpu_clk.parent = &spll_clk;
+ } else {
+ cpu_clk.parent = &mpll_clk;
+ cpu_clk.set_parent = NULL;
+ cpu_clk.round_rate = NULL;
+ cpu_clk.set_rate = NULL;
+ ahb_clk.parent = &mpll_clk;
+
+ per1_clk.parent = &mpll_clk;
+ per2_clk.parent = &mpll_clk;
+ per3_clk.parent = &mpll_clk;
+ per4_clk.parent = &mpll_clk;
+
+ ssi1_clk.parent = &mpll_clk;
+ ssi2_clk.parent = &mpll_clk;
+
+ vpu_clk.parent = &mpll_clk;
+ }
+ }
+
+ /*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+ int __init mx27_clocks_init(unsigned long fref)
+ {
+ u32 cscr = __raw_readl(CCM_CSCR);
+
+ external_high_reference = fref;
+
+ /* detect clock reference for both system PLLs */
+ if (cscr & CCM_CSCR_MCU)
+ mpll_clk.parent = &ckih_clk;
+ else
+ mpll_clk.parent = &fpm_clk;
+
+ if (cscr & CCM_CSCR_SP)
+ spll_clk.parent = &ckih_clk;
+ else
+ spll_clk.parent = &fpm_clk;
+
+ to2_adjust_clocks();
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ /* Turn off all clocks we do not need */
+ __raw_writel(0, CCM_PCCR0);
+ __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
+
+ spll_clk.disable(&spll_clk);
+
+ /* enable basic clocks */
+ clk_enable(&per1_clk);
+ clk_enable(&gpio_clk);
+ clk_enable(&emi_clk);
+ clk_enable(&iim_clk);
+
+ #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+ clk_enable(&uart1_clk);
+ #endif
+
+ mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
+ MX27_INT_GPT1);
+
+ return 0;
+ }
+
--- /dev/null
+ /*
+ * Author: MontaVista Software, Inc.
+ * <source@mvista.com>
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/serial.h>
+
+ #include <mach/irqs.h>
+ #include <mach/hardware.h>
+ #include <mach/common.h>
+ #include <mach/mmc.h>
+
+ #include "devices.h"
+
+ #if defined(CONFIG_ARCH_MX1)
+ static struct resource imx1_camera_resources[] = {
+ {
+ .start = 0x00224000,
+ .end = 0x00224010,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX1_CSI_INT,
+ .end = MX1_CSI_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
+
+ struct platform_device imx1_camera_device = {
+ .name = "mx1-camera",
+ .id = 0, /* This is used to put cameras on this interface */
+ .dev = {
+ .dma_mask = &imx1_camera_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = imx1_camera_resources,
+ .num_resources = ARRAY_SIZE(imx1_camera_resources),
+ };
+
+ static struct resource imx_rtc_resources[] = {
+ {
+ .start = 0x00204000,
+ .end = 0x00204024,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX1_RTC_INT,
+ .end = MX1_RTC_INT,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MX1_RTC_SAMINT,
+ .end = MX1_RTC_SAMINT,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device imx_rtc_device = {
+ .name = "rtc-imx",
+ .id = 0,
+ .resource = imx_rtc_resources,
+ .num_resources = ARRAY_SIZE(imx_rtc_resources),
+ };
+
+ static struct resource imx_wdt_resources[] = {
+ {
+ .start = 0x00201000,
+ .end = 0x00201008,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX1_WDT_INT,
+ .end = MX1_WDT_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device imx_wdt_device = {
+ .name = "imx-wdt",
+ .id = 0,
+ .resource = imx_wdt_resources,
+ .num_resources = ARRAY_SIZE(imx_wdt_resources),
+ };
+
+ static struct resource imx_usb_resources[] = {
+ {
+ .start = 0x00212000,
+ .end = 0x00212148,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX1_USBD_INT0,
+ .end = MX1_USBD_INT0,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MX1_USBD_INT1,
+ .end = MX1_USBD_INT1,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MX1_USBD_INT2,
+ .end = MX1_USBD_INT2,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MX1_USBD_INT3,
+ .end = MX1_USBD_INT3,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MX1_USBD_INT4,
+ .end = MX1_USBD_INT4,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MX1_USBD_INT5,
+ .end = MX1_USBD_INT5,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MX1_USBD_INT6,
+ .end = MX1_USBD_INT6,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device imx_usb_device = {
+ .name = "imx_udc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(imx_usb_resources),
+ .resource = imx_usb_resources,
+ };
+
+ /* GPIO port description */
+ static struct mxc_gpio_port imx_gpio_ports[] = {
+ {
+ .chip.label = "gpio-0",
+ .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+ .irq = MX1_GPIO_INT_PORTA,
+ .virtual_irq_start = MXC_GPIO_IRQ_START,
+ }, {
+ .chip.label = "gpio-1",
+ .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
+ .irq = MX1_GPIO_INT_PORTB,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+ }, {
+ .chip.label = "gpio-2",
+ .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
+ .irq = MX1_GPIO_INT_PORTC,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+ }, {
+ .chip.label = "gpio-3",
+ .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
+ .irq = MX1_GPIO_INT_PORTD,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+ }
+ };
+
+ int __init imx1_register_gpios(void)
+ {
+ return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+ }
+ #endif
+
+ #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
++
++#ifdef CONFIG_MACH_MX27
++static struct resource mx27_camera_resources[] = {
++ {
++ .start = MX27_CSI_BASE_ADDR,
++ .end = MX27_CSI_BASE_ADDR + 0x1f,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = MX27_EMMA_PRP_BASE_ADDR,
++ .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = MX27_INT_CSI,
++ .end = MX27_INT_CSI,
++ .flags = IORESOURCE_IRQ,
++ },{
++ .start = MX27_INT_EMMAPRP,
++ .end = MX27_INT_EMMAPRP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++struct platform_device mx27_camera_device = {
++ .name = "mx2-camera",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(mx27_camera_resources),
++ .resource = mx27_camera_resources,
++ .dev = {
++ .coherent_dma_mask = 0xffffffff,
++ },
++};
++#endif
++
+ /*
+ * General Purpose Timer
+ * - i.MX21: 3 timers
+ * - i.MX27: 6 timers
+ */
+ #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
+ static struct resource timer ## n ##_resources[] = { \
+ { \
+ .start = baseaddr, \
+ .end = baseaddr + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = irq, \
+ .end = irq, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }; \
+ \
+ struct platform_device mxc_gpt ## n = { \
+ .name = "imx_gpt", \
+ .id = n, \
+ .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
+ .resource = timer ## n ## _resources, \
+ }
+
+ /* We use gpt1 as system timer, so do not add a device for this one */
+ DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
+ DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
+
+ #ifdef CONFIG_MACH_MX27
+ DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
+ DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
+ DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
+ #endif
+
+ /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
+ static struct resource mxc_wdt_resources[] = {
+ {
+ .start = MX2x_WDOG_BASE_ADDR,
+ .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ struct platform_device mxc_wdt = {
+ .name = "imx2-wdt",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+ .resource = mxc_wdt_resources,
+ };
+
+ static struct resource mxc_w1_master_resources[] = {
+ {
+ .start = MX2x_OWIRE_BASE_ADDR,
+ .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ struct platform_device mxc_w1_master_device = {
+ .name = "mxc_w1",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
+ .resource = mxc_w1_master_resources,
+ };
+
+ /*
+ * lcdc:
+ * - i.MX1: the basic controller
+ * - i.MX21: to be checked
+ * - i.MX27: like i.MX1, with slightly variations
+ */
+ static struct resource mxc_fb[] = {
+ {
+ .start = MX2x_LCDC_BASE_ADDR,
+ .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_LCDC,
+ .end = MX2x_INT_LCDC,
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+
+ /* mxc lcd driver */
+ struct platform_device mxc_fb_device = {
+ .name = "imx-fb",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_fb),
+ .resource = mxc_fb,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ };
+
+ #ifdef CONFIG_MACH_MX27
+ static struct resource mxc_fec_resources[] = {
+ {
+ .start = MX27_FEC_BASE_ADDR,
+ .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_FEC,
+ .end = MX27_INT_FEC,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device mxc_fec_device = {
+ .name = "fec",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_fec_resources),
+ .resource = mxc_fec_resources,
+ };
+ #endif
+
+ static struct resource mxc_pwm_resources[] = {
+ {
+ .start = MX2x_PWM_BASE_ADDR,
+ .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX2x_INT_PWM,
+ .end = MX2x_INT_PWM,
+ .flags = IORESOURCE_IRQ,
+ }
+ };
+
+ struct platform_device mxc_pwm_device = {
+ .name = "mxc_pwm",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mxc_pwm_resources),
+ .resource = mxc_pwm_resources,
+ };
+
+ #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
+ static struct resource mxc_sdhc_resources ## n[] = { \
+ { \
+ .start = baseaddr, \
+ .end = baseaddr + SZ_4K - 1, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = irq, \
+ .end = irq, \
+ .flags = IORESOURCE_IRQ, \
+ }, { \
+ .start = dmareq, \
+ .end = dmareq, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ }; \
+ \
+ static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
+ \
+ struct platform_device mxc_sdhc_device ## n = { \
+ .name = "mxc-mmc", \
+ .id = n, \
+ .dev = { \
+ .dma_mask = &mxc_sdhc ## n ## _dmamask, \
+ .coherent_dma_mask = DMA_BIT_MASK(32), \
+ }, \
+ .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
+ .resource = mxc_sdhc_resources ## n, \
+ }
+
+ DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
+ DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
+
+ #ifdef CONFIG_MACH_MX27
+ static struct resource otg_resources[] = {
+ {
+ .start = MX27_USBOTG_BASE_ADDR,
+ .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_USB3,
+ .end = MX27_INT_USB3,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ static u64 otg_dmamask = DMA_BIT_MASK(32);
+
+ /* OTG gadget device */
+ struct platform_device mxc_otg_udc_device = {
+ .name = "fsl-usb2-udc",
+ .id = -1,
+ .dev = {
+ .dma_mask = &otg_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = otg_resources,
+ .num_resources = ARRAY_SIZE(otg_resources),
+ };
+
+ /* OTG host */
+ struct platform_device mxc_otg_host = {
+ .name = "mxc-ehci",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .dma_mask = &otg_dmamask,
+ },
+ .resource = otg_resources,
+ .num_resources = ARRAY_SIZE(otg_resources),
+ };
+
+ /* USB host 1 */
+
+ static u64 usbh1_dmamask = DMA_BIT_MASK(32);
+
+ static struct resource mxc_usbh1_resources[] = {
+ {
+ .start = MX27_USBOTG_BASE_ADDR + 0x200,
+ .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_USB1,
+ .end = MX27_INT_USB1,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device mxc_usbh1 = {
+ .name = "mxc-ehci",
+ .id = 1,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .dma_mask = &usbh1_dmamask,
+ },
+ .resource = mxc_usbh1_resources,
+ .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+ };
+
+ /* USB host 2 */
+ static u64 usbh2_dmamask = DMA_BIT_MASK(32);
+
+ static struct resource mxc_usbh2_resources[] = {
+ {
+ .start = MX27_USBOTG_BASE_ADDR + 0x400,
+ .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX27_INT_USB2,
+ .end = MX27_INT_USB2,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device mxc_usbh2 = {
+ .name = "mxc-ehci",
+ .id = 2,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .dma_mask = &usbh2_dmamask,
+ },
+ .resource = mxc_usbh2_resources,
+ .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+ };
+ #endif
+
+ #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
+ { \
+ .name = _name, \
+ .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
+ .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
+ .flags = IORESOURCE_DMA, \
+ }
+
+ #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
+ static struct resource imx_ssi_resources ## n[] = { \
+ { \
+ .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
+ .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
+ .flags = IORESOURCE_MEM, \
+ }, { \
+ .start = MX2x_INT_SSI1, \
+ .end = MX2x_INT_SSI1, \
+ .flags = IORESOURCE_IRQ, \
+ }, \
+ DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
+ DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
+ DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
+ DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
+ }; \
+ \
+ struct platform_device imx_ssi_device ## n = { \
+ .name = "imx-ssi", \
+ .id = n, \
+ .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
+ .resource = imx_ssi_resources ## n, \
+ }
+
+ DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
+ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
+
+ /* GPIO port description */
+ #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
+ { \
+ .chip.label = "gpio-" #n, \
+ .irq = _irq, \
+ .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
+ n * 0x100), \
+ .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
+ }
+
+ #define DEFINE_MXC_GPIO_PORT(SOC, n) \
+ { \
+ .chip.label = "gpio-" #n, \
+ .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
+ n * 0x100), \
+ .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
+ }
+
+ #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
+ static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
+ DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
+ DEFINE_MXC_GPIO_PORT(SOC, 1), \
+ DEFINE_MXC_GPIO_PORT(SOC, 2), \
+ DEFINE_MXC_GPIO_PORT(SOC, 3), \
+ DEFINE_MXC_GPIO_PORT(SOC, 4), \
+ DEFINE_MXC_GPIO_PORT(SOC, 5), \
+ }
+
+ #ifdef CONFIG_MACH_MX21
+ DEFINE_MXC_GPIO_PORTS(MX21, imx21);
+
+ int __init imx21_register_gpios(void)
+ {
+ return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
+ }
+ #endif
+
+ #ifdef CONFIG_MACH_MX27
+ DEFINE_MXC_GPIO_PORTS(MX27, imx27);
+
+ int __init imx27_register_gpios(void)
+ {
+ return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
+ }
+ #endif
+
+ #ifdef CONFIG_MACH_MX21
+ static struct resource mx21_usbhc_resources[] = {
+ {
+ .start = MX21_USBOTG_BASE_ADDR,
+ .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MX21_INT_USBHOST,
+ .end = MX21_INT_USBHOST,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ struct platform_device mx21_usbhc_device = {
+ .name = "imx21-hcd",
+ .id = 0,
+ .dev = {
+ .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
+ .resource = mx21_usbhc_resources,
+ };
+ #endif
++
++static struct resource imx_kpp_resources[] = {
++ {
++ .start = MX2x_KPP_BASE_ADDR,
++ .end = MX2x_KPP_BASE_ADDR + 0xf,
++ .flags = IORESOURCE_MEM
++ }, {
++ .start = MX2x_INT_KPP,
++ .end = MX2x_INT_KPP,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++struct platform_device imx_kpp_device = {
++ .name = "imx-keypad",
++ .id = -1,
++ .num_resources = ARRAY_SIZE(imx_kpp_resources),
++ .resource = imx_kpp_resources,
++};
++
+ #endif
--- /dev/null
+ #ifdef CONFIG_ARCH_MX1
+ extern struct platform_device imx1_camera_device;
+ extern struct platform_device imx_rtc_device;
+ extern struct platform_device imx_wdt_device;
+ extern struct platform_device imx_usb_device;
+ #endif
+
+ #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
+ extern struct platform_device mxc_gpt1;
+ extern struct platform_device mxc_gpt2;
+ #ifdef CONFIG_MACH_MX27
+ extern struct platform_device mxc_gpt3;
+ extern struct platform_device mxc_gpt4;
+ extern struct platform_device mxc_gpt5;
+ #endif
+ extern struct platform_device mxc_wdt;
+ extern struct platform_device mxc_w1_master_device;
+ extern struct platform_device mxc_fb_device;
+ extern struct platform_device mxc_fec_device;
+ extern struct platform_device mxc_pwm_device;
+ extern struct platform_device mxc_sdhc_device0;
+ extern struct platform_device mxc_sdhc_device1;
+ extern struct platform_device mxc_otg_udc_device;
++extern struct platform_device mx27_camera_device;
+ extern struct platform_device mxc_otg_host;
+ extern struct platform_device mxc_usbh1;
+ extern struct platform_device mxc_usbh2;
+ extern struct platform_device mx21_usbhc_device;
+ extern struct platform_device imx_ssi_device0;
+ extern struct platform_device imx_ssi_device1;
++extern struct platform_device imx_kpp_device;
+ #endif
--- /dev/null
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ /*
- PD28_PF_CSPI1_SS0,
++ * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+ #include <linux/gpio.h>
+ #include <linux/irq.h>
+ #include <linux/platform_device.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/ads7846.h>
++#include <linux/backlight.h>
++#include <video/platform_lcd.h>
++#include <linux/input/matrix_keypad.h>
+
+ #include <asm/mach/arch.h>
+
+ #include <mach/common.h>
+ #include <mach/iomux-mx27.h>
+ #include <mach/imxfb.h>
+ #include <mach/hardware.h>
+ #include <mach/mmc.h>
++#include <mach/spi.h>
++#include <mach/ssi.h>
++#include <mach/audmux.h>
+
+ #include "devices-imx27.h"
+ #include "devices.h"
+
+ static int eukrea_mbimx27_pins[] = {
+ /* UART2 */
+ PE3_PF_UART2_CTS,
+ PE4_PF_UART2_RTS,
+ PE6_PF_UART2_TXD,
+ PE7_PF_UART2_RXD,
+ /* UART3 */
+ PE8_PF_UART3_TXD,
+ PE9_PF_UART3_RXD,
+ PE10_PF_UART3_CTS,
+ PE11_PF_UART3_RTS,
+ /* UART4 */
++#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
+ PB26_AF_UART4_RTS,
+ PB28_AF_UART4_TXD,
+ PB29_AF_UART4_CTS,
+ PB31_AF_UART4_RXD,
++#endif
+ /* SDHC1*/
+ PE18_PF_SD1_D0,
+ PE19_PF_SD1_D1,
+ PE20_PF_SD1_D2,
+ PE21_PF_SD1_D3,
+ PE22_PF_SD1_CMD,
+ PE23_PF_SD1_CLK,
+ /* display */
+ PA5_PF_LSCLK,
+ PA6_PF_LD0,
+ PA7_PF_LD1,
+ PA8_PF_LD2,
+ PA9_PF_LD3,
+ PA10_PF_LD4,
+ PA11_PF_LD5,
+ PA12_PF_LD6,
+ PA13_PF_LD7,
+ PA14_PF_LD8,
+ PA15_PF_LD9,
+ PA16_PF_LD10,
+ PA17_PF_LD11,
+ PA18_PF_LD12,
+ PA19_PF_LD13,
+ PA20_PF_LD14,
+ PA21_PF_LD15,
+ PA22_PF_LD16,
+ PA23_PF_LD17,
+ PA28_PF_HSYNC,
+ PA29_PF_VSYNC,
+ PA30_PF_CONTRAST,
+ PA31_PF_OE_ACD,
+ /* SPI1 */
- {
- .name = "backlight",
- .default_trigger = "backlight",
- .active_low = 0,
- .gpio = GPIO_PORTE | 5,
- },
+ PD29_PF_CSPI1_SCLK,
+ PD30_PF_CSPI1_MISO,
+ PD31_PF_CSPI1_MOSI,
++ /* SSI4 */
++#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
++ || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
++ PC16_PF_SSI4_FS,
++ PC17_PF_SSI4_RXD | GPIO_PUEN,
++ PC18_PF_SSI4_TXD | GPIO_PUEN,
++ PC19_PF_SSI4_CLK,
++#endif
++};
++
++static const uint32_t eukrea_mbimx27_keymap[] = {
++ KEY(0, 0, KEY_UP),
++ KEY(0, 1, KEY_DOWN),
++ KEY(1, 0, KEY_RIGHT),
++ KEY(1, 1, KEY_LEFT),
++};
++
++static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
++ .keymap = eukrea_mbimx27_keymap,
++ .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
+ };
+
+ static struct gpio_led gpio_leds[] = {
+ {
+ .name = "led1",
+ .default_trigger = "heartbeat",
+ .active_low = 1,
+ .gpio = GPIO_PORTF | 16,
+ },
+ {
+ .name = "led2",
+ .default_trigger = "none",
+ .active_low = 1,
+ .gpio = GPIO_PORTF | 19,
+ },
- .name = "CMO-QGVA",
+ };
+
+ static struct gpio_led_platform_data gpio_led_info = {
+ .leds = gpio_leds,
+ .num_leds = ARRAY_SIZE(gpio_leds),
+ };
+
+ static struct platform_device leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &gpio_led_info,
+ },
+ };
+
+ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
+ {
+ .mode = {
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
++ .name = "CMO-QVGA",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = 156000,
+ .hsync_len = 30,
+ .left_margin = 38,
+ .right_margin = 20,
+ .vsync_len = 3,
+ .upper_margin = 15,
+ .lower_margin = 4,
+ },
+ .pcr = 0xFAD08B80,
+ .bpp = 16,
++ }, {
++ .mode = {
++ .name = "DVI-VGA",
++ .refresh = 60,
++ .xres = 640,
++ .yres = 480,
++ .pixclock = 32000,
++ .hsync_len = 1,
++ .left_margin = 35,
++ .right_margin = 0,
++ .vsync_len = 1,
++ .upper_margin = 7,
++ .lower_margin = 0,
++ },
++ .pcr = 0xFA208B80,
++ .bpp = 16,
++ }, {
++ .mode = {
++ .name = "DVI-SVGA",
++ .refresh = 60,
++ .xres = 800,
++ .yres = 600,
++ .pixclock = 25000,
++ .hsync_len = 1,
++ .left_margin = 35,
++ .right_margin = 0,
++ .vsync_len = 1,
++ .upper_margin = 7,
++ .lower_margin = 0,
++ },
++ .pcr = 0xFA208B80,
++ .bpp = 16,
+ },
+ };
+
+ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
+ .mode = eukrea_mbimx27_modes,
+ .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
+
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00040060,
+ };
+
++static void eukrea_mbimx27_bl_set_intensity(int intensity)
++{
++ if (intensity)
++ gpio_direction_output(GPIO_PORTE | 5, 1);
++ else
++ gpio_direction_output(GPIO_PORTE | 5, 0);
++}
++
++static struct generic_bl_info eukrea_mbimx27_bl_info = {
++ .name = "eukrea_mbimx27-bl",
++ .max_intensity = 0xff,
++ .default_intensity = 0xff,
++ .set_bl_intensity = eukrea_mbimx27_bl_set_intensity,
++};
++
++static struct platform_device eukrea_mbimx27_bl_dev = {
++ .name = "generic-bl",
++ .id = 1,
++ .dev = {
++ .platform_data = &eukrea_mbimx27_bl_info,
++ },
++};
++
++static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
++ unsigned int power)
++{
++ if (power)
++ gpio_direction_output(GPIO_PORTA | 25, 1);
++ else
++ gpio_direction_output(GPIO_PORTA | 25, 0);
++}
++
++static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
++ .set_power = eukrea_mbimx27_lcd_power_set,
++};
++
++static struct platform_device eukrea_mbimx27_lcd_powerdev = {
++ .name = "platform-lcd",
++ .dev.platform_data = &eukrea_mbimx27_lcd_power_data,
++};
++
+ static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+ };
+
-
++#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
+ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+
+ #define ADS7846_PENDOWN (GPIO_PORTD | 25)
+
+ static void ads7846_dev_init(void)
+ {
+ if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
+ printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+ return;
+ }
- mxc_register_device(&mxc_sdhc_device0, NULL);
+ gpio_direction_input(ADS7846_PENDOWN);
+ }
+
+ static int ads7846_get_pendown_state(void)
+ {
+ return !gpio_get_value(ADS7846_PENDOWN);
+ }
+
+ static struct ads7846_platform_data ads7846_config __initdata = {
+ .get_pendown_state = ads7846_get_pendown_state,
+ .keep_vref_on = 1,
+ };
++#endif
+
++#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
+ [0] = {
+ .modalias = "ads7846",
+ .bus_num = 0,
+ .chip_select = 0,
+ .max_speed_hz = 1500000,
+ .irq = IRQ_GPIOD(25),
+ .platform_data = &ads7846_config,
+ .mode = SPI_MODE_2,
+ },
+ };
+
++static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
++ {
++ I2C_BOARD_INFO("tlv320aic23", 0x1a),
++ },
++};
++
+ static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
+
+ static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
+ .chipselect = eukrea_mbimx27_spi_cs,
+ .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
+ };
+ #endif
+
+ static struct platform_device *platform_devices[] __initdata = {
+ &leds_gpio,
+ };
+
++static struct imxmmc_platform_data sdhc_pdata = {
++ .dat3_card_detect = 1,
++};
++
++struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
++ .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
++};
++
+ /*
+ * system init for baseboard usage. Will be called by cpuimx27 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+ void __init eukrea_mbimx27_baseboard_init(void)
+ {
+ mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
+ ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
+
++#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
++ || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
++ /* SSI unit master I2S codec connected to SSI_PINS_4*/
++ mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
++ MXC_AUDMUX_V1_PCR_SYN |
++ MXC_AUDMUX_V1_PCR_TFSDIR |
++ MXC_AUDMUX_V1_PCR_TCLKDIR |
++ MXC_AUDMUX_V1_PCR_RFSDIR |
++ MXC_AUDMUX_V1_PCR_RCLKDIR |
++ MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
++ MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
++ MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
++ );
++ mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
++ MXC_AUDMUX_V1_PCR_SYN |
++ MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
++ );
++#endif
++
+ imx27_add_imx_uart1(&uart_pdata);
+ imx27_add_imx_uart2(&uart_pdata);
++#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
++ imx27_add_imx_uart3(&uart_pdata);
++#endif
+
+ mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
++ mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
+
- /* SPI and ADS7846 Touchscreen controler init */
- mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
++ i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
++ ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
++
++ mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
++
++#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
+ || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
- ads7846_dev_init();
++ /* ADS7846 Touchscreen controller init */
+ mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
++ ads7846_dev_init();
++#endif
++
++#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
++ /* SPI_CS0 init */
++ mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+ imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
+ spi_register_board_info(eukrea_mbimx27_spi_board_info,
+ ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
+ #endif
+
+ /* Leds configuration */
+ mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
+ mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
+ /* Backlight */
+ mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
++ gpio_request(GPIO_PORTE | 5, "backlight");
++ platform_device_register(&eukrea_mbimx27_bl_dev);
++ /* LCD Reset */
++ mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
++ gpio_request(GPIO_PORTA | 25, "lcd_enable");
++ platform_device_register(&eukrea_mbimx27_lcd_powerdev);
++
++ mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ }
--- /dev/null
- GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
- GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
- GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
- GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+ /*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm038.c which is :
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+ #include <linux/i2c.h>
+ #include <linux/io.h>
+ #include <linux/mtd/plat-ram.h>
+ #include <linux/mtd/physmap.h>
+ #include <linux/platform_device.h>
+ #include <linux/serial_8250.h>
++#include <linux/usb/otg.h>
++#include <linux/usb/ulpi.h>
++#include <linux/fsl_devices.h>
+
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/time.h>
+ #include <asm/mach/map.h>
+
+ #include <mach/board-eukrea_cpuimx27.h>
+ #include <mach/common.h>
+ #include <mach/hardware.h>
+ #include <mach/iomux-mx27.h>
+ #include <mach/mxc_nand.h>
++#include <mach/mxc_ehci.h>
++#include <mach/ulpi.h>
+
+ #include "devices-imx27.h"
+ #include "devices.h"
+
+ static int eukrea_cpuimx27_pins[] = {
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* UART4 */
++#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
+ PB26_AF_UART4_RTS,
+ PB28_AF_UART4_TXD,
+ PB29_AF_UART4_CTS,
+ PB31_AF_UART4_RXD,
++#endif
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ /* I2C1 */
+ PD17_PF_I2C_DATA,
+ PD18_PF_I2C_CLK,
+ /* SDHC2 */
++#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
++#endif
+ #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ /* Quad UART's IRQ */
++ GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
++ GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
++ GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
++ GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
+ #endif
++ /* OTG */
++ PC7_PF_USBOTG_DATA5,
++ PC8_PF_USBOTG_DATA6,
++ PC9_PF_USBOTG_DATA0,
++ PC10_PF_USBOTG_DATA2,
++ PC11_PF_USBOTG_DATA1,
++ PC12_PF_USBOTG_DATA4,
++ PC13_PF_USBOTG_DATA3,
++ PE0_PF_USBOTG_NXT,
++ PE1_PF_USBOTG_STP,
++ PE2_PF_USBOTG_DIR,
++ PE24_PF_USBOTG_CLK,
++ PE25_PF_USBOTG_DATA7,
++ /* USBH2 */
++ PA0_PF_USBH2_CLK,
++ PA1_PF_USBH2_DIR,
++ PA2_PF_USBH2_DATA7,
++ PA3_PF_USBH2_NXT,
++ PA4_PF_USBH2_STP,
++ PD19_AF_USBH2_DATA4,
++ PD20_AF_USBH2_DATA3,
++ PD21_AF_USBH2_DATA6,
++ PD22_AF_USBH2_DATA0,
++ PD23_AF_USBH2_DATA2,
++ PD24_AF_USBH2_DATA1,
++ PD26_AF_USBH2_DATA5,
+ };
+
+ static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
+ .width = 2,
+ };
+
+ static struct resource eukrea_cpuimx27_flash_resource = {
+ .start = 0xc0000000,
+ .end = 0xc3ffffff,
+ .flags = IORESOURCE_MEM,
+ };
+
+ static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &eukrea_cpuimx27_flash_data,
+ },
+ .num_resources = 1,
+ .resource = &eukrea_cpuimx27_flash_resource,
+ };
+
+ static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+ };
+
+ static const struct mxc_nand_platform_data
+ cpuimx27_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
+
+ static struct platform_device *platform_devices[] __initdata = {
+ &eukrea_cpuimx27_nor_mtd_device,
+ &mxc_fec_device,
++ &mxc_wdt,
++ &mxc_w1_master_device,
+ };
+
+ static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
+ .bitrate = 100000,
+ };
+
+ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ },
+ };
+
+ #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ static struct plat_serial8250_port serial_platform_data[] = {
+ {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
+ .irq = IRQ_GPIOB(23),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
+ .irq = IRQ_GPIOB(22),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
+ .irq = IRQ_GPIOB(27),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
+ .irq = IRQ_GPIOB(30),
+ .uartclk = 14745600,
+ .regshift = 1,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+ }, {
+ }
+ };
+
+ static struct platform_device serial_device = {
+ .name = "serial8250",
+ .id = 0,
+ .dev = {
+ .platform_data = serial_platform_data,
+ },
+ };
+ #endif
+
++#if defined(CONFIG_USB_ULPI)
++static struct mxc_usbh_platform_data otg_pdata = {
++ .portsc = MXC_EHCI_MODE_ULPI,
++ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
++};
++
++static struct mxc_usbh_platform_data usbh2_pdata = {
++ .portsc = MXC_EHCI_MODE_ULPI,
++ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
++};
++#endif
++
++static struct fsl_usb2_platform_data otg_device_pdata = {
++ .operating_mode = FSL_USB2_DR_DEVICE,
++ .phy_mode = FSL_USB2_PHY_ULPI,
++};
++
++static int otg_mode_host;
++
++static int __init eukrea_cpuimx27_otg_mode(char *options)
++{
++ if (!strcmp(options, "host"))
++ otg_mode_host = 1;
++ else if (!strcmp(options, "device"))
++ otg_mode_host = 0;
++ else
++ pr_info("otg_mode neither \"host\" nor \"device\". "
++ "Defaulting to device\n");
++ return 0;
++}
++__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
++
+ static void __init eukrea_cpuimx27_init(void)
+ {
+ mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
+ ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
+
+ imx27_add_imx_uart0(&uart_pdata);
+
+ imx27_add_mxc_nand(&cpuimx27_nand_board_info);
+
+ i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
+ ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
+
+ imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+ #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
+ /* SDHC2 can be used for Wifi */
+ mxc_register_device(&mxc_sdhc_device1, NULL);
++#endif
++#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
+ /* in which case UART4 is also used for Bluetooth */
+ imx27_add_imx_uart3(&uart_pdata);
+ #endif
+
+ #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+ platform_device_register(&serial_device);
+ #endif
+
++#if defined(CONFIG_USB_ULPI)
++ if (otg_mode_host) {
++ otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
++ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
++
++ mxc_register_device(&mxc_otg_host, &otg_pdata);
++ }
++
++ usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
++ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
++
++ mxc_register_device(&mxc_usbh2, &usbh2_pdata);
++#endif
++ if (!otg_mode_host)
++ mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
++
+ #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
+ eukrea_mbimx27_baseboard_init();
+ #endif
+ }
+
+ static void __init eukrea_cpuimx27_timer_init(void)
+ {
+ mx27_clocks_init(26000000);
+ }
+
+ static struct sys_timer eukrea_cpuimx27_timer = {
+ .init = eukrea_cpuimx27_timer_init,
+ };
+
+ MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = eukrea_cpuimx27_init,
+ .timer = &eukrea_cpuimx27_timer,
+ MACHINE_END
--- /dev/null
-static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+ /*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c/at24.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/eeprom.h>
+ #include <linux/irq.h>
+ #include <linux/delay.h>
+ #include <linux/gpio.h>
+ #include <linux/usb/otg.h>
+ #include <linux/usb/ulpi.h>
+ #include <linux/fsl_devices.h>
+
+ #include <asm/mach/arch.h>
+ #include <asm/mach-types.h>
+ #include <mach/common.h>
+ #include <mach/hardware.h>
+ #include <mach/iomux-mx27.h>
+ #include <asm/mach/time.h>
+ #include <mach/audmux.h>
+ #include <mach/ssi.h>
+ #include <mach/mxc_nand.h>
+ #include <mach/irqs.h>
+ #include <mach/mmc.h>
+ #include <mach/mxc_ehci.h>
+ #include <mach/ulpi.h>
++#include <mach/imxfb.h>
+
+ #include "devices-imx27.h"
+ #include "devices.h"
+
+ #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
+ #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
++#define SPI1_SS0 (GPIO_PORTD + 28)
++#define SPI1_SS1 (GPIO_PORTD + 27)
++#define SD2_CD (GPIO_PORTC + 29)
+
+ static int pca100_pins[] = {
+ /* UART1 */
+ PE12_PF_UART1_TXD,
+ PE13_PF_UART1_RXD,
+ PE14_PF_UART1_CTS,
+ PE15_PF_UART1_RTS,
+ /* SDHC */
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
++ SD2_CD | GPIO_GPIO | GPIO_IN,
+ /* FEC */
+ PD0_AIN_FEC_TXD0,
+ PD1_AIN_FEC_TXD1,
+ PD2_AIN_FEC_TXD2,
+ PD3_AIN_FEC_TXD3,
+ PD4_AOUT_FEC_RX_ER,
+ PD5_AOUT_FEC_RXD1,
+ PD6_AOUT_FEC_RXD2,
+ PD7_AOUT_FEC_RXD3,
+ PD8_AF_FEC_MDIO,
+ PD9_AIN_FEC_MDC,
+ PD10_AOUT_FEC_CRS,
+ PD11_AOUT_FEC_TX_CLK,
+ PD12_AOUT_FEC_RXD0,
+ PD13_AOUT_FEC_RX_DV,
+ PD14_AOUT_FEC_RX_CLK,
+ PD15_AOUT_FEC_COL,
+ PD16_AIN_FEC_TX_ER,
+ PF23_AIN_FEC_TX_EN,
+ /* SSI1 */
+ PC20_PF_SSI1_FS,
+ PC21_PF_SSI1_RXD,
+ PC22_PF_SSI1_TXD,
+ PC23_PF_SSI1_CLK,
+ /* onboard I2C */
+ PC5_PF_I2C2_SDA,
+ PC6_PF_I2C2_SCL,
+ /* external I2C */
+ PD17_PF_I2C_DATA,
+ PD18_PF_I2C_CLK,
+ /* SPI1 */
+ PD25_PF_CSPI1_RDY,
+ PD29_PF_CSPI1_SCLK,
+ PD30_PF_CSPI1_MISO,
+ PD31_PF_CSPI1_MOSI,
+ /* OTG */
+ OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+ PC7_PF_USBOTG_DATA5,
+ PC8_PF_USBOTG_DATA6,
+ PC9_PF_USBOTG_DATA0,
+ PC10_PF_USBOTG_DATA2,
+ PC11_PF_USBOTG_DATA1,
+ PC12_PF_USBOTG_DATA4,
+ PC13_PF_USBOTG_DATA3,
+ PE0_PF_USBOTG_NXT,
+ PE1_PF_USBOTG_STP,
+ PE2_PF_USBOTG_DIR,
+ PE24_PF_USBOTG_CLK,
+ PE25_PF_USBOTG_DATA7,
+ /* USBH2 */
+ USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+ PA0_PF_USBH2_CLK,
+ PA1_PF_USBH2_DIR,
+ PA2_PF_USBH2_DATA7,
+ PA3_PF_USBH2_NXT,
+ PA4_PF_USBH2_STP,
+ PD19_AF_USBH2_DATA4,
+ PD20_AF_USBH2_DATA3,
+ PD21_AF_USBH2_DATA6,
+ PD22_AF_USBH2_DATA0,
+ PD23_AF_USBH2_DATA2,
+ PD24_AF_USBH2_DATA1,
+ PD26_AF_USBH2_DATA5,
++ /* display */
++ PA5_PF_LSCLK,
++ PA6_PF_LD0,
++ PA7_PF_LD1,
++ PA8_PF_LD2,
++ PA9_PF_LD3,
++ PA10_PF_LD4,
++ PA11_PF_LD5,
++ PA12_PF_LD6,
++ PA13_PF_LD7,
++ PA14_PF_LD8,
++ PA15_PF_LD9,
++ PA16_PF_LD10,
++ PA17_PF_LD11,
++ PA18_PF_LD12,
++ PA19_PF_LD13,
++ PA20_PF_LD14,
++ PA21_PF_LD15,
++ PA22_PF_LD16,
++ PA23_PF_LD17,
++ PA26_PF_PS,
++ PA28_PF_HSYNC,
++ PA29_PF_VSYNC,
++ PA31_PF_OE_ACD,
++ /* free GPIO */
++ GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
++ GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
++ GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
+ };
+
+ static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+ };
+
+ static const struct mxc_nand_platform_data
+ pca100_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ };
+
+ static struct platform_device *platform_devices[] __initdata = {
+ &mxc_w1_master_device,
+ &mxc_fec_device,
+ &mxc_wdt,
+ };
+
+ static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
+ .bitrate = 100000,
+ };
+
+ static struct at24_platform_data board_eeprom = {
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = AT24_FLAG_ADDR16,
+ };
+
+ static struct i2c_board_info pca100_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+ .platform_data = &board_eeprom,
+ }, {
+ I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+ .type = "pcf8563"
+ }, {
+ I2C_BOARD_INFO("lm75", 0x4a),
+ .type = "lm75"
+ }
+ };
+
+ #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+ static struct spi_eeprom at25320 = {
+ .name = "at25320an",
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = EE_ADDR2,
+ };
+
+ static struct spi_board_info pca100_spi_board_info[] __initdata = {
+ {
+ .modalias = "at25",
+ .max_speed_hz = 30000,
+ .bus_num = 0,
+ .chip_select = 1,
+ .platform_data = &at25320,
+ },
+ };
+
- mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
++static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
+
+ static const struct spi_imx_master pca100_spi0_data __initconst = {
+ .chipselect = pca100_spi_cs,
+ .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
+ };
+ #endif
+
+ static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
+ {
+ mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT);
+ gpio_set_value(GPIO_PORTC + 20, 1);
+ udelay(2);
+ gpio_set_value(GPIO_PORTC + 20, 0);
+ mxc_gpio_mode(PC20_PF_SSI1_FS);
+ msleep(2);
+ }
+
+ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
+ {
+ mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */
+ gpio_set_value(GPIO_PORTC + 20, 0);
+ mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */
+ gpio_set_value(GPIO_PORTC + 22, 0);
+ mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */
+ gpio_set_value(GPIO_PORTC + 28, 0);
+ udelay(10);
+ gpio_set_value(GPIO_PORTC + 28, 1);
+ mxc_gpio_mode(PC20_PF_SSI1_FS);
+ mxc_gpio_mode(PC22_PF_SSI1_TXD);
+ msleep(2);
+ }
+
+ static struct imx_ssi_platform_data pca100_ssi_pdata = {
+ .ac97_reset = pca100_ac97_cold_reset,
+ .ac97_warm_reset = pca100_ac97_warm_reset,
+ .flags = IMX_SSI_USE_AC97,
+ };
+
+ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+ {
+ int ret;
+
+ ret = request_irq(IRQ_GPIOC(29), detect_irq,
+ IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+ "imx-mmc-detect", data);
+ if (ret)
+ printk(KERN_ERR
+ "pca100: Failed to reuest irq for sd/mmc detection\n");
+
+ return ret;
+ }
+
+ static void pca100_sdhc2_exit(struct device *dev, void *data)
+ {
+ free_irq(IRQ_GPIOC(29), data);
+ }
+
+ static struct imxmmc_platform_data sdhc_pdata = {
+ .init = pca100_sdhc2_init,
+ .exit = pca100_sdhc2_exit,
+ };
+
++#if defined(CONFIG_USB_ULPI)
+ static int otg_phy_init(struct platform_device *pdev)
+ {
+ gpio_set_value(OTG_PHY_CS_GPIO, 0);
+ return 0;
+ }
+
+ static struct mxc_usbh_platform_data otg_pdata = {
+ .init = otg_phy_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+
+ static int usbh2_phy_init(struct platform_device *pdev)
+ {
+ gpio_set_value(USBH2_PHY_CS_GPIO, 0);
+ return 0;
+ }
+
+ static struct mxc_usbh_platform_data usbh2_pdata = {
+ .init = usbh2_phy_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
++#endif
+
+ static struct fsl_usb2_platform_data otg_device_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+ };
+
+ static int otg_mode_host;
+
+ static int __init pca100_otg_mode(char *options)
+ {
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+ }
+ __setup("otg_mode=", pca100_otg_mode);
+
++/* framebuffer info */
++static struct imx_fb_videomode pca100_fb_modes[] = {
++ {
++ .mode = {
++ .name = "EMERGING-ETV570G0DHU",
++ .refresh = 60,
++ .xres = 640,
++ .yres = 480,
++ .pixclock = 39722, /* in ps (25.175 MHz) */
++ .hsync_len = 30,
++ .left_margin = 114,
++ .right_margin = 16,
++ .vsync_len = 3,
++ .upper_margin = 32,
++ .lower_margin = 0,
++ },
++ /*
++ * TFT
++ * Pixel pol active high
++ * HSYNC active low
++ * VSYNC active low
++ * use HSYNC for ACD count
++ * line clock disable while idle
++ * always enable line clock even if no data
++ */
++ .pcr = 0xf0c08080,
++ .bpp = 16,
++ },
++};
++
++static struct imx_fb_platform_data pca100_fb_data = {
++ .mode = pca100_fb_modes,
++ .num_modes = ARRAY_SIZE(pca100_fb_modes),
++
++ .pwmr = 0x00A903FF,
++ .lscr1 = 0x00120300,
++ .dmacr = 0x00020010,
++};
++
+ static void __init pca100_init(void)
+ {
+ int ret;
+
+ /* SSI unit */
+ mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+ MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+ MXC_AUDMUX_V1_PCR_TFCSEL(3) |
+ MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
+ MXC_AUDMUX_V1_PCR_RXDSEL(3));
+ mxc_audmux_v1_configure_port(3,
+ MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
+ MXC_AUDMUX_V1_PCR_TFCSEL(0) |
+ MXC_AUDMUX_V1_PCR_TFSDIR |
+ MXC_AUDMUX_V1_PCR_RXDSEL(0));
+
+ ret = mxc_gpio_setup_multiple_pins(pca100_pins,
+ ARRAY_SIZE(pca100_pins), "PCA100");
+ if (ret)
+ printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
+
+ mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
+
+ imx27_add_imx_uart0(&uart_pdata);
+
- mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
- mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
-
- /* GPIO0_IRQ */
- mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
- /* GPIO1_IRQ */
- mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
- /* GPIO2_IRQ */
- mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
-
+ mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+
+ imx27_add_mxc_nand(&pca100_nand_board_info);
+
+ /* only the i2c master 1 is used on this CPU card */
+ i2c_register_board_info(1, pca100_i2c_devices,
+ ARRAY_SIZE(pca100_i2c_devices));
+
+ imx27_add_i2c_imx1(&pca100_i2c1_data);
+
+ #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
++ mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
++ mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
+ spi_register_board_info(pca100_spi_board_info,
+ ARRAY_SIZE(pca100_spi_board_info));
+ imx27_add_spi_imx0(&pca100_spi_0_data);
+ #endif
+
+ gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
+ gpio_direction_output(OTG_PHY_CS_GPIO, 1);
+ gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
+ gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
+
+ #if defined(CONFIG_USB_ULPI)
+ if (otg_mode_host) {
+ otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+ mxc_register_device(&mxc_otg_host, &otg_pdata);
+ }
+
+ usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+ mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+ #endif
+ if (!otg_mode_host) {
+ gpio_set_value(OTG_PHY_CS_GPIO, 0);
+ mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+ }
+
++ mxc_register_device(&mxc_fb_device, &pca100_fb_data);
++
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ }
+
+ static void __init pca100_timer_init(void)
+ {
+ mx27_clocks_init(26000000);
+ }
+
+ static struct sys_timer pca100_timer = {
+ .init = pca100_timer_init,
+ };
+
+ MACHINE_START(PCA100, "phyCARD-i.MX27")
+ .phys_io = MX27_AIPI_BASE_ADDR,
+ .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = mx27_map_io,
+ .init_irq = mx27_init_irq,
+ .init_machine = pca100_init,
+ .timer = &pca100_timer,
+ MACHINE_END
+
--- /dev/null
--- /dev/null
++/*
++ * i.MX27 Power Management Routines
++ *
++ * Based on Freescale's BSP
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License.
++ */
++
++#include <linux/kernel.h>
++#include <linux/suspend.h>
++#include <linux/io.h>
++#include <mach/system.h>
++#include <mach/mx27.h>
++
++static int mx27_suspend_enter(suspend_state_t state)
++{
++ u32 cscr;
++ switch (state) {
++ case PM_SUSPEND_MEM:
++ /* Clear MPEN and SPEN to disable MPLL/SPLL */
++ cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
++ cscr &= 0xFFFFFFFC;
++ __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
++ /* Executes WFI */
++ arch_idle();
++ break;
++
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static struct platform_suspend_ops mx27_suspend_ops = {
++ .enter = mx27_suspend_enter,
++ .valid = suspend_valid_only_mem,
++};
++
++static int __init mx27_pm_init(void)
++{
++ suspend_set_ops(&mx27_suspend_ops);
++ return 0;
++}
++
++device_initcall(mx27_pm_init);
config MACH_MX25_3DS
bool "Support MX25PDK (3DS) Platform"
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_NAND
+config MACH_EUKREA_CPUIMX25
+ bool "Support Eukrea CPUIMX25 Platform"
++ select IMX_HAVE_PLATFORM_IMX_I2C
++ select IMX_HAVE_PLATFORM_IMX_UART
++ select IMX_HAVE_PLATFORM_MXC_NAND
+ select MXC_ULPI if USB_ULPI
+
+choice
+ prompt "Baseboard"
+ depends on MACH_EUKREA_CPUIMX25
+ default MACH_EUKREA_MBIMXSD_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD_BASEBOARD
+ prompt "Eukrea MBIMXSD development board"
+ bool
+ help
+ This adds board specific devices that can be found on Eukrea's
+ MBIMXSD evaluation board.
+
+endchoice
+
endif
obj-y := mm.o devices.o
obj-$(CONFIG_ARCH_MX25) += clock.o
- obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o
+ obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD) += eukrea_mbimxsd-baseboard.o
#include <mach/mx25.h>
#include <mach/irqs.h>
- static struct resource uart0[] = {
- {
- .start = 0x43f90000,
- .end = 0x43f93fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 45,
- .end = 45,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- struct platform_device mxc_uart_device0 = {
- .name = "imx-uart",
- .id = 0,
- .resource = uart0,
- .num_resources = ARRAY_SIZE(uart0),
- };
-
- static struct resource uart1[] = {
- {
- .start = 0x43f94000,
- .end = 0x43f97fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 32,
- .end = 32,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- struct platform_device mxc_uart_device1 = {
- .name = "imx-uart",
- .id = 1,
- .resource = uart1,
- .num_resources = ARRAY_SIZE(uart1),
- };
-
- static struct resource uart2[] = {
- {
- .start = 0x5000c000,
- .end = 0x5000ffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 18,
- .end = 18,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- struct platform_device mxc_uart_device2 = {
- .name = "imx-uart",
- .id = 2,
- .resource = uart2,
- .num_resources = ARRAY_SIZE(uart2),
- };
-
- static struct resource uart3[] = {
- {
- .start = 0x50008000,
- .end = 0x5000bfff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 5,
- .end = 5,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- struct platform_device mxc_uart_device3 = {
- .name = "imx-uart",
- .id = 3,
- .resource = uart3,
- .num_resources = ARRAY_SIZE(uart3),
- };
-
- static struct resource uart4[] = {
- {
- .start = 0x5002c000,
- .end = 0x5002ffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 40,
- .end = 40,
- .flags = IORESOURCE_IRQ,
- },
- };
-
- struct platform_device mxc_uart_device4 = {
- .name = "imx-uart",
- .id = 4,
- .resource = uart4,
- .num_resources = ARRAY_SIZE(uart4),
- };
-#define MX25_OTG_BASE_ADDR 0x53FF4000
--
static u64 otg_dmamask = DMA_BIT_MASK(32);
static struct resource mxc_otg_resources[] = {
--- /dev/null
- static struct imxuart_platform_data uart_pdata = {
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+
+#include <mach/board-eukrea_cpuimx25.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx25.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/mx25.h>
+#include <mach/imx-uart.h>
+#include <mach/imxfb.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
+
++#include "devices-imx25.h"
+#include "devices.h"
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+ /* LCD */
+ MX25_PAD_LD0__LD0,
+ MX25_PAD_LD1__LD1,
+ MX25_PAD_LD2__LD2,
+ MX25_PAD_LD3__LD3,
+ MX25_PAD_LD4__LD4,
+ MX25_PAD_LD5__LD5,
+ MX25_PAD_LD6__LD6,
+ MX25_PAD_LD7__LD7,
+ MX25_PAD_LD8__LD8,
+ MX25_PAD_LD9__LD9,
+ MX25_PAD_LD10__LD10,
+ MX25_PAD_LD11__LD11,
+ MX25_PAD_LD12__LD12,
+ MX25_PAD_LD13__LD13,
+ MX25_PAD_LD14__LD14,
+ MX25_PAD_LD15__LD15,
+ MX25_PAD_GPIO_E__LD16,
+ MX25_PAD_GPIO_F__LD17,
+ MX25_PAD_HSYNC__HSYNC,
+ MX25_PAD_VSYNC__VSYNC,
+ MX25_PAD_LSCLK__LSCLK,
+ MX25_PAD_OE_ACD__OE_ACD,
+ MX25_PAD_CONTRAST__CONTRAST,
+ /* LCD_PWR */
+ MX25_PAD_PWM__GPIO_1_26,
+ /* LED */
+ MX25_PAD_POWER_FAIL__GPIO_3_19,
+ /* SWITCH */
+ MX25_PAD_VSTBY_ACK__GPIO_3_18,
+ /* UART2 */
+ MX25_PAD_UART2_RTS__UART2_RTS,
+ MX25_PAD_UART2_CTS__UART2_CTS,
+ MX25_PAD_UART2_TXD__UART2_TXD,
+ MX25_PAD_UART2_RXD__UART2_RXD,
+ /* SD1 */
+ MX25_PAD_SD1_CMD__SD1_CMD,
+ MX25_PAD_SD1_CLK__SD1_CLK,
+ MX25_PAD_SD1_DATA0__SD1_DATA0,
+ MX25_PAD_SD1_DATA1__SD1_DATA1,
+ MX25_PAD_SD1_DATA2__SD1_DATA2,
+ MX25_PAD_SD1_DATA3__SD1_DATA3,
+ /* SD1 CD */
+ MX25_PAD_DE_B__GPIO_2_20,
+ /* I2S */
+ MX25_PAD_KPP_COL3__AUD5_TXFS,
+ MX25_PAD_KPP_COL2__AUD5_TXC,
+ MX25_PAD_KPP_COL1__AUD5_RXD,
+ MX25_PAD_KPP_COL0__AUD5_TXD,
+};
+
+#define GPIO_LED1 83
+#define GPIO_SWITCH1 82
+#define GPIO_SD1CD 52
+#define GPIO_LCDPWR 26
+
+static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
+ {
+ .mode = {
+ .name = "CMO-QVGA",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 30,
+ .right_margin = 38,
+ .upper_margin = 20,
+ .lower_margin = 3,
+ .hsync_len = 15,
+ .vsync_len = 4,
+ },
+ .bpp = 16,
+ .pcr = 0xCAD08B80,
+ },
+};
+
+static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
+ .mode = eukrea_mximxsd_modes,
+ .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00040060,
+};
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power)
+ gpio_direction_output(GPIO_LCDPWR, 1);
+ else
+ gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+ .set_power = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+ .name = "platform-lcd",
+ .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+ {
+ .name = "led1",
+ .default_trigger = "heartbeat",
+ .active_low = 1,
+ .gpio = GPIO_LED1,
+ },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+ .leds = eukrea_mbimxsd_leds,
+ .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &eukrea_mbimxsd_led_info,
+ },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+ {
+ .gpio = GPIO_SWITCH1,
+ .code = BTN_0,
+ .desc = "BP1",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+ .buttons = eukrea_mbimxsd_gpio_buttons,
+ .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+ .name = "gpio-keys",
+ .id = -1,
+ .num_resources = 0,
+ .dev = {
+ .platform_data = &eukrea_mbimxsd_button_data,
+ }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &eukrea_mbimxsd_leds_gpio,
+ &eukrea_mbimxsd_button_device,
+ &eukrea_mbimxsd_lcd_powerdev,
+};
+
- mxc_register_device(&mxc_uart_device1, &uart_pdata);
++static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("tlv320aic23", 0x1a),
+ },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+ .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx25 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+ if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+ ARRAY_SIZE(eukrea_mbimxsd_pads)))
+ printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+ /* SSI unit master I2S codec connected to SSI_AUD5*/
+ mxc_audmux_v2_configure_port(0,
+ MXC_AUDMUX_V2_PTCR_SYN |
+ MXC_AUDMUX_V2_PTCR_TFSDIR |
+ MXC_AUDMUX_V2_PTCR_TFSEL(4) |
+ MXC_AUDMUX_V2_PTCR_TCLKDIR |
+ MXC_AUDMUX_V2_PTCR_TCSEL(4),
+ MXC_AUDMUX_V2_PDCR_RXDSEL(4)
+ );
+ mxc_audmux_v2_configure_port(4,
+ MXC_AUDMUX_V2_PTCR_SYN,
+ MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+ );
+#endif
+
++ imx25_add_imx_uart1(&uart_pdata);
+ mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
+ mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+ gpio_request(GPIO_LED1, "LED1");
+ gpio_direction_output(GPIO_LED1, 1);
+ gpio_free(GPIO_LED1);
+
+ gpio_request(GPIO_SWITCH1, "SWITCH1");
+ gpio_direction_input(GPIO_SWITCH1);
+ gpio_free(GPIO_SWITCH1);
+
+ gpio_request(GPIO_LCDPWR, "LCDPWR");
+ gpio_direction_output(GPIO_LCDPWR, 1);
+ gpio_free(GPIO_SWITCH1);
+
+ i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+ ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
--- /dev/null
- #include <mach/imx-uart.h>
- #include <mach/i2c.h>
+/*
+ * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
+ * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/fec.h>
+#include <linux/platform_device.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/board-eukrea_cpuimx25.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
- #include <mach/iomux-mx25.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include <mach/imxfb.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
++#include <mach/iomux-mx25.h>
+
++#include "devices-imx25.h"
+#include "devices.h"
- static struct imxuart_platform_data uart_pdata = {
+
- static struct mxc_nand_platform_data eukrea_cpuimx25_nand_board_info = {
++static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct pad_desc eukrea_cpuimx25_pads[] = {
+ /* FEC - RMII */
+ MX25_PAD_FEC_MDC__FEC_MDC,
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+ MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ /* I2C1 */
+ MX25_PAD_I2C1_CLK__I2C1_CLK,
+ MX25_PAD_I2C1_DAT__I2C1_DAT,
+};
+
+static struct fec_platform_data mx25_fec_pdata = {
+ .phy = PHY_INTERFACE_MODE_RMII,
+};
+
- static struct imxi2c_platform_data eukrea_cpuimx25_i2c_1_data = {
++static const struct mxc_nand_platform_data
++eukrea_cpuimx25_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ .flash_bbt = 1,
+};
+
- mxc_register_device(&mxc_uart_device0, &uart_pdata);
- mxc_register_device(&mxc_nand_device, &eukrea_cpuimx25_nand_board_info);
++static const struct imxi2c_platform_data
++eukrea_cpuimx25_i2c0_data __initconst = {
+ .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ },
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+ .portsc = MXC_EHCI_MODE_UTMI,
+ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+ .portsc = MXC_EHCI_MODE_SERIAL,
+ .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+ MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx25_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
+
+static void __init eukrea_cpuimx25_init(void)
+{
+ if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
+ ARRAY_SIZE(eukrea_cpuimx25_pads)))
+ printk(KERN_ERR "error setting cpuimx25 pads !\n");
+
- mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx25_i2c_1_data);
++ imx25_add_imx_uart0(&uart_pdata);
++ imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
+ mxc_register_device(&mx25_rtc_device, NULL);
+ mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+
+ i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
+ ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
++ imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+ if (otg_mode_host) {
+ otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+ mxc_register_device(&mxc_otg, &otg_pdata);
+ }
+ mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+ if (!otg_mode_host)
+ mxc_register_device(&otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+ eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx25_timer_init(void)
+{
+ mx25_clocks_init();
+}
+
+static struct sys_timer eukrea_cpuimx25_timer = {
+ .init = eukrea_cpuimx25_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
+ /* Maintainer: Eukrea Electromatique */
+ .phys_io = MX25_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX25_PHYS_OFFSET + 0x100,
+ .map_io = mx25_map_io,
+ .init_irq = mx25_init_irq,
+ .init_machine = eukrea_cpuimx25_init,
+ .timer = &eukrea_cpuimx25_timer,
+MACHINE_END
--- /dev/null
+ /*
+ * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ */
+
+ /*
+ * This machine is known as:
+ * - i.MX25 3-Stack Development System
+ * - i.MX25 Platform Development Kit (i.MX25 PDK)
+ */
+
+ #include <linux/types.h>
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
+ #include <linux/irq.h>
+ #include <linux/gpio.h>
+ #include <linux/fec.h>
+ #include <linux/platform_device.h>
++#include <linux/input/matrix_keypad.h>
+
+ #include <mach/hardware.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/time.h>
+ #include <asm/memory.h>
+ #include <asm/mach/map.h>
+ #include <mach/common.h>
+ #include <mach/mx25.h>
+ #include <mach/imxfb.h>
+ #include <mach/iomux-mx25.h>
+
+ #include "devices-imx25.h"
+ #include "devices.h"
+
+ static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+ };
+
+ static struct pad_desc mx25pdk_pads[] = {
+ MX25_PAD_FEC_MDC__FEC_MDC,
+ MX25_PAD_FEC_MDIO__FEC_MDIO,
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+ MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
+ MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
+
+ /* LCD */
+ MX25_PAD_LD0__LD0,
+ MX25_PAD_LD1__LD1,
+ MX25_PAD_LD2__LD2,
+ MX25_PAD_LD3__LD3,
+ MX25_PAD_LD4__LD4,
+ MX25_PAD_LD5__LD5,
+ MX25_PAD_LD6__LD6,
+ MX25_PAD_LD7__LD7,
+ MX25_PAD_LD8__LD8,
+ MX25_PAD_LD9__LD9,
+ MX25_PAD_LD10__LD10,
+ MX25_PAD_LD11__LD11,
+ MX25_PAD_LD12__LD12,
+ MX25_PAD_LD13__LD13,
+ MX25_PAD_LD14__LD14,
+ MX25_PAD_LD15__LD15,
+ MX25_PAD_GPIO_E__LD16,
+ MX25_PAD_GPIO_F__LD17,
+ MX25_PAD_HSYNC__HSYNC,
+ MX25_PAD_VSYNC__VSYNC,
+ MX25_PAD_LSCLK__LSCLK,
+ MX25_PAD_OE_ACD__OE_ACD,
+ MX25_PAD_CONTRAST__CONTRAST,
++
++ /* Keypad */
++ MX25_PAD_KPP_ROW0__KPP_ROW0,
++ MX25_PAD_KPP_ROW1__KPP_ROW1,
++ MX25_PAD_KPP_ROW2__KPP_ROW2,
++ MX25_PAD_KPP_ROW3__KPP_ROW3,
++ MX25_PAD_KPP_COL0__KPP_COL0,
++ MX25_PAD_KPP_COL1__KPP_COL1,
++ MX25_PAD_KPP_COL2__KPP_COL2,
++ MX25_PAD_KPP_COL3__KPP_COL3,
+ };
+
+ static struct fec_platform_data mx25_fec_pdata = {
+ .phy = PHY_INTERFACE_MODE_RMII,
+ };
+
+ #define FEC_ENABLE_GPIO 35
+ #define FEC_RESET_B_GPIO 104
+
+ static void __init mx25pdk_fec_reset(void)
+ {
+ gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
+ gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
+
+ gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */
+ gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
+ udelay(2);
+
+ /* turn on PHY power and lift reset */
+ gpio_set_value(FEC_ENABLE_GPIO, 1);
+ gpio_set_value(FEC_RESET_B_GPIO, 1);
+ }
+
+ static const struct mxc_nand_platform_data
+ mx25pdk_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ .flash_bbt = 1,
+ };
+
+ static struct imx_fb_videomode mx25pdk_modes[] = {
+ {
+ .mode = {
+ .name = "CRT-VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 39683,
+ .left_margin = 45,
+ .right_margin = 114,
+ .upper_margin = 33,
+ .lower_margin = 11,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ },
+ .bpp = 16,
+ .pcr = 0xFA208B80,
+ },
+ };
+
+ static struct imx_fb_platform_data mx25pdk_fb_pdata = {
+ .mode = mx25pdk_modes,
+ .num_modes = ARRAY_SIZE(mx25pdk_modes),
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00020010,
+ };
+
++static const uint32_t mx25pdk_keymap[] = {
++ KEY(0, 0, KEY_UP),
++ KEY(0, 1, KEY_DOWN),
++ KEY(0, 2, KEY_VOLUMEDOWN),
++ KEY(0, 3, KEY_HOME),
++ KEY(1, 0, KEY_RIGHT),
++ KEY(1, 1, KEY_LEFT),
++ KEY(1, 2, KEY_ENTER),
++ KEY(1, 3, KEY_VOLUMEUP),
++ KEY(2, 0, KEY_F6),
++ KEY(2, 1, KEY_F8),
++ KEY(2, 2, KEY_F9),
++ KEY(2, 3, KEY_F10),
++ KEY(3, 0, KEY_F1),
++ KEY(3, 1, KEY_F2),
++ KEY(3, 2, KEY_F3),
++ KEY(3, 3, KEY_POWER),
++};
++
++static struct matrix_keymap_data mx25pdk_keymap_data = {
++ .keymap = mx25pdk_keymap,
++ .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
++};
++
+ static void __init mx25pdk_init(void)
+ {
+ mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
+ ARRAY_SIZE(mx25pdk_pads));
+
+ imx25_add_imx_uart0(&uart_pdata);
+ mxc_register_device(&mxc_usbh2, NULL);
+ imx25_add_mxc_nand(&mx25pdk_nand_board_info);
+ mxc_register_device(&mx25_rtc_device, NULL);
+ mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
++ mxc_register_device(&mxc_wdt, NULL);
+
+ mx25pdk_fec_reset();
+ mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
++ mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
+ }
+
+ static void __init mx25pdk_timer_init(void)
+ {
+ mx25_clocks_init();
+ }
+
+ static struct sys_timer mx25pdk_timer = {
+ .init = mx25pdk_timer_init,
+ };
+
+ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
+ /* Maintainer: Freescale Semiconductor, Inc. */
+ .phys_io = MX25_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX25_PHYS_OFFSET + 0x100,
+ .map_io = mx25_map_io,
+ .init_irq = mx25_init_irq,
+ .init_machine = mx25pdk_init,
+ .timer = &mx25pdk_timer,
+ MACHINE_END
+
Include support for KZM-ARM11-01. This includes specific
configurations for the board and its peripherals.
+config MACH_EUKREA_CPUIMX35
+ bool "Support Eukrea CPUIMX35 Platform"
+ select ARCH_MX35
++ select IMX_HAVE_PLATFORM_IMX_UART
++ select IMX_HAVE_PLATFORM_IMX_I2C
++ select IMX_HAVE_PLATFORM_MXC_NAND
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for Eukrea CPUIMX35 platform. This includes
+ specific configurations for the board and its peripherals.
+
+choice
+ prompt "Baseboard"
+ depends on MACH_EUKREA_CPUIMX35
+ default MACH_EUKREA_MBIMXSD_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD_BASEBOARD
+ prompt "Eukrea MBIMXSD development board"
+ bool
+ help
+ This adds board specific devices that can be found on Eukrea's
+ MBIMXSD evaluation board.
+
+endchoice
+
endif
obj-$(CONFIG_MACH_QONG) += mach-qong.o
obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
- obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o
+ obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD) += eukrea_mbimxsd-baseboard.o
--- /dev/null
- static struct imxuart_platform_data uart_pdata = {
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/board-eukrea_cpuimx35.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx35.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/audmux.h>
+#include <mach/ssi.h>
+
++#include "devices-imx35.h"
+#include "devices.h"
+
+static const struct fb_videomode fb_modedb[] = {
+ {
+ .name = "CMO_QVGA",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68,
+ .right_margin = 20,
+ .upper_margin = 15,
+ .lower_margin = 4,
+ .hsync_len = 30,
+ .vsync_len = 3,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+ .dma_dev = &mx3_ipu.dev,
+ .name = "CMO_QVGA",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+ /* LCD */
+ MX35_PAD_LD0__IPU_DISPB_DAT_0,
+ MX35_PAD_LD1__IPU_DISPB_DAT_1,
+ MX35_PAD_LD2__IPU_DISPB_DAT_2,
+ MX35_PAD_LD3__IPU_DISPB_DAT_3,
+ MX35_PAD_LD4__IPU_DISPB_DAT_4,
+ MX35_PAD_LD5__IPU_DISPB_DAT_5,
+ MX35_PAD_LD6__IPU_DISPB_DAT_6,
+ MX35_PAD_LD7__IPU_DISPB_DAT_7,
+ MX35_PAD_LD8__IPU_DISPB_DAT_8,
+ MX35_PAD_LD9__IPU_DISPB_DAT_9,
+ MX35_PAD_LD10__IPU_DISPB_DAT_10,
+ MX35_PAD_LD11__IPU_DISPB_DAT_11,
+ MX35_PAD_LD12__IPU_DISPB_DAT_12,
+ MX35_PAD_LD13__IPU_DISPB_DAT_13,
+ MX35_PAD_LD14__IPU_DISPB_DAT_14,
+ MX35_PAD_LD15__IPU_DISPB_DAT_15,
+ MX35_PAD_LD16__IPU_DISPB_DAT_16,
+ MX35_PAD_LD17__IPU_DISPB_DAT_17,
+ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+ /* Backlight */
+ MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+ /* LCD_PWR */
+ MX35_PAD_D3_CLS__GPIO1_4,
+ /* LED */
+ MX35_PAD_LD23__GPIO3_29,
+ /* SWITCH */
+ MX35_PAD_LD19__GPIO3_25,
+ /* UART2 */
+ MX35_PAD_CTS2__UART2_CTS,
+ MX35_PAD_RTS2__UART2_RTS,
+ MX35_PAD_TXD2__UART2_TXD_MUX,
+ MX35_PAD_RXD2__UART2_RXD_MUX,
+ /* I2S */
+ MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+ MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+ MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+ MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+};
+
+#define GPIO_LED1 (2 * 32 + 29)
+#define GPIO_SWITCH1 (2 * 32 + 25)
+#define GPIO_LCDPWR (4)
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power)
+ gpio_direction_output(GPIO_LCDPWR, 1);
+ else
+ gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+ .set_power = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+ .name = "platform-lcd",
+ .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+ {
+ .name = "led1",
+ .default_trigger = "heartbeat",
+ .active_low = 1,
+ .gpio = GPIO_LED1,
+ },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+ .leds = eukrea_mbimxsd_leds,
+ .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &eukrea_mbimxsd_led_info,
+ },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+ {
+ .gpio = GPIO_SWITCH1,
+ .code = BTN_0,
+ .desc = "BP1",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+ .buttons = eukrea_mbimxsd_gpio_buttons,
+ .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+ .name = "gpio-keys",
+ .id = -1,
+ .num_resources = 0,
+ .dev = {
+ .platform_data = &eukrea_mbimxsd_button_data,
+ }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &eukrea_mbimxsd_leds_gpio,
+ &eukrea_mbimxsd_button_device,
+ &eukrea_mbimxsd_lcd_powerdev,
+};
+
- mxc_register_device(&mxc_uart_device1, &uart_pdata);
++static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("tlv320aic23", 0x1a),
+ },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+ .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx35 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+ if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+ ARRAY_SIZE(eukrea_mbimxsd_pads)))
+ printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+ /* SSI unit master I2S codec connected to SSI_AUD4 */
+ mxc_audmux_v2_configure_port(0,
+ MXC_AUDMUX_V2_PTCR_SYN |
+ MXC_AUDMUX_V2_PTCR_TFSDIR |
+ MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+ MXC_AUDMUX_V2_PTCR_TCLKDIR |
+ MXC_AUDMUX_V2_PTCR_TCSEL(3),
+ MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+ );
+ mxc_audmux_v2_configure_port(3,
+ MXC_AUDMUX_V2_PTCR_SYN,
+ MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+ );
+#endif
+
++ imx35_add_imx_uart1(&uart_pdata);
+ mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+ mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+ mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+ gpio_request(GPIO_LED1, "LED1");
+ gpio_direction_output(GPIO_LED1, 1);
+ gpio_free(GPIO_LED1);
+
+ gpio_request(GPIO_SWITCH1, "SWITCH1");
+ gpio_direction_input(GPIO_SWITCH1);
+ gpio_free(GPIO_SWITCH1);
+
+ gpio_request(GPIO_LCDPWR, "LCDPWR");
+ gpio_direction_output(GPIO_LCDPWR, 1);
+ gpio_free(GPIO_SWITCH1);
+
+ i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+ ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
--- /dev/null
- #include <mach/imx-uart.h>
- #include <mach/i2c.h>
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/board-eukrea_cpuimx35.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
- static struct imxuart_platform_data uart_pdata = {
+#include <mach/iomux-mx35.h>
+#include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
++#include "devices-imx35.h"
+#include "devices.h"
+
- static struct imxi2c_platform_data eukrea_cpuimx35_i2c_1_data = {
++static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
- static struct mxc_nand_platform_data pcm037_nand_board_info = {
++static const struct imxi2c_platform_data
++eukrea_cpuimx35_i2c0_data __initconst = {
+ .bitrate = 50000,
+};
+
+#define TSC2007_IRQGPIO (2 * 32 + 2)
+static int ts_get_pendown_state(void)
+{
+ int val = 0;
+ gpio_free(TSC2007_IRQGPIO);
+ gpio_request(TSC2007_IRQGPIO, NULL);
+ gpio_direction_input(TSC2007_IRQGPIO);
+
+ val = gpio_get_value(TSC2007_IRQGPIO);
+
+ gpio_free(TSC2007_IRQGPIO);
+ gpio_request(TSC2007_IRQGPIO, NULL);
+
+ return val ? 0 : 1;
+}
+
+static int ts_init(void)
+{
+ gpio_request(TSC2007_IRQGPIO, NULL);
+ return 0;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+ .model = 2007,
+ .x_plate_ohms = 180,
+ .get_pendown_state = ts_get_pendown_state,
+ .init_platform_hw = ts_init,
+};
+
+static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ }, {
+ I2C_BOARD_INFO("tsc2007", 0x48),
+ .type = "tsc2007",
+ .platform_data = &tsc2007_info,
+ .irq = gpio_to_irq(TSC2007_IRQGPIO),
+ },
+};
+
+static struct platform_device *devices[] __initdata = {
+ &mxc_fec_device,
+ &imx_wdt_device0,
+};
+
+static struct pad_desc eukrea_cpuimx35_pads[] = {
+ /* UART1 */
+ MX35_PAD_CTS1__UART1_CTS,
+ MX35_PAD_RTS1__UART1_RTS,
+ MX35_PAD_TXD1__UART1_TXD_MUX,
+ MX35_PAD_RXD1__UART1_RXD_MUX,
+ /* FEC */
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* I2C1 */
+ MX35_PAD_I2C1_CLK__I2C1_SCL,
+ MX35_PAD_I2C1_DAT__I2C1_SDA,
+ /* TSC2007 IRQ */
+ MX35_PAD_ATA_DA2__GPIO3_2,
+};
+
- mxc_register_device(&mxc_uart_device0, &uart_pdata);
- mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
++static const struct mxc_nand_platform_data
++eukrea_cpuimx35_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ .flash_bbt = 1,
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+ .portsc = MXC_EHCI_MODE_UTMI,
+ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh1_pdata = {
+ .portsc = MXC_EHCI_MODE_SERIAL,
+ .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+ MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx35_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
+ ARRAY_SIZE(eukrea_cpuimx35_pads));
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
- mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx35_i2c_1_data);
++ imx35_add_imx_uart0(&uart_pdata);
++ imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
+
+ i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
+ ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
++ imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+ if (otg_mode_host) {
+ otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+ USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+ mxc_register_device(&mxc_otg_host, &otg_pdata);
+ }
+ mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+#endif
+ if (!otg_mode_host)
+ mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+ eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx35_timer_init(void)
+{
+ mx35_clocks_init();
+}
+
+struct sys_timer eukrea_cpuimx35_timer = {
+ .init = eukrea_cpuimx35_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
+ /* Maintainer: Eukrea Electromatique */
+ .phys_io = MX35_AIPS1_BASE_ADDR,
+ .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx35_map_io,
+ .init_irq = mx35_init_irq,
+ .init_machine = mxc_board_init,
+ .timer = &eukrea_cpuimx35_timer,
+MACHINE_END
#define MX25_UART1_BASE_ADDR 0x43f90000
#define MX25_UART2_BASE_ADDR 0x43f94000
+#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
+ #define MX25_UART3_BASE_ADDR 0x5000c000
+ #define MX25_UART4_BASE_ADDR 0x50008000
+ #define MX25_UART5_BASE_ADDR 0x5002c000
+ #define MX25_CSPI3_BASE_ADDR 0x50004000
+ #define MX25_CSPI2_BASE_ADDR 0x50010000
#define MX25_FEC_BASE_ADDR 0x50038000
+#define MX25_SSI2_BASE_ADDR 0x50014000
+#define MX25_SSI1_BASE_ADDR 0x50034000
#define MX25_NFC_BASE_ADDR 0xbb000000
#define MX25_DRYICE_BASE_ADDR 0x53ffc000
#define MX25_LCDC_BASE_ADDR 0x53fbc000
+#define MX25_KPP_BASE_ADDR 0x43fa8000
+#define MX25_OTG_BASE_ADDR 0x53ff4000
+#define MX25_CSI_BASE_ADDR 0x53ff8000
- #define MX25_INT_SSI2 11
- #define MX25_INT_SSI1 12
- #define MX25_INT_CSI 17
- #define MX25_INT_DRYICE 25
- #define MX25_INT_NANDFC 33
- #define MX25_INT_LCDC 39
- #define MX25_INT_KPP 24
- #define MX25_INT_FEC 57
+ #define MX25_INT_CSPI3 0
+ #define MX25_INT_I2C1 3
+ #define MX25_INT_I2C2 4
+ #define MX25_INT_UART4 5
+ #define MX25_INT_I2C3 10
++#define MX25_INT_SSI2 11
++#define MX25_INT_SSI1 12
+ #define MX25_INT_CSPI2 13
+ #define MX25_INT_CSPI1 14
++#define MX25_INT_CSI 17
+ #define MX25_INT_UART3 18
++#define MX25_INT_KPP 24
+ #define MX25_INT_DRYICE 25
+ #define MX25_INT_UART2 32
+ #define MX25_INT_NANDFC 33
+ #define MX25_INT_LCDC 39
+ #define MX25_INT_UART5 40
+ #define MX25_INT_UART1 45
+ #define MX25_INT_FEC 57
#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR
#ifndef __ASM_ARCH_NAND_H
#define __ASM_ARCH_NAND_H
+#include <linux/mtd/partitions.h>
+
struct mxc_nand_platform_data {
- int width; /* data bus width in bytes */
- int hw_ecc:1; /* 0 if supress hardware ECC */
- int flash_bbt:1; /* set to 1 to use a flash based bbt */
+ unsigned int width; /* data bus width in bytes */
+ unsigned int hw_ecc:1; /* 0 if supress hardware ECC */
+ unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
+ struct mtd_partition *parts; /* partition table */
+ int nr_parts; /* size of parts */
};
#endif /* __ASM_ARCH_NAND_H */
projects / linux-drm-fsl-dcu.git / commitdiff