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(parent: f047604) | patch
amd-xgbe: Base queue fifo size and enablement on ring count
authorLendacky, Thomas <Thomas.Lendacky@amd.com>
Tue, 29 Jul 2014 13:57:31 +0000 (08:57 -0500)
committerDavid S. Miller <davem@davemloft.net>
Thu, 31 Jul 2014 01:46:52 +0000 (18:46 -0700)
commit853eb16b8b6a347315443f2ef010e5b97d8c1577
tree2966ae65124b9dab3c1dc5c26ae887121505b2d3tree | snapshot
parentf047604a3ff1a1d7c8bd4a43c72de3936d71f3c1commit | diff
amd-xgbe: Base queue fifo size and enablement on ring count

When setting the fifo sizes for the queues and enabling the queues
use the number of active Tx and Rx queues that have been enabled
not the maximum number available.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/amd/xgbe/xgbe-dev.c diff | blob | history
drivers/net/ethernet/amd/xgbe/xgbe-main.c diff | blob | history
drivers/net/ethernet/amd/xgbe/xgbe.h diff | blob | history
Freescale DCU DRM driver