MIPS: clear execution hazard after changing FTLB enable
authorPaul Burton <paul.burton@imgtec.com>
Fri, 19 Aug 2016 17:18:28 +0000 (18:18 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 29 Sep 2016 16:59:49 +0000 (18:59 +0200)
commit67acd8d5c606cf42e6726767d705851dec9f6a34
treef47a7004f00792f0c9c05590dda085bdfa2e1a72
parentebd0e0f503d0774407a63ebb5ec1a90bb54941f5
MIPS: clear execution hazard after changing FTLB enable

On current P-series cores from Imagination the FTLB can be enabled or
disabled via a bit in the Config6 register, and an execution hazard is
created by changing the value of bit. The ftlb_disable function already
cleared that hazard but that does no good for other callers. Clear the
hazard in the set_ftlb_enable function that creates it, and only for the
cores where it applies.

This has the effect of reverting c982c6d6c48b ("MIPS: cpu-probe: Remove
cp0 hazard barrier when enabling the FTLB") which was incorrect.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: c982c6d6c48b ("MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB")
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14023/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/cpu-probe.c