fm10k: Reset mailbox global interrupts
authorNgai-Mint Kwan <ngai-mint.kwan@intel.com>
Tue, 7 Jun 2016 23:08:46 +0000 (16:08 -0700)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Wed, 20 Jul 2016 22:22:10 +0000 (15:22 -0700)
commit5e93cbadd3e9db342e48582178b7d241097f51c4
treef3add981b01d6897650e8c3f0ddbe5385d57113a
parent9d73edee5900baff47887b36e9b97f45a7d13b6d
fm10k: Reset mailbox global interrupts

When a data path reset is initiated, write control to the PCIE_GMBX is
yanked from the switch manager. The switch manager writes to this
register to clear mailbox global interrupt bits as part of its mailbox
interrupt handling routine. When the device recovers from the data path
reset and these bits are not cleared, it will prevent future mailbox
global interrupts from being triggered. Upon confirming that the device
has exited from a data path reset, clear these bits to ensure the proper
functioning of the mailbox global interrupt.

Signed-off-by: Ngai-Mint Kwan <ngai-mint.kwan@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Tested-by: Krishneil Singh <Krishneil.k.singh@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/fm10k/fm10k_mbx.h
drivers/net/ethernet/intel/fm10k/fm10k_pf.c