X-Git-Url: http://git.agner.ch/gitweb/?a=blobdiff_plain;f=arch%2Fmips%2Fsibyte%2Fsb1250%2Ftime.c;h=bcb74f2c19484dfb4cecef6e6f7213c9f98e8e71;hb=bdbf77d6707a52bdeff223d0a60df12d086d21d7;hp=511c89d65f3821371ac34a59f4362e830f45f6e5;hpb=3d5271f9883cba7b54762bc4fe027d4172f06db7;p=linux-drm-fsl-dcu.git diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 511c89d65f38..bcb74f2c1948 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -25,14 +25,12 @@ * code to do general bookkeeping (e.g. update jiffies, run * bottom halves, etc.) */ -#include #include #include #include #include #include -#include #include #include #include @@ -47,23 +45,43 @@ #define IMR_IP3_VAL K_INT_MAP_I1 #define IMR_IP4_VAL K_INT_MAP_I2 +#define SB1250_HPT_NUM 3 +#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */ + + extern int sb1250_steal_irq(int irq); +static unsigned int sb1250_hpt_read(void); + +void __init sb1250_hpt_setup(void) +{ + int cpu = smp_processor_id(); + + if (!cpu) { + /* Setup hpt using timer #3 but do not enable irq for it */ + __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); + __raw_writeq(SB1250_HPT_VALUE, + IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT))); + __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); + + mips_hpt_frequency = V_SCD_TIMER_FREQ; + mips_hpt_read = sb1250_hpt_read; + mips_hpt_mask = M_SCD_TIMER_INIT; + } +} + + void sb1250_time_init(void) { int cpu = smp_processor_id(); int irq = K_INT_TIMER_0+cpu; - /* Only have 4 general purpose timers */ - if (cpu > 3) { + /* Only have 4 general purpose timers, and we use last one as hpt */ + if (cpu > 2) { BUG(); } - if (!cpu) { - /* Use our own gettimeoffset() routine */ - do_gettimeoffset = sb1250_gettimeoffset; - } - sb1250_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ @@ -75,10 +93,10 @@ void sb1250_time_init(void) /* Disable the timer and set up the count */ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION - __raw_writeq(50000 / HZ, + __raw_writeq((50000 / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else - __raw_writeq(1000000 / HZ, + __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif @@ -98,12 +116,12 @@ void sb1250_time_init(void) */ } -void sb1250_timer_interrupt(struct pt_regs *regs) +void sb1250_timer_interrupt(void) { int cpu = smp_processor_id(); int irq = K_INT_TIMER_0 + cpu; - /* Reset the timer */ + /* ACK interrupt */ ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); @@ -111,26 +129,25 @@ void sb1250_timer_interrupt(struct pt_regs *regs) /* * CPU 0 handles the global timer interrupt job */ - ll_timer_interrupt(irq, regs); + ll_timer_interrupt(irq); } else { /* * other CPUs should just do profiling and process accounting */ - ll_local_timer_interrupt(irq, regs); + ll_local_timer_interrupt(irq); } } /* - * We use our own do_gettimeoffset() instead of the generic one, - * because the generic one does not work for SMP case. - * In addition, since we use general timer 0 for system time, - * we can get accurate intra-jiffy offset without calibration. + * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over + * again. */ -unsigned long sb1250_gettimeoffset(void) +static unsigned int sb1250_hpt_read(void) { - unsigned long count = - __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); + unsigned int count; - return 1000000/HZ - count; - } + count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)))); + + return SB1250_HPT_VALUE - count; +}