int __init detect_cpu_and_cache_system(void)
{
/* Just SH7206 for now .. */
- cpu_data->type = CPU_SH7206;
+ current_cpu_data.type = CPU_SH7206;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1 << 11);
- cpu_data->dcache.sets = 128;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1 << 11);
+ current_cpu_data.dcache.sets = 128;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
/*
* The icache is the same as the dcache as far as this setup is
* lacks the U bit that the dcache has, none of this has any bearing
* on the cache info.
*/
- cpu_data->icache = cpu_data->dcache;
+ current_cpu_data.icache = current_cpu_data.dcache;
return 0;
}