uint64_t upper:2; /* Normally 2 for XKPHYS */
uint64_t reserved_49_61:13; /* Must be zero */
uint64_t io:1; /* 1 for IO space access */
- uint64_t did:5; /* PCIe DID = 3 */
+ uint64_t did:5; /* PCIe DID = 3 */
uint64_t subdid:3; /* PCIe SubDID = 1 */
uint64_t reserved_36_39:4; /* Must be zero */
uint64_t es:2; /* Endian swap = 1 */
uint64_t upper:2; /* Normally 2 for XKPHYS */
uint64_t reserved_49_61:13; /* Must be zero */
uint64_t io:1; /* 1 for IO space access */
- uint64_t did:5; /* PCIe DID = 3 */
+ uint64_t did:5; /* PCIe DID = 3 */
uint64_t subdid:3; /* PCIe SubDID = 2 */
uint64_t reserved_36_39:4; /* Must be zero */
uint64_t es:2; /* Endian swap = 1 */
uint64_t upper:2; /* Normally 2 for XKPHYS */
uint64_t reserved_49_61:13; /* Must be zero */
uint64_t io:1; /* 1 for IO space access */
- uint64_t did:5; /* PCIe DID = 3 */
+ uint64_t did:5; /* PCIe DID = 3 */
uint64_t subdid:3; /* PCIe SubDID = 3-6 */
uint64_t reserved_36_39:4; /* Must be zero */
uint64_t address:36; /* PCIe Mem address */
* Read a PCIe config space register indirectly. This is used for
* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
*
- * @pcie_port: PCIe port to read from
+ * @pcie_port: PCIe port to read from
* @cfg_offset: Address to read
*
* Returns Value read
* Write a PCIe config space register indirectly. This is used for
* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
*
- * @pcie_port: PCIe port to write to
+ * @pcie_port: PCIe port to write to
* @cfg_offset: Address to write
- * @val: Value to write
+ * @val: Value to write
*/
static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
uint32_t val)
* @pcie_port: PCIe port to access
* @bus: Sub bus
* @dev: Device ID
- * @fn: Device sub function
+ * @fn: Device sub function
* @reg: Register to access
*
* Returns 64bit Octeon IO address
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
- * @fn: Device sub function
+ * @fn: Device sub function
* @reg: Register to access
*
* Returns Result of the read
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
- * @fn: Device sub function
+ * @fn: Device sub function
* @reg: Register to access
*
* Returns Result of the read
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
- * @fn: Device sub function
+ * @fn: Device sub function
* @reg: Register to access
*
* Returns Result of the read
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
- * @fn: Device sub function
+ * @fn: Device sub function
* @reg: Register to access
* @val: Value to write
*/
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
- * @fn: Device sub function
+ * @fn: Device sub function
* @reg: Register to access
* @val: Value to write
*/
* @pcie_port: PCIe port the device is on
* @bus: Sub bus
* @dev: Device ID
- * @fn: Device sub function
+ * @fn: Device sub function
* @reg: Register to access
* @val: Value to write
*/
/* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
- npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
- npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
+ npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
+ npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
/* Setup Mem access SubDIDs */
mem_access_subid.u64 = 0;
mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
- mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
+ mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
bar1_index.u32 = 0;
bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
- bar1_index.s.ca = 1; /* Not Cached */
+ bar1_index.s.ca = 1; /* Not Cached */
bar1_index.s.end_swp = 1; /* Endian Swap mode */
bar1_index.s.addr_v = 1; /* Valid entry */
/* Setup Mem access SubDIDs */
mem_access_subid.u64 = 0;
mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
- mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
- mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
- mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
- mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
- mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
+ mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
+ mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
+ mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
+ mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
+ mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
/* PCIe Adddress Bits <63:34>. */
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
mem_access_subid.cn68xx.ba = 0;
bar1_index.u64 = 0;
bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
- bar1_index.s.ca = 1; /* Not Cached */
+ bar1_index.s.ca = 1; /* Not Cached */
bar1_index.s.end_swp = 1; /* Endian Swap mode */
bar1_index.s.addr_v = 1; /* Valid entry */
*
* @dev: The Linux PCI device structure for the device to map
* @slot: The slot number for this device on __BUS 0__. Linux
- * enumerates through all the bridges and figures out the
- * slot on Bus 0 where this device eventually hooks to.
+ * enumerates through all the bridges and figures out the
+ * slot on Bus 0 where this device eventually hooks to.
* @pin: The PCI interrupt pin read from the device, then swizzled
- * as it goes through each bridge.
+ * as it goes through each bridge.
* Returns Interrupt number for the device
*/
int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
return pin - 1 + OCTEON_IRQ_PCI_INT0;
}
-static void set_cfg_read_retry(u32 retry_cnt)
+static void set_cfg_read_retry(u32 retry_cnt)
{
union cvmx_pemx_ctl_status pemx_ctl;
pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
if (sriox_status_reg.s.srio) {
- srio_war15205 += 1; /* Port is SRIO */
+ srio_war15205 += 1; /* Port is SRIO */
port = 0;
}
}
OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
if (sriox_status_reg.s.srio) {
- srio_war15205 += 1; /* Port is SRIO */
+ srio_war15205 += 1; /* Port is SRIO */
port = 1;
}
}
projects / linux-drm-fsl-dcu.git / blobdiff