2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
41 #include <linux/atomic.h>
43 #define MAX_MSIX_P_PORT 17
45 #define MSIX_LEGACY_SZ 4
46 #define MIN_MSIX_P_PORT 5
49 MLX4_FLAG_MSI_X = 1 << 0,
50 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
51 MLX4_FLAG_MASTER = 1 << 2,
52 MLX4_FLAG_SLAVE = 1 << 3,
53 MLX4_FLAG_SRIOV = 1 << 4,
57 MLX4_PORT_CAP_IS_SM = 1 << 1,
58 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
63 MLX4_MAX_PORT_PKEYS = 128
66 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
67 * These qkeys must not be allowed for general use. This is a 64k range,
68 * and to test for violation, we use the mask (protect against future chg).
70 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
71 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
74 MLX4_BOARD_ID_LEN = 64
81 MLX4_MAX_EQ_NUM = 1024,
82 MLX4_MFUNC_EQ_NUM = 4,
83 MLX4_MFUNC_MAX_EQES = 8,
84 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
87 /* Driver supports 3 diffrent device methods to manage traffic steering:
88 * -device managed - High level API for ib and eth flow steering. FW is
89 * managing flow steering tables.
90 * - B0 steering mode - Common low level API for ib and (if supported) eth.
91 * - A0 steering mode - Limited low level API for eth. In case of IB,
95 MLX4_STEERING_MODE_A0,
96 MLX4_STEERING_MODE_B0,
97 MLX4_STEERING_MODE_DEVICE_MANAGED
100 static inline const char *mlx4_steering_mode_str(int steering_mode)
102 switch (steering_mode) {
103 case MLX4_STEERING_MODE_A0:
104 return "A0 steering";
106 case MLX4_STEERING_MODE_B0:
107 return "B0 steering";
109 case MLX4_STEERING_MODE_DEVICE_MANAGED:
110 return "Device managed flow steering";
113 return "Unrecognize steering mode";
118 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
119 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
120 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
121 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
122 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
123 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
124 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
125 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
126 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
127 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
128 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
129 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
130 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
131 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
132 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
133 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
134 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
135 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
136 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
137 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
138 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
139 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
140 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
141 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
142 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
143 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
144 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
145 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
146 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
147 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
151 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
152 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
153 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
154 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
155 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4,
156 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5
160 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
161 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
165 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
169 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
173 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
176 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
177 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
178 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
179 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
180 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
181 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
185 MLX4_EVENT_TYPE_COMP = 0x00,
186 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
187 MLX4_EVENT_TYPE_COMM_EST = 0x02,
188 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
189 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
190 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
191 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
192 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
193 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
194 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
195 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
196 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
197 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
198 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
199 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
200 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
201 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
202 MLX4_EVENT_TYPE_CMD = 0x0a,
203 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
204 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
205 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
206 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
207 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
208 MLX4_EVENT_TYPE_NONE = 0xff,
212 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
213 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
217 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
220 enum slave_port_state {
226 enum slave_port_gen_event {
227 SLAVE_PORT_GEN_EVENT_DOWN = 0,
228 SLAVE_PORT_GEN_EVENT_UP,
229 SLAVE_PORT_GEN_EVENT_NONE,
232 enum slave_port_state_event {
233 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
234 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
235 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
236 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
240 MLX4_PERM_LOCAL_READ = 1 << 10,
241 MLX4_PERM_LOCAL_WRITE = 1 << 11,
242 MLX4_PERM_REMOTE_READ = 1 << 12,
243 MLX4_PERM_REMOTE_WRITE = 1 << 13,
244 MLX4_PERM_ATOMIC = 1 << 14,
245 MLX4_PERM_BIND_MW = 1 << 15,
249 MLX4_OPCODE_NOP = 0x00,
250 MLX4_OPCODE_SEND_INVAL = 0x01,
251 MLX4_OPCODE_RDMA_WRITE = 0x08,
252 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
253 MLX4_OPCODE_SEND = 0x0a,
254 MLX4_OPCODE_SEND_IMM = 0x0b,
255 MLX4_OPCODE_LSO = 0x0e,
256 MLX4_OPCODE_RDMA_READ = 0x10,
257 MLX4_OPCODE_ATOMIC_CS = 0x11,
258 MLX4_OPCODE_ATOMIC_FA = 0x12,
259 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
260 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
261 MLX4_OPCODE_BIND_MW = 0x18,
262 MLX4_OPCODE_FMR = 0x19,
263 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
264 MLX4_OPCODE_CONFIG_CMD = 0x1f,
266 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
267 MLX4_RECV_OPCODE_SEND = 0x01,
268 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
269 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
271 MLX4_CQE_OPCODE_ERROR = 0x1e,
272 MLX4_CQE_OPCODE_RESIZE = 0x16,
276 MLX4_STAT_RATE_OFFSET = 5
280 MLX4_PROT_IB_IPV6 = 0,
287 MLX4_MTT_FLAG_PRESENT = 1
290 enum mlx4_qp_region {
291 MLX4_QP_REGION_FW = 0,
292 MLX4_QP_REGION_ETH_ADDR,
293 MLX4_QP_REGION_FC_ADDR,
294 MLX4_QP_REGION_FC_EXCH,
298 enum mlx4_port_type {
299 MLX4_PORT_TYPE_NONE = 0,
300 MLX4_PORT_TYPE_IB = 1,
301 MLX4_PORT_TYPE_ETH = 2,
302 MLX4_PORT_TYPE_AUTO = 3
305 enum mlx4_special_vlan_idx {
306 MLX4_NO_VLAN_IDX = 0,
311 enum mlx4_steer_type {
318 MLX4_NUM_FEXCH = 64 * 1024,
322 MLX4_MAX_FAST_REG_PAGES = 511,
326 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
327 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
328 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
331 /* Port mgmt change event handling */
333 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
334 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
335 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
336 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
337 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
340 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
341 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
343 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
345 return (major << 32) | (minor << 16) | subminor;
348 struct mlx4_phys_caps {
349 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
350 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
354 u32 base_tunnel_sqpn;
361 int vl_cap[MLX4_MAX_PORTS + 1];
362 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
363 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
364 u64 def_mac[MLX4_MAX_PORTS + 1];
365 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
366 int gid_table_len[MLX4_MAX_PORTS + 1];
367 int pkey_table_len[MLX4_MAX_PORTS + 1];
368 int trans_type[MLX4_MAX_PORTS + 1];
369 int vendor_oui[MLX4_MAX_PORTS + 1];
370 int wavelength[MLX4_MAX_PORTS + 1];
371 u64 trans_code[MLX4_MAX_PORTS + 1];
372 int local_ca_ack_delay;
376 int bf_regs_per_page;
383 int max_qp_init_rdma;
384 int max_qp_dest_rdma;
398 int num_comp_vectors;
403 int fmr_reserved_mtts;
412 int fs_log_max_ucast_qp_range_size;
424 u16 stat_rate_support;
425 u8 port_width_cap[MLX4_MAX_PORTS + 1];
428 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
430 int reserved_qps_base[MLX4_NUM_QP_REGION];
434 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
435 u8 supported_type[MLX4_MAX_PORTS + 1];
436 u8 suggested_type[MLX4_MAX_PORTS + 1];
437 u8 default_sense[MLX4_MAX_PORTS + 1];
438 u32 port_mask[MLX4_MAX_PORTS + 1];
439 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
441 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
446 u32 userspace_caps; /* userspace must be aware of these */
447 u32 function_caps; /* VFs must be aware of these */
450 struct mlx4_buf_list {
456 struct mlx4_buf_list direct;
457 struct mlx4_buf_list *page_list;
470 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
473 struct mlx4_db_pgdir {
474 struct list_head list;
475 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
476 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
477 unsigned long *bits[2];
482 struct mlx4_ib_user_db_page;
487 struct mlx4_db_pgdir *pgdir;
488 struct mlx4_ib_user_db_page *user_page;
495 struct mlx4_hwq_resources {
519 enum mlx4_mw_type type;
525 struct mlx4_mpt_entry *mpt;
527 dma_addr_t dma_handle;
537 struct list_head bf_list;
538 unsigned free_bf_bmap;
540 void __iomem *bf_map;
544 unsigned long offset;
546 struct mlx4_uar *uar;
551 void (*comp) (struct mlx4_cq *);
552 void (*event) (struct mlx4_cq *, enum mlx4_event);
554 struct mlx4_uar *uar;
566 struct completion free;
570 void (*event) (struct mlx4_qp *, enum mlx4_event);
575 struct completion free;
579 void (*event) (struct mlx4_srq *, enum mlx4_event);
587 struct completion free;
599 __be32 sl_tclass_flowlabel;
612 __be32 sl_tclass_flowlabel;
621 struct mlx4_eth_av eth;
624 struct mlx4_counter {
636 struct pci_dev *pdev;
638 unsigned long num_slaves;
639 struct mlx4_caps caps;
640 struct mlx4_phys_caps phys_caps;
641 struct radix_tree_root qp_table_tree;
643 char board_id[MLX4_BOARD_ID_LEN];
645 int oper_log_mgm_entry_size;
646 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
647 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
683 } __packed port_change;
685 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
687 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
688 } __packed comm_channel_arm;
693 } __packed mac_update;
696 } __packed flr_event;
698 __be16 current_temperature;
699 __be16 warning_threshold;
712 } __packed port_info;
715 __be32 tbl_entries_mask;
716 } __packed tbl_change_info;
718 } __packed port_mgmt_change;
725 struct mlx4_init_port_param {
739 #define mlx4_foreach_port(port, dev, type) \
740 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
741 if ((type) == (dev)->caps.port_mask[(port)])
743 #define mlx4_foreach_non_ib_transport_port(port, dev) \
744 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
745 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
747 #define mlx4_foreach_ib_transport_port(port, dev) \
748 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
749 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
750 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
752 #define MLX4_INVALID_SLAVE_ID 0xFF
754 void handle_port_mgmt_change_event(struct work_struct *work);
756 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
758 return dev->caps.function;
761 static inline int mlx4_is_master(struct mlx4_dev *dev)
763 return dev->flags & MLX4_FLAG_MASTER;
766 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
768 return (qpn < dev->phys_caps.base_sqpn + 8 +
769 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
772 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
774 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
776 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
782 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
784 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
787 static inline int mlx4_is_slave(struct mlx4_dev *dev)
789 return dev->flags & MLX4_FLAG_SLAVE;
792 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
793 struct mlx4_buf *buf);
794 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
795 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
797 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
798 return buf->direct.buf + offset;
800 return buf->page_list[offset >> PAGE_SHIFT].buf +
801 (offset & (PAGE_SIZE - 1));
804 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
805 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
806 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
807 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
809 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
810 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
811 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
812 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
814 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
815 struct mlx4_mtt *mtt);
816 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
817 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
819 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
820 int npages, int page_shift, struct mlx4_mr *mr);
821 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
822 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
823 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
825 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
826 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
827 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
828 int start_index, int npages, u64 *page_list);
829 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
830 struct mlx4_buf *buf);
832 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
833 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
835 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
836 int size, int max_direct);
837 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
840 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
841 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
842 unsigned vector, int collapsed);
843 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
845 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
846 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
848 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
849 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
851 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
852 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
853 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
854 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
855 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
857 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
858 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
860 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
861 int block_mcast_loopback, enum mlx4_protocol prot);
862 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
863 enum mlx4_protocol prot);
864 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
865 u8 port, int block_mcast_loopback,
866 enum mlx4_protocol protocol, u64 *reg_id);
867 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
868 enum mlx4_protocol protocol, u64 reg_id);
871 MLX4_DOMAIN_UVERBS = 0x1000,
872 MLX4_DOMAIN_ETHTOOL = 0x2000,
873 MLX4_DOMAIN_RFS = 0x3000,
874 MLX4_DOMAIN_NIC = 0x5000,
877 enum mlx4_net_trans_rule_id {
878 MLX4_NET_TRANS_RULE_ID_ETH = 0,
879 MLX4_NET_TRANS_RULE_ID_IB,
880 MLX4_NET_TRANS_RULE_ID_IPV6,
881 MLX4_NET_TRANS_RULE_ID_IPV4,
882 MLX4_NET_TRANS_RULE_ID_TCP,
883 MLX4_NET_TRANS_RULE_ID_UDP,
884 MLX4_NET_TRANS_RULE_NUM, /* should be last */
887 extern const u16 __sw_id_hw[];
889 static inline int map_hw_to_sw_id(u16 header_id)
893 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
894 if (header_id == __sw_id_hw[i])
900 enum mlx4_net_trans_promisc_mode {
901 MLX4_FS_PROMISC_NONE = 0,
902 MLX4_FS_PROMISC_UPLINK,
903 /* For future use. Not implemented yet */
904 MLX4_FS_PROMISC_FUNCTION_PORT,
905 MLX4_FS_PROMISC_ALL_MULTI,
908 struct mlx4_spec_eth {
913 u8 ether_type_enable;
919 struct mlx4_spec_tcp_udp {
926 struct mlx4_spec_ipv4 {
933 struct mlx4_spec_ib {
940 struct mlx4_spec_list {
941 struct list_head list;
942 enum mlx4_net_trans_rule_id id;
944 struct mlx4_spec_eth eth;
945 struct mlx4_spec_ib ib;
946 struct mlx4_spec_ipv4 ipv4;
947 struct mlx4_spec_tcp_udp tcp_udp;
951 enum mlx4_net_trans_hw_rule_queue {
952 MLX4_NET_TRANS_Q_FIFO,
953 MLX4_NET_TRANS_Q_LIFO,
956 struct mlx4_net_trans_rule {
957 struct list_head list;
958 enum mlx4_net_trans_hw_rule_queue queue_mode;
961 enum mlx4_net_trans_promisc_mode promisc_mode;
967 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
968 enum mlx4_net_trans_promisc_mode mode);
969 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
970 enum mlx4_net_trans_promisc_mode mode);
971 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
972 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
973 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
974 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
975 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
977 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
978 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
979 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
980 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
981 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
982 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
983 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
984 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
986 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
987 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
988 u8 *pg, u16 *ratelimit);
989 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
990 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
991 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
993 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
994 int npages, u64 iova, u32 *lkey, u32 *rkey);
995 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
996 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
997 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
998 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
999 u32 *lkey, u32 *rkey);
1000 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1001 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1002 int mlx4_test_interrupts(struct mlx4_dev *dev);
1003 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1005 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1007 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1008 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1010 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1011 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1013 int mlx4_flow_attach(struct mlx4_dev *dev,
1014 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1015 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1017 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1020 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1022 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1023 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1024 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1025 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1026 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1027 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1028 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1030 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1031 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1033 #endif /* MLX4_DEVICE_H */