2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/backlight.h>
48 #include <asm/pci-bridge.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/machdep.h>
52 #include <asm/backlight.h>
58 #ifndef CONFIG_PCI /* sanity check */
59 #error This driver requires PCI support.
62 /* version number of this driver */
63 #define RIVAFB_VERSION "0.9.5b"
65 /* ------------------------------------------------------------------------- *
67 * various helpful macros and constants
69 * ------------------------------------------------------------------------- */
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define NVTRACE printk
73 #define NVTRACE if(0) printk
76 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
77 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
79 #ifdef CONFIG_FB_RIVA_DEBUG
80 #define assert(expr) \
82 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
83 #expr,__FILE__,__FUNCTION__,__LINE__); \
90 #define PFX "rivafb: "
92 /* macro that allows you to set overflow bits */
93 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
94 #define SetBit(n) (1<<(n))
95 #define Set8Bits(value) ((value)&0xff)
97 /* HW cursor parameters */
100 /* ------------------------------------------------------------------------- *
104 * ------------------------------------------------------------------------- */
106 static int rivafb_blank(int blank, struct fb_info *info);
108 /* ------------------------------------------------------------------------- *
110 * card identification
112 * ------------------------------------------------------------------------- */
114 static struct pci_device_id rivafb_pci_tbl[] = {
115 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
117 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
119 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 // NF2/IGP version, GeForce 4 MX, NV18
156 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
164 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
166 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
168 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
170 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
180 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
182 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
184 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
186 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
188 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
190 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
192 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
194 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
196 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
198 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
200 { 0, } /* terminate list */
202 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
204 /* ------------------------------------------------------------------------- *
208 * ------------------------------------------------------------------------- */
210 /* command line data, set in rivafb_setup() */
211 static int flatpanel __devinitdata = -1; /* Autodetect later */
212 static int forceCRTC __devinitdata = -1;
213 static int noaccel __devinitdata = 0;
215 static int nomtrr __devinitdata = 0;
218 static char *mode_option __devinitdata = NULL;
219 static int strictmode = 0;
221 static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
222 .type = FB_TYPE_PACKED_PIXELS,
227 static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
237 .activate = FB_ACTIVATE_NOW,
247 .vmode = FB_VMODE_NONINTERLACED
251 static const struct riva_regs reg_template = {
252 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
253 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
254 0x41, 0x01, 0x0F, 0x00, 0x00},
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
256 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
258 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
260 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
267 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
274 #ifdef CONFIG_FB_RIVA_BACKLIGHT
275 /* We do not have any information about which values are allowed, thus
276 * we used safe values.
278 #define MIN_LEVEL 0x158
279 #define MAX_LEVEL 0x534
281 static struct backlight_properties riva_bl_data;
283 static int riva_bl_get_level_brightness(struct riva_par *par,
286 struct fb_info *info = pci_get_drvdata(par->pdev);
289 /* Get and convert the value */
290 mutex_lock(&info->bl_mutex);
291 nlevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
292 mutex_unlock(&info->bl_mutex);
296 else if (nlevel < MIN_LEVEL)
298 else if (nlevel > MAX_LEVEL)
304 static int riva_bl_update_status(struct backlight_device *bd)
306 struct riva_par *par = class_get_devdata(&bd->class_dev);
307 U032 tmp_pcrt, tmp_pmc;
310 if (bd->props->power != FB_BLANK_UNBLANK ||
311 bd->props->fb_blank != FB_BLANK_UNBLANK)
314 level = bd->props->brightness;
316 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
317 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
320 tmp_pmc |= (1 << 31); /* backlight bit */
321 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
323 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
324 par->riva.PMC[0x10F0/4] = tmp_pmc;
329 static int riva_bl_get_brightness(struct backlight_device *bd)
331 return bd->props->brightness;
334 static struct backlight_properties riva_bl_data = {
335 .owner = THIS_MODULE,
336 .get_brightness = riva_bl_get_brightness,
337 .update_status = riva_bl_update_status,
338 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
341 static void riva_bl_init(struct riva_par *par)
343 struct fb_info *info = pci_get_drvdata(par->pdev);
344 struct backlight_device *bd;
350 #ifdef CONFIG_PMAC_BACKLIGHT
351 if (!machine_is(powermac) ||
352 !pmac_has_backlight_type("mnca"))
356 snprintf(name, sizeof(name), "rivabl%d", info->node);
358 bd = backlight_device_register(name, par, &riva_bl_data);
361 printk("riva: Backlight registration failed\n");
365 mutex_lock(&info->bl_mutex);
367 fb_bl_default_curve(info, 0,
368 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
369 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
370 mutex_unlock(&info->bl_mutex);
373 bd->props->brightness = riva_bl_data.max_brightness;
374 bd->props->power = FB_BLANK_UNBLANK;
375 bd->props->update_status(bd);
378 #ifdef CONFIG_PMAC_BACKLIGHT
379 mutex_lock(&pmac_backlight_mutex);
382 mutex_unlock(&pmac_backlight_mutex);
385 printk("riva: Backlight initialized (%s)\n", name);
393 static void riva_bl_exit(struct riva_par *par)
395 struct fb_info *info = pci_get_drvdata(par->pdev);
397 #ifdef CONFIG_PMAC_BACKLIGHT
398 mutex_lock(&pmac_backlight_mutex);
401 mutex_lock(&info->bl_mutex);
403 #ifdef CONFIG_PMAC_BACKLIGHT
404 if (pmac_backlight == info->bl_dev)
405 pmac_backlight = NULL;
408 backlight_device_unregister(info->bl_dev);
410 printk("riva: Backlight unloaded\n");
412 mutex_unlock(&info->bl_mutex);
414 #ifdef CONFIG_PMAC_BACKLIGHT
415 mutex_unlock(&pmac_backlight_mutex);
419 static inline void riva_bl_init(struct riva_par *par) {}
420 static inline void riva_bl_exit(struct riva_par *par) {}
421 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
423 /* ------------------------------------------------------------------------- *
427 * ------------------------------------------------------------------------- */
429 static inline void CRTCout(struct riva_par *par, unsigned char index,
432 VGA_WR08(par->riva.PCIO, 0x3d4, index);
433 VGA_WR08(par->riva.PCIO, 0x3d5, val);
436 static inline unsigned char CRTCin(struct riva_par *par,
439 VGA_WR08(par->riva.PCIO, 0x3d4, index);
440 return (VGA_RD08(par->riva.PCIO, 0x3d5));
443 static inline void GRAout(struct riva_par *par, unsigned char index,
446 VGA_WR08(par->riva.PVIO, 0x3ce, index);
447 VGA_WR08(par->riva.PVIO, 0x3cf, val);
450 static inline unsigned char GRAin(struct riva_par *par,
453 VGA_WR08(par->riva.PVIO, 0x3ce, index);
454 return (VGA_RD08(par->riva.PVIO, 0x3cf));
457 static inline void SEQout(struct riva_par *par, unsigned char index,
460 VGA_WR08(par->riva.PVIO, 0x3c4, index);
461 VGA_WR08(par->riva.PVIO, 0x3c5, val);
464 static inline unsigned char SEQin(struct riva_par *par,
467 VGA_WR08(par->riva.PVIO, 0x3c4, index);
468 return (VGA_RD08(par->riva.PVIO, 0x3c5));
471 static inline void ATTRout(struct riva_par *par, unsigned char index,
474 VGA_WR08(par->riva.PCIO, 0x3c0, index);
475 VGA_WR08(par->riva.PCIO, 0x3c0, val);
478 static inline unsigned char ATTRin(struct riva_par *par,
481 VGA_WR08(par->riva.PCIO, 0x3c0, index);
482 return (VGA_RD08(par->riva.PCIO, 0x3c1));
485 static inline void MISCout(struct riva_par *par, unsigned char val)
487 VGA_WR08(par->riva.PVIO, 0x3c2, val);
490 static inline unsigned char MISCin(struct riva_par *par)
492 return (VGA_RD08(par->riva.PVIO, 0x3cc));
495 static u8 byte_rev[256] = {
496 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
497 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
498 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
499 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
500 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
501 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
502 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
503 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
504 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
505 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
506 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
507 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
508 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
509 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
510 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
511 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
512 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
513 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
514 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
515 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
516 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
517 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
518 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
519 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
520 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
521 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
522 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
523 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
524 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
525 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
526 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
527 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
530 static inline void reverse_order(u32 *l)
533 *a = byte_rev[*a], a++;
534 *a = byte_rev[*a], a++;
535 *a = byte_rev[*a], a++;
539 /* ------------------------------------------------------------------------- *
543 * ------------------------------------------------------------------------- */
546 * rivafb_load_cursor_image - load cursor image to hardware
547 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
548 * @par: pointer to private data
549 * @w: width of cursor image in pixels
550 * @h: height of cursor image in scanlines
551 * @bg: background color (ARGB1555) - alpha bit determines opacity
552 * @fg: foreground color (ARGB1555)
555 * Loads cursor image based on a monochrome source and mask bitmap. The
556 * image bits determines the color of the pixel, 0 for background, 1 for
557 * foreground. Only the affected region (as determined by @w and @h
558 * parameters) will be updated.
563 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
564 u16 bg, u16 fg, u32 w, u32 h)
568 u32 *data = (u32 *)data8;
569 bg = le16_to_cpu(bg);
570 fg = le16_to_cpu(fg);
574 for (i = 0; i < h; i++) {
578 for (j = 0; j < w/2; j++) {
580 #if defined (__BIG_ENDIAN)
581 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
583 tmp |= (b & (1 << 31)) ? fg : bg;
586 tmp = (b & 1) ? fg : bg;
588 tmp |= (b & 1) ? fg << 16 : bg << 16;
591 writel(tmp, &par->riva.CURSOR[k++]);
593 k += (MAX_CURS - w)/2;
597 /* ------------------------------------------------------------------------- *
599 * general utility functions
601 * ------------------------------------------------------------------------- */
604 * riva_wclut - set CLUT entry
605 * @chip: pointer to RIVA_HW_INST object
606 * @regnum: register number
607 * @red: red component
608 * @green: green component
609 * @blue: blue component
612 * Sets color register @regnum.
617 static void riva_wclut(RIVA_HW_INST *chip,
618 unsigned char regnum, unsigned char red,
619 unsigned char green, unsigned char blue)
621 VGA_WR08(chip->PDIO, 0x3c8, regnum);
622 VGA_WR08(chip->PDIO, 0x3c9, red);
623 VGA_WR08(chip->PDIO, 0x3c9, green);
624 VGA_WR08(chip->PDIO, 0x3c9, blue);
628 * riva_rclut - read fromCLUT register
629 * @chip: pointer to RIVA_HW_INST object
630 * @regnum: register number
631 * @red: red component
632 * @green: green component
633 * @blue: blue component
636 * Reads red, green, and blue from color register @regnum.
641 static void riva_rclut(RIVA_HW_INST *chip,
642 unsigned char regnum, unsigned char *red,
643 unsigned char *green, unsigned char *blue)
646 VGA_WR08(chip->PDIO, 0x3c7, regnum);
647 *red = VGA_RD08(chip->PDIO, 0x3c9);
648 *green = VGA_RD08(chip->PDIO, 0x3c9);
649 *blue = VGA_RD08(chip->PDIO, 0x3c9);
653 * riva_save_state - saves current chip state
654 * @par: pointer to riva_par object containing info for current riva board
655 * @regs: pointer to riva_regs object
658 * Saves current chip state to @regs.
664 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
669 par->riva.LockUnlock(&par->riva, 0);
671 par->riva.UnloadStateExt(&par->riva, ®s->ext);
673 regs->misc_output = MISCin(par);
675 for (i = 0; i < NUM_CRT_REGS; i++)
676 regs->crtc[i] = CRTCin(par, i);
678 for (i = 0; i < NUM_ATC_REGS; i++)
679 regs->attr[i] = ATTRin(par, i);
681 for (i = 0; i < NUM_GRC_REGS; i++)
682 regs->gra[i] = GRAin(par, i);
684 for (i = 0; i < NUM_SEQ_REGS; i++)
685 regs->seq[i] = SEQin(par, i);
690 * riva_load_state - loads current chip state
691 * @par: pointer to riva_par object containing info for current riva board
692 * @regs: pointer to riva_regs object
695 * Loads chip state from @regs.
698 * riva_load_video_mode()
703 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
705 RIVA_HW_STATE *state = ®s->ext;
709 CRTCout(par, 0x11, 0x00);
711 par->riva.LockUnlock(&par->riva, 0);
713 par->riva.LoadStateExt(&par->riva, state);
715 MISCout(par, regs->misc_output);
717 for (i = 0; i < NUM_CRT_REGS; i++) {
723 CRTCout(par, i, regs->crtc[i]);
727 for (i = 0; i < NUM_ATC_REGS; i++)
728 ATTRout(par, i, regs->attr[i]);
730 for (i = 0; i < NUM_GRC_REGS; i++)
731 GRAout(par, i, regs->gra[i]);
733 for (i = 0; i < NUM_SEQ_REGS; i++)
734 SEQout(par, i, regs->seq[i]);
739 * riva_load_video_mode - calculate timings
740 * @info: pointer to fb_info object containing info for current riva board
743 * Calculate some timings and then send em off to riva_load_state().
748 static void riva_load_video_mode(struct fb_info *info)
750 int bpp, width, hDisplaySize, hDisplay, hStart,
751 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
752 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
753 struct riva_par *par = info->par;
754 struct riva_regs newmode;
757 /* time to calculate */
758 rivafb_blank(1, info);
760 bpp = info->var.bits_per_pixel;
761 if (bpp == 16 && info->var.green.length == 5)
763 width = info->var.xres_virtual;
764 hDisplaySize = info->var.xres;
765 hDisplay = (hDisplaySize / 8) - 1;
766 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
767 hEnd = (hDisplaySize + info->var.right_margin +
768 info->var.hsync_len) / 8 - 1;
769 hTotal = (hDisplaySize + info->var.right_margin +
770 info->var.hsync_len + info->var.left_margin) / 8 - 5;
771 hBlankStart = hDisplay;
772 hBlankEnd = hTotal + 4;
774 height = info->var.yres_virtual;
775 vDisplay = info->var.yres - 1;
776 vStart = info->var.yres + info->var.lower_margin - 1;
777 vEnd = info->var.yres + info->var.lower_margin +
778 info->var.vsync_len - 1;
779 vTotal = info->var.yres + info->var.lower_margin +
780 info->var.vsync_len + info->var.upper_margin + 2;
781 vBlankStart = vDisplay;
782 vBlankEnd = vTotal + 1;
783 dotClock = 1000000000 / info->var.pixclock;
785 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
787 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
790 if (par->FlatPanel) {
793 vBlankStart = vStart;
796 hBlankEnd = hTotal + 4;
799 newmode.crtc[0x0] = Set8Bits (hTotal);
800 newmode.crtc[0x1] = Set8Bits (hDisplay);
801 newmode.crtc[0x2] = Set8Bits (hBlankStart);
802 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
803 newmode.crtc[0x4] = Set8Bits (hStart);
804 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
805 | SetBitField (hEnd, 4: 0, 4:0);
806 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
807 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
808 | SetBitField (vDisplay, 8: 8, 1:1)
809 | SetBitField (vStart, 8: 8, 2:2)
810 | SetBitField (vBlankStart, 8: 8, 3:3)
812 | SetBitField (vTotal, 9: 9, 5:5)
813 | SetBitField (vDisplay, 9: 9, 6:6)
814 | SetBitField (vStart, 9: 9, 7:7);
815 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
817 newmode.crtc[0x10] = Set8Bits (vStart);
818 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
820 newmode.crtc[0x12] = Set8Bits (vDisplay);
821 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
822 newmode.crtc[0x15] = Set8Bits (vBlankStart);
823 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
825 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
826 | SetBitField(vBlankStart,10:10,3:3)
827 | SetBitField(vStart,10:10,2:2)
828 | SetBitField(vDisplay,10:10,1:1)
829 | SetBitField(vTotal,10:10,0:0);
830 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
831 | SetBitField(hDisplay,8:8,1:1)
832 | SetBitField(hBlankStart,8:8,2:2)
833 | SetBitField(hStart,8:8,3:3);
834 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
835 | SetBitField(vDisplay,11:11,2:2)
836 | SetBitField(vStart,11:11,4:4)
837 | SetBitField(vBlankStart,11:11,6:6);
839 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
840 int tmp = (hTotal >> 1) & ~1;
841 newmode.ext.interlace = Set8Bits(tmp);
842 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
844 newmode.ext.interlace = 0xff; /* interlace off */
846 if (par->riva.Architecture >= NV_ARCH_10)
847 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
849 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
850 newmode.misc_output &= ~0x40;
852 newmode.misc_output |= 0x40;
853 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
854 newmode.misc_output &= ~0x80;
856 newmode.misc_output |= 0x80;
858 par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
859 hDisplaySize, height, dotClock);
861 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
863 if (par->FlatPanel == 1) {
864 newmode.ext.pixel |= (1 << 7);
865 newmode.ext.scale |= (1 << 8);
867 if (par->SecondCRTC) {
868 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
870 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
872 newmode.ext.crtcOwner = 3;
873 newmode.ext.pllsel |= 0x20000800;
874 newmode.ext.vpll2 = newmode.ext.vpll;
875 } else if (par->riva.twoHeads) {
876 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
878 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
880 newmode.ext.crtcOwner = 0;
881 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
883 if (par->FlatPanel == 1) {
884 newmode.ext.pixel |= (1 << 7);
885 newmode.ext.scale |= (1 << 8);
887 newmode.ext.cursorConfig = 0x02000100;
888 par->current_state = newmode;
889 riva_load_state(par, &par->current_state);
890 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
891 rivafb_blank(0, info);
895 static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
898 var->xres = var->xres_virtual = modedb->xres;
899 var->yres = modedb->yres;
900 if (var->yres_virtual < var->yres)
901 var->yres_virtual = var->yres;
902 var->xoffset = var->yoffset = 0;
903 var->pixclock = modedb->pixclock;
904 var->left_margin = modedb->left_margin;
905 var->right_margin = modedb->right_margin;
906 var->upper_margin = modedb->upper_margin;
907 var->lower_margin = modedb->lower_margin;
908 var->hsync_len = modedb->hsync_len;
909 var->vsync_len = modedb->vsync_len;
910 var->sync = modedb->sync;
911 var->vmode = modedb->vmode;
916 * rivafb_do_maximize -
917 * @info: pointer to fb_info object containing info for current riva board
926 * -EINVAL on failure, 0 on success
932 static int rivafb_do_maximize(struct fb_info *info,
933 struct fb_var_screeninfo *var,
949 /* use highest possible virtual resolution */
950 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
951 printk(KERN_WARNING PFX
952 "using maximum available virtual resolution\n");
953 for (i = 0; modes[i].xres != -1; i++) {
954 if (modes[i].xres * nom / den * modes[i].yres <
958 if (modes[i].xres == -1) {
960 "could not find a virtual resolution that fits into video memory!!\n");
961 NVTRACE("EXIT - EINVAL error\n");
964 var->xres_virtual = modes[i].xres;
965 var->yres_virtual = modes[i].yres;
968 "virtual resolution set to maximum of %dx%d\n",
969 var->xres_virtual, var->yres_virtual);
970 } else if (var->xres_virtual == -1) {
971 var->xres_virtual = (info->fix.smem_len * den /
972 (nom * var->yres_virtual)) & ~15;
973 printk(KERN_WARNING PFX
974 "setting virtual X resolution to %d\n", var->xres_virtual);
975 } else if (var->yres_virtual == -1) {
976 var->xres_virtual = (var->xres_virtual + 15) & ~15;
977 var->yres_virtual = info->fix.smem_len * den /
978 (nom * var->xres_virtual);
979 printk(KERN_WARNING PFX
980 "setting virtual Y resolution to %d\n", var->yres_virtual);
982 var->xres_virtual = (var->xres_virtual + 15) & ~15;
983 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
985 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
986 var->xres, var->yres, var->bits_per_pixel);
987 NVTRACE("EXIT - EINVAL error\n");
992 if (var->xres_virtual * nom / den >= 8192) {
993 printk(KERN_WARNING PFX
994 "virtual X resolution (%d) is too high, lowering to %d\n",
995 var->xres_virtual, 8192 * den / nom - 16);
996 var->xres_virtual = 8192 * den / nom - 16;
999 if (var->xres_virtual < var->xres) {
1001 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
1005 if (var->yres_virtual < var->yres) {
1007 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
1010 if (var->yres_virtual > 0x7fff/nom)
1011 var->yres_virtual = 0x7fff/nom;
1012 if (var->xres_virtual > 0x7fff/nom)
1013 var->xres_virtual = 0x7fff/nom;
1019 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
1021 RIVA_FIFO_FREE(par->riva, Patt, 4);
1022 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
1023 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
1024 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
1025 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
1028 /* acceleration routines */
1029 static inline void wait_for_idle(struct riva_par *par)
1031 while (par->riva.Busy(&par->riva));
1035 * Set ROP. Translate X rop into ROP3. Internal routine.
1038 riva_set_rop_solid(struct riva_par *par, int rop)
1040 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1041 RIVA_FIFO_FREE(par->riva, Rop, 1);
1042 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
1046 static void riva_setup_accel(struct fb_info *info)
1048 struct riva_par *par = info->par;
1050 RIVA_FIFO_FREE(par->riva, Clip, 2);
1051 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
1052 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1053 (info->var.xres_virtual & 0xffff) |
1054 (info->var.yres_virtual << 16));
1055 riva_set_rop_solid(par, 0xcc);
1060 * riva_get_cmap_len - query current color map length
1061 * @var: standard kernel fb changeable data
1064 * Get current color map length.
1067 * Length of color map
1070 * rivafb_setcolreg()
1072 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1074 int rc = 256; /* reasonable default */
1076 switch (var->green.length) {
1078 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1081 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1084 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1087 /* should not occur */
1093 /* ------------------------------------------------------------------------- *
1095 * framebuffer operations
1097 * ------------------------------------------------------------------------- */
1099 static int rivafb_open(struct fb_info *info, int user)
1101 struct riva_par *par = info->par;
1102 int cnt = atomic_read(&par->ref_count);
1107 memset(&par->state, 0, sizeof(struct vgastate));
1108 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1109 /* save the DAC for Riva128 */
1110 if (par->riva.Architecture == NV_ARCH_03)
1111 par->state.flags |= VGA_SAVE_CMAP;
1112 save_vga(&par->state);
1114 /* vgaHWunlock() + riva unlock (0x7F) */
1115 CRTCout(par, 0x11, 0xFF);
1116 par->riva.LockUnlock(&par->riva, 0);
1118 riva_save_state(par, &par->initial_state);
1120 atomic_inc(&par->ref_count);
1125 static int rivafb_release(struct fb_info *info, int user)
1127 struct riva_par *par = info->par;
1128 int cnt = atomic_read(&par->ref_count);
1134 par->riva.LockUnlock(&par->riva, 0);
1135 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1136 riva_load_state(par, &par->initial_state);
1138 restore_vga(&par->state);
1140 par->riva.LockUnlock(&par->riva, 1);
1142 atomic_dec(&par->ref_count);
1147 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1149 struct fb_videomode *mode;
1150 struct riva_par *par = info->par;
1151 int nom, den; /* translating from pixels->bytes */
1155 switch (var->bits_per_pixel) {
1157 var->red.offset = var->green.offset = var->blue.offset = 0;
1158 var->red.length = var->green.length = var->blue.length = 8;
1159 var->bits_per_pixel = 8;
1163 var->green.length = 5;
1166 var->bits_per_pixel = 16;
1167 /* The Riva128 supports RGB555 only */
1168 if (par->riva.Architecture == NV_ARCH_03)
1169 var->green.length = 5;
1170 if (var->green.length == 5) {
1171 /* 0rrrrrgg gggbbbbb */
1172 var->red.offset = 10;
1173 var->green.offset = 5;
1174 var->blue.offset = 0;
1175 var->red.length = 5;
1176 var->green.length = 5;
1177 var->blue.length = 5;
1179 /* rrrrrggg gggbbbbb */
1180 var->red.offset = 11;
1181 var->green.offset = 5;
1182 var->blue.offset = 0;
1183 var->red.length = 5;
1184 var->green.length = 6;
1185 var->blue.length = 5;
1191 var->red.length = var->green.length = var->blue.length = 8;
1192 var->bits_per_pixel = 32;
1193 var->red.offset = 16;
1194 var->green.offset = 8;
1195 var->blue.offset = 0;
1201 "mode %dx%dx%d rejected...color depth not supported.\n",
1202 var->xres, var->yres, var->bits_per_pixel);
1203 NVTRACE("EXIT, returning -EINVAL\n");
1208 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1209 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1213 /* calculate modeline if supported by monitor */
1214 if (!mode_valid && info->monspecs.gtf) {
1215 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1220 mode = fb_find_best_mode(var, &info->modelist);
1222 riva_update_var(var, mode);
1227 if (!mode_valid && info->monspecs.modedb_len)
1230 if (var->xres_virtual < var->xres)
1231 var->xres_virtual = var->xres;
1232 if (var->yres_virtual <= var->yres)
1233 var->yres_virtual = -1;
1234 if (rivafb_do_maximize(info, var, nom, den) < 0)
1237 if (var->xoffset < 0)
1239 if (var->yoffset < 0)
1242 /* truncate xoffset and yoffset to maximum if too high */
1243 if (var->xoffset > var->xres_virtual - var->xres)
1244 var->xoffset = var->xres_virtual - var->xres - 1;
1246 if (var->yoffset > var->yres_virtual - var->yres)
1247 var->yoffset = var->yres_virtual - var->yres - 1;
1249 var->red.msb_right =
1250 var->green.msb_right =
1251 var->blue.msb_right =
1252 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1257 static int rivafb_set_par(struct fb_info *info)
1259 struct riva_par *par = info->par;
1262 /* vgaHWunlock() + riva unlock (0x7F) */
1263 CRTCout(par, 0x11, 0xFF);
1264 par->riva.LockUnlock(&par->riva, 0);
1265 riva_load_video_mode(info);
1266 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1267 riva_setup_accel(info);
1269 par->cursor_reset = 1;
1270 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1271 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1272 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1274 if (info->flags & FBINFO_HWACCEL_DISABLED)
1275 info->pixmap.scan_align = 1;
1277 info->pixmap.scan_align = 4;
1283 * rivafb_pan_display
1284 * @var: standard kernel fb changeable data
1286 * @info: pointer to fb_info object containing info for current riva board
1289 * Pan (or wrap, depending on the `vmode' field) the display using the
1290 * `xoffset' and `yoffset' fields of the `var' structure.
1291 * If the values don't fit, return -EINVAL.
1293 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1295 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1296 struct fb_info *info)
1298 struct riva_par *par = info->par;
1302 base = var->yoffset * info->fix.line_length + var->xoffset;
1303 par->riva.SetStartAddress(&par->riva, base);
1308 static int rivafb_blank(int blank, struct fb_info *info)
1310 struct riva_par *par= info->par;
1311 unsigned char tmp, vesa;
1313 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1314 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1322 case FB_BLANK_UNBLANK:
1323 case FB_BLANK_NORMAL:
1325 case FB_BLANK_VSYNC_SUSPEND:
1328 case FB_BLANK_HSYNC_SUSPEND:
1331 case FB_BLANK_POWERDOWN:
1336 SEQout(par, 0x01, tmp);
1337 CRTCout(par, 0x1a, vesa);
1339 #ifdef CONFIG_FB_RIVA_BACKLIGHT
1340 mutex_lock(&info->bl_mutex);
1342 down(&info->bl_dev->sem);
1343 info->bl_dev->props->power = blank;
1344 info->bl_dev->props->update_status(info->bl_dev);
1345 up(&info->bl_dev->sem);
1347 mutex_unlock(&info->bl_mutex);
1357 * @regno: register index
1358 * @red: red component
1359 * @green: green component
1360 * @blue: blue component
1361 * @transp: transparency
1362 * @info: pointer to fb_info object containing info for current riva board
1365 * Set a single color register. The values supplied have a 16 bit
1369 * Return != 0 for invalid regno.
1372 * fbcmap.c:fb_set_cmap()
1374 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1375 unsigned blue, unsigned transp,
1376 struct fb_info *info)
1378 struct riva_par *par = info->par;
1379 RIVA_HW_INST *chip = &par->riva;
1382 if (regno >= riva_get_cmap_len(&info->var))
1385 if (info->var.grayscale) {
1386 /* gray = 0.30*R + 0.59*G + 0.11*B */
1387 red = green = blue =
1388 (red * 77 + green * 151 + blue * 28) >> 8;
1391 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1392 ((u32 *) info->pseudo_palette)[regno] =
1393 (regno << info->var.red.offset) |
1394 (regno << info->var.green.offset) |
1395 (regno << info->var.blue.offset);
1397 * The Riva128 2D engine requires color information in
1398 * TrueColor format even if framebuffer is in DirectColor
1400 if (par->riva.Architecture == NV_ARCH_03) {
1401 switch (info->var.bits_per_pixel) {
1403 par->palette[regno] = ((red & 0xf800) >> 1) |
1404 ((green & 0xf800) >> 6) |
1405 ((blue & 0xf800) >> 11);
1408 par->palette[regno] = ((red & 0xff00) << 8) |
1409 ((green & 0xff00)) |
1410 ((blue & 0xff00) >> 8);
1416 switch (info->var.bits_per_pixel) {
1418 /* "transparent" stuff is completely ignored. */
1419 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1422 if (info->var.green.length == 5) {
1423 for (i = 0; i < 8; i++) {
1424 riva_wclut(chip, regno*8+i, red >> 8,
1425 green >> 8, blue >> 8);
1431 for (i = 0; i < 8; i++) {
1432 riva_wclut(chip, regno*8+i,
1433 red >> 8, green >> 8,
1437 riva_rclut(chip, regno*4, &r, &g, &b);
1438 for (i = 0; i < 4; i++)
1439 riva_wclut(chip, regno*4+i, r,
1444 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1454 * rivafb_fillrect - hardware accelerated color fill function
1455 * @info: pointer to fb_info structure
1456 * @rect: pointer to fb_fillrect structure
1459 * This function fills up a region of framebuffer memory with a solid
1460 * color with a choice of two different ROP's, copy or invert.
1465 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1467 struct riva_par *par = info->par;
1468 u_int color, rop = 0;
1470 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1471 cfb_fillrect(info, rect);
1475 if (info->var.bits_per_pixel == 8)
1476 color = rect->color;
1478 if (par->riva.Architecture != NV_ARCH_03)
1479 color = ((u32 *)info->pseudo_palette)[rect->color];
1481 color = par->palette[rect->color];
1484 switch (rect->rop) {
1494 riva_set_rop_solid(par, rop);
1496 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1497 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1499 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1500 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1501 (rect->dx << 16) | rect->dy);
1503 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1504 (rect->width << 16) | rect->height);
1506 riva_set_rop_solid(par, 0xcc);
1511 * rivafb_copyarea - hardware accelerated blit function
1512 * @info: pointer to fb_info structure
1513 * @region: pointer to fb_copyarea structure
1516 * This copies an area of pixels from one location to another
1521 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1523 struct riva_par *par = info->par;
1525 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1526 cfb_copyarea(info, region);
1530 RIVA_FIFO_FREE(par->riva, Blt, 3);
1531 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1532 (region->sy << 16) | region->sx);
1533 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1534 (region->dy << 16) | region->dx);
1536 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1537 (region->height << 16) | region->width);
1541 static inline void convert_bgcolor_16(u32 *col)
1543 *col = ((*col & 0x0000F800) << 8)
1544 | ((*col & 0x00007E0) << 5)
1545 | ((*col & 0x0000001F) << 3)
1551 * rivafb_imageblit: hardware accelerated color expand function
1552 * @info: pointer to fb_info structure
1553 * @image: pointer to fb_image structure
1556 * If the source is a monochrome bitmap, the function fills up a a region
1557 * of framebuffer memory with pixels whose color is determined by the bit
1558 * setting of the bitmap, 1 - foreground, 0 - background.
1560 * If the source is not a monochrome bitmap, color expansion is not done.
1561 * In this case, it is channeled to a software function.
1566 static void rivafb_imageblit(struct fb_info *info,
1567 const struct fb_image *image)
1569 struct riva_par *par = info->par;
1570 u32 fgx = 0, bgx = 0, width, tmp;
1571 u8 *cdat = (u8 *) image->data;
1572 volatile u32 __iomem *d;
1575 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1576 cfb_imageblit(info, image);
1580 switch (info->var.bits_per_pixel) {
1582 fgx = image->fg_color;
1583 bgx = image->bg_color;
1587 if (par->riva.Architecture != NV_ARCH_03) {
1588 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1589 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1591 fgx = par->palette[image->fg_color];
1592 bgx = par->palette[image->bg_color];
1594 if (info->var.green.length == 6)
1595 convert_bgcolor_16(&bgx);
1599 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1600 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1601 (image->dy << 16) | (image->dx & 0xFFFF));
1602 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1603 (((image->dy + image->height) << 16) |
1604 ((image->dx + image->width) & 0xffff)));
1605 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1606 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1607 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1608 (image->height << 16) | ((image->width + 31) & ~31));
1609 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1610 (image->height << 16) | ((image->width + 31) & ~31));
1611 NV_WR32(&par->riva.Bitmap->PointE, 0,
1612 (image->dy << 16) | (image->dx & 0xFFFF));
1614 d = &par->riva.Bitmap->MonochromeData01E;
1616 width = (image->width + 31)/32;
1617 size = width * image->height;
1618 while (size >= 16) {
1619 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1620 for (i = 0; i < 16; i++) {
1621 tmp = *((u32 *)cdat);
1622 cdat = (u8 *)((u32 *)cdat + 1);
1623 reverse_order(&tmp);
1624 NV_WR32(d, i*4, tmp);
1629 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1630 for (i = 0; i < size; i++) {
1631 tmp = *((u32 *) cdat);
1632 cdat = (u8 *)((u32 *)cdat + 1);
1633 reverse_order(&tmp);
1634 NV_WR32(d, i*4, tmp);
1640 * rivafb_cursor - hardware cursor function
1641 * @info: pointer to info structure
1642 * @cursor: pointer to fbcursor structure
1645 * A cursor function that supports displaying a cursor image via hardware.
1646 * Within the kernel, copy and invert rops are supported. If exported
1647 * to user space, only the copy rop will be supported.
1652 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1654 struct riva_par *par = info->par;
1655 u8 data[MAX_CURS * MAX_CURS/8];
1656 int i, set = cursor->set;
1659 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1662 par->riva.ShowHideCursor(&par->riva, 0);
1664 if (par->cursor_reset) {
1665 set = FB_CUR_SETALL;
1666 par->cursor_reset = 0;
1669 if (set & FB_CUR_SETSIZE)
1670 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1672 if (set & FB_CUR_SETPOS) {
1675 yy = cursor->image.dy - info->var.yoffset;
1676 xx = cursor->image.dx - info->var.xoffset;
1680 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1684 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1685 u32 bg_idx = cursor->image.bg_color;
1686 u32 fg_idx = cursor->image.fg_color;
1687 u32 s_pitch = (cursor->image.width+7) >> 3;
1688 u32 d_pitch = MAX_CURS/8;
1689 u8 *dat = (u8 *) cursor->image.data;
1690 u8 *msk = (u8 *) cursor->mask;
1693 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1696 switch (cursor->rop) {
1698 for (i = 0; i < s_pitch * cursor->image.height; i++)
1699 src[i] = dat[i] ^ msk[i];
1703 for (i = 0; i < s_pitch * cursor->image.height; i++)
1704 src[i] = dat[i] & msk[i];
1708 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1709 cursor->image.height);
1711 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1712 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1713 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1716 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1717 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1718 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1721 par->riva.LockUnlock(&par->riva, 0);
1723 rivafb_load_cursor_image(par, data, bg, fg,
1724 cursor->image.width,
1725 cursor->image.height);
1731 par->riva.ShowHideCursor(&par->riva, 1);
1736 static int rivafb_sync(struct fb_info *info)
1738 struct riva_par *par = info->par;
1744 /* ------------------------------------------------------------------------- *
1746 * initialization helper functions
1748 * ------------------------------------------------------------------------- */
1750 /* kernel interface */
1751 static struct fb_ops riva_fb_ops = {
1752 .owner = THIS_MODULE,
1753 .fb_open = rivafb_open,
1754 .fb_release = rivafb_release,
1755 .fb_check_var = rivafb_check_var,
1756 .fb_set_par = rivafb_set_par,
1757 .fb_setcolreg = rivafb_setcolreg,
1758 .fb_pan_display = rivafb_pan_display,
1759 .fb_blank = rivafb_blank,
1760 .fb_fillrect = rivafb_fillrect,
1761 .fb_copyarea = rivafb_copyarea,
1762 .fb_imageblit = rivafb_imageblit,
1763 .fb_cursor = rivafb_cursor,
1764 .fb_sync = rivafb_sync,
1767 static int __devinit riva_set_fbinfo(struct fb_info *info)
1769 unsigned int cmap_len;
1770 struct riva_par *par = info->par;
1773 info->flags = FBINFO_DEFAULT
1774 | FBINFO_HWACCEL_XPAN
1775 | FBINFO_HWACCEL_YPAN
1776 | FBINFO_HWACCEL_COPYAREA
1777 | FBINFO_HWACCEL_FILLRECT
1778 | FBINFO_HWACCEL_IMAGEBLIT;
1780 /* Accel seems to not work properly on NV30 yet...*/
1781 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1782 printk(KERN_DEBUG PFX "disabling acceleration\n");
1783 info->flags |= FBINFO_HWACCEL_DISABLED;
1786 info->var = rivafb_default_var;
1787 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1788 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1790 info->pseudo_palette = par->pseudo_palette;
1792 cmap_len = riva_get_cmap_len(&info->var);
1793 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1795 info->pixmap.size = 8 * 1024;
1796 info->pixmap.buf_align = 4;
1797 info->pixmap.access_align = 32;
1798 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1799 info->var.yres_virtual = -1;
1801 return (rivafb_check_var(&info->var, info));
1804 #ifdef CONFIG_PPC_OF
1805 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1807 struct riva_par *par = info->par;
1808 struct device_node *dp;
1809 unsigned char *pedid = NULL;
1810 unsigned char *disptype = NULL;
1811 static char *propnames[] = {
1812 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1816 dp = pci_device_to_OF_node(pd);
1817 for (; dp != NULL; dp = dp->child) {
1818 disptype = (unsigned char *)get_property(dp, "display-type", NULL);
1819 if (disptype == NULL)
1821 if (strncmp(disptype, "LCD", 3) != 0)
1823 for (i = 0; propnames[i] != NULL; ++i) {
1824 pedid = (unsigned char *)
1825 get_property(dp, propnames[i], NULL);
1826 if (pedid != NULL) {
1828 NVTRACE("LCD found.\n");
1836 #endif /* CONFIG_PPC_OF */
1838 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1839 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1841 struct riva_par *par = info->par;
1842 struct fb_var_screeninfo var;
1846 riva_create_i2c_busses(par);
1847 for (i = 0; i < par->bus; i++) {
1848 riva_probe_i2c_connector(par, i+1, &par->EDID);
1849 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1850 printk(PFX "Found EDID Block from BUS %i\n", i);
1856 return (par->EDID) ? 1 : 0;
1858 #endif /* CONFIG_FB_RIVA_I2C */
1860 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1861 struct fb_info *info)
1863 struct fb_monspecs *specs = &info->monspecs;
1864 struct fb_videomode modedb;
1867 /* respect mode options */
1869 fb_find_mode(var, info, mode_option,
1870 specs->modedb, specs->modedb_len,
1872 } else if (specs->modedb != NULL) {
1873 /* get preferred timing */
1874 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1877 for (i = 0; i < specs->modedb_len; i++) {
1878 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1879 modedb = specs->modedb[i];
1884 /* otherwise, get first mode in database */
1885 modedb = specs->modedb[0];
1887 var->bits_per_pixel = 8;
1888 riva_update_var(var, &modedb);
1894 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1897 #ifdef CONFIG_PPC_OF
1898 if (!riva_get_EDID_OF(info, pdev))
1899 printk(PFX "could not retrieve EDID from OF\n");
1900 #elif defined(CONFIG_FB_RIVA_I2C)
1901 if (!riva_get_EDID_i2c(info))
1902 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1908 static void __devinit riva_get_edidinfo(struct fb_info *info)
1910 struct fb_var_screeninfo *var = &rivafb_default_var;
1911 struct riva_par *par = info->par;
1913 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1914 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1916 riva_update_default_var(var, info);
1918 /* if user specified flatpanel, we respect that */
1919 if (info->monspecs.input & FB_DISP_DDI)
1923 /* ------------------------------------------------------------------------- *
1927 * ------------------------------------------------------------------------- */
1929 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1933 switch (pd->device & 0x0ff0) {
1934 case 0x0100: /* GeForce 256 */
1935 case 0x0110: /* GeForce2 MX */
1936 case 0x0150: /* GeForce2 */
1937 case 0x0170: /* GeForce4 MX */
1938 case 0x0180: /* GeForce4 MX (8x AGP) */
1939 case 0x01A0: /* nForce */
1940 case 0x01F0: /* nForce2 */
1943 case 0x0200: /* GeForce3 */
1944 case 0x0250: /* GeForce4 Ti */
1945 case 0x0280: /* GeForce4 Ti (8x AGP) */
1948 case 0x0300: /* GeForceFX 5800 */
1949 case 0x0310: /* GeForceFX 5600 */
1950 case 0x0320: /* GeForceFX 5200 */
1951 case 0x0330: /* GeForceFX 5900 */
1952 case 0x0340: /* GeForceFX 5700 */
1955 case 0x0020: /* TNT, TNT2 */
1958 case 0x0010: /* Riva128 */
1961 default: /* unknown architecture */
1967 static int __devinit rivafb_probe(struct pci_dev *pd,
1968 const struct pci_device_id *ent)
1970 struct riva_par *default_par;
1971 struct fb_info *info;
1977 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1979 printk (KERN_ERR PFX "could not allocate memory\n");
1983 default_par = info->par;
1984 default_par->pdev = pd;
1986 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1987 if (info->pixmap.addr == NULL) {
1989 goto err_framebuffer_release;
1991 memset(info->pixmap.addr, 0, 8 * 1024);
1993 ret = pci_enable_device(pd);
1995 printk(KERN_ERR PFX "cannot enable PCI device\n");
1996 goto err_free_pixmap;
1999 ret = pci_request_regions(pd, "rivafb");
2001 printk(KERN_ERR PFX "cannot request PCI regions\n");
2002 goto err_disable_device;
2005 default_par->riva.Architecture = riva_get_arch(pd);
2007 default_par->Chipset = (pd->vendor << 16) | pd->device;
2008 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
2010 if(default_par->riva.Architecture == 0) {
2011 printk(KERN_ERR PFX "unknown NV_ARCH\n");
2013 goto err_release_region;
2015 if(default_par->riva.Architecture == NV_ARCH_10 ||
2016 default_par->riva.Architecture == NV_ARCH_20 ||
2017 default_par->riva.Architecture == NV_ARCH_30) {
2018 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
2020 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
2023 default_par->FlatPanel = flatpanel;
2025 printk(KERN_INFO PFX "flatpanel support enabled\n");
2026 default_par->forceCRTC = forceCRTC;
2028 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
2029 rivafb_fix.smem_len = pci_resource_len(pd, 1);
2032 /* enable IO and mem if not already done */
2035 pci_read_config_word(pd, PCI_COMMAND, &cmd);
2036 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
2037 pci_write_config_word(pd, PCI_COMMAND, cmd);
2040 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
2041 rivafb_fix.smem_start = pci_resource_start(pd, 1);
2043 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
2044 rivafb_fix.mmio_len);
2045 if (!default_par->ctrl_base) {
2046 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2048 goto err_release_region;
2051 switch (default_par->riva.Architecture) {
2053 /* Riva128's PRAMIN is in the "framebuffer" space
2054 * Since these cards were never made with more than 8 megabytes
2055 * we can safely allocate this separately.
2057 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2058 if (!default_par->riva.PRAMIN) {
2059 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2061 goto err_iounmap_ctrl_base;
2068 default_par->riva.PCRTC0 =
2069 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2070 default_par->riva.PRAMIN =
2071 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2074 riva_common_setup(default_par);
2076 if (default_par->riva.Architecture == NV_ARCH_03) {
2077 default_par->riva.PCRTC = default_par->riva.PCRTC0
2078 = default_par->riva.PGRAPH;
2081 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2082 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2083 info->screen_base = ioremap(rivafb_fix.smem_start,
2084 rivafb_fix.smem_len);
2085 if (!info->screen_base) {
2086 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2088 goto err_iounmap_pramin;
2093 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2094 rivafb_fix.smem_len,
2095 MTRR_TYPE_WRCOMB, 1);
2096 if (default_par->mtrr.vram < 0) {
2097 printk(KERN_ERR PFX "unable to setup MTRR\n");
2099 default_par->mtrr.vram_valid = 1;
2100 /* let there be speed */
2101 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2104 #endif /* CONFIG_MTRR */
2106 info->fbops = &riva_fb_ops;
2107 info->fix = rivafb_fix;
2108 riva_get_EDID(info, pd);
2109 riva_get_edidinfo(info);
2111 ret=riva_set_fbinfo(info);
2113 printk(KERN_ERR PFX "error setting initial video mode\n");
2114 goto err_iounmap_screen_base;
2117 fb_destroy_modedb(info->monspecs.modedb);
2118 info->monspecs.modedb = NULL;
2119 ret = register_framebuffer(info);
2122 "error registering riva framebuffer\n");
2123 goto err_iounmap_screen_base;
2126 pci_set_drvdata(pd, info);
2128 printk(KERN_INFO PFX
2129 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2132 info->fix.smem_len / (1024 * 1024),
2133 info->fix.smem_start);
2135 riva_bl_init(info->par);
2140 err_iounmap_screen_base:
2141 #ifdef CONFIG_FB_RIVA_I2C
2142 riva_delete_i2c_busses(info->par);
2144 iounmap(info->screen_base);
2146 if (default_par->riva.Architecture == NV_ARCH_03)
2147 iounmap(default_par->riva.PRAMIN);
2148 err_iounmap_ctrl_base:
2149 iounmap(default_par->ctrl_base);
2151 pci_release_regions(pd);
2154 kfree(info->pixmap.addr);
2155 err_framebuffer_release:
2156 framebuffer_release(info);
2161 static void __exit rivafb_remove(struct pci_dev *pd)
2163 struct fb_info *info = pci_get_drvdata(pd);
2164 struct riva_par *par = info->par;
2170 #ifdef CONFIG_FB_RIVA_I2C
2171 riva_delete_i2c_busses(par);
2175 unregister_framebuffer(info);
2177 if (par->mtrr.vram_valid)
2178 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2179 info->fix.smem_len);
2180 #endif /* CONFIG_MTRR */
2182 iounmap(par->ctrl_base);
2183 iounmap(info->screen_base);
2184 if (par->riva.Architecture == NV_ARCH_03)
2185 iounmap(par->riva.PRAMIN);
2186 pci_release_regions(pd);
2187 kfree(info->pixmap.addr);
2188 framebuffer_release(info);
2189 pci_set_drvdata(pd, NULL);
2193 /* ------------------------------------------------------------------------- *
2197 * ------------------------------------------------------------------------- */
2200 static int __init rivafb_setup(char *options)
2205 if (!options || !*options)
2208 while ((this_opt = strsep(&options, ",")) != NULL) {
2209 if (!strncmp(this_opt, "forceCRTC", 9)) {
2213 if (!*p || !*(++p)) continue;
2214 forceCRTC = *p - '0';
2215 if (forceCRTC < 0 || forceCRTC > 1)
2217 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2220 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2223 } else if (!strncmp(this_opt, "strictmode", 10)) {
2225 } else if (!strncmp(this_opt, "noaccel", 7)) {
2228 mode_option = this_opt;
2233 #endif /* !MODULE */
2235 static struct pci_driver rivafb_driver = {
2237 .id_table = rivafb_pci_tbl,
2238 .probe = rivafb_probe,
2239 .remove = __exit_p(rivafb_remove),
2244 /* ------------------------------------------------------------------------- *
2248 * ------------------------------------------------------------------------- */
2250 static int __devinit rivafb_init(void)
2253 char *option = NULL;
2255 if (fb_get_options("rivafb", &option))
2257 rivafb_setup(option);
2259 return pci_register_driver(&rivafb_driver);
2263 module_init(rivafb_init);
2266 static void __exit rivafb_exit(void)
2268 pci_unregister_driver(&rivafb_driver);
2271 module_exit(rivafb_exit);
2274 module_param(noaccel, bool, 0);
2275 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2276 module_param(flatpanel, int, 0);
2277 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2278 module_param(forceCRTC, int, 0);
2279 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2281 module_param(nomtrr, bool, 0);
2282 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2284 module_param(strictmode, bool, 0);
2285 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2287 MODULE_AUTHOR("Ani Joshi, maintainer");
2288 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2289 MODULE_LICENSE("GPL");