drivers/usb/host/isp1760-hcd.c

   1 /*
   2  * Driver for the NXP ISP1760 chip
   3  *
   4  * However, the code might contain some bugs. What doesn't work for sure is:
   5  * - ISO
   6  * - OTG
   7  e The interrupt line is configured as active low, level.
   8  *
   9  * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10  *
  11  * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
  12  *
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/list.h>
  18 #include <linux/usb.h>
  19 #include <linux/usb/hcd.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <asm/unaligned.h>
  25 #include <asm/cacheflush.h>
  26
  27 #include "isp1760-hcd.h"
  28
  29 static struct kmem_cache *qtd_cachep;
  30 static struct kmem_cache *qh_cachep;
  31 static struct kmem_cache *urb_listitem_cachep;
  32
  33 struct isp1760_hcd {
  34         u32 hcs_params;
  35         spinlock_t              lock;
  36         struct slotinfo         atl_slots[32];
  37         int                     atl_done_map;
  38         struct slotinfo         int_slots[32];
  39         int                     int_done_map;
  40         struct memory_chunk memory_pool[BLOCKS];
  41         struct list_head        controlqhs, bulkqhs, interruptqhs;
  42         int active_ptds;
  43
  44         /* periodic schedule support */
  45 #define DEFAULT_I_TDPS          1024
  46         unsigned                periodic_size;
  47         unsigned                i_thresh;
  48         unsigned long           reset_done;
  49         unsigned long           next_statechange;
  50         unsigned int            devflags;
  51 };
  52
  53 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  54 {
  55         return (struct isp1760_hcd *) (hcd->hcd_priv);
  56 }
  57
  58 /* Section 2.2 Host Controller Capability Registers */
  59 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
  60 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
  61 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
  62 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
  63 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
  64 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
  65 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
  66
  67 /* Section 2.3 Host Controller Operational Registers */
  68 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
  69 #define CMD_RESET       (1<<1)          /* reset HC not bus */
  70 #define CMD_RUN         (1<<0)          /* start/stop HC */
  71 #define STS_PCD         (1<<2)          /* port change detect */
  72 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
  73
  74 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
  75 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
  76 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10))  /* USB 1.1 device */
  77 #define PORT_RESET      (1<<8)          /* reset port */
  78 #define PORT_SUSPEND    (1<<7)          /* suspend port */
  79 #define PORT_RESUME     (1<<6)          /* resume it */
  80 #define PORT_PE         (1<<2)          /* port enable */
  81 #define PORT_CSC        (1<<1)          /* connect status change */
  82 #define PORT_CONNECT    (1<<0)          /* device connected */
  83 #define PORT_RWC_BITS   (PORT_CSC)
  84
  85 struct isp1760_qtd {
  86         u8 packet_type;
  87         void *data_buffer;
  88         u32 payload_addr;
  89
  90         /* the rest is HCD-private */
  91         struct list_head qtd_list;
  92         struct urb *urb;
  93         size_t length;
  94         size_t actual_length;
  95
  96         /* QTD_ENQUEUED:        waiting for transfer (inactive) */
  97         /* QTD_PAYLOAD_ALLOC:   chip mem has been allocated for payload */
  98         /* QTD_XFER_STARTED:    valid ptd has been written to isp176x - only
  99                                 interrupt handler may touch this qtd! */
 100         /* QTD_XFER_COMPLETE:   payload has been transferred successfully */
 101         /* QTD_RETIRE:          transfer error/abort qtd */
 102 #define QTD_ENQUEUED            0
 103 #define QTD_PAYLOAD_ALLOC       1
 104 #define QTD_XFER_STARTED        2
 105 #define QTD_XFER_COMPLETE       3
 106 #define QTD_RETIRE              4
 107         u32 status;
 108 };
 109
 110 /* Queue head, one for each active endpoint */
 111 struct isp1760_qh {
 112         struct list_head qh_list;
 113         struct list_head qtd_list;
 114         u32 toggle;
 115         u32 ping;
 116         int slot;
 117 };
 118
 119 struct urb_listitem {
 120         struct list_head urb_list;
 121         struct urb *urb;
 122 };
 123
 124 /*
 125  * Access functions for isp176x registers (addresses 0..0x03FF).
 126  */
 127 static u32 reg_read32(void __iomem *base, u32 reg)
 128 {
 129         return readl(base + reg);
 130 }
 131
 132 static void reg_write32(void __iomem *base, u32 reg, u32 val)
 133 {
 134         writel(val, base + reg);
 135 }
 136
 137 /*
 138  * Access functions for isp176x memory (offset >= 0x0400).
 139  *
 140  * bank_reads8() reads memory locations prefetched by an earlier write to
 141  * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
 142  * bank optimizations, you should use the more generic mem_reads8() below.
 143  *
 144  * For access to ptd memory, use the specialized ptd_read() and ptd_write()
 145  * below.
 146  *
 147  * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
 148  * doesn't quite work because some people have to enforce 32-bit access
 149  */
 150 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
 151                                                         __u32 *dst, u32 bytes)
 152 {
 153         __u32 __iomem *src;
 154         u32 val;
 155         __u8 *src_byteptr;
 156         __u8 *dst_byteptr;
 157
 158         src = src_base + (bank_addr | src_offset);
 159
 160         if (src_offset < PAYLOAD_OFFSET) {
 161                 while (bytes >= 4) {
 162                         *dst = le32_to_cpu(__raw_readl(src));
 163                         bytes -= 4;
 164                         src++;
 165                         dst++;
 166                 }
 167         } else {
 168                 while (bytes >= 4) {
 169                         *dst = __raw_readl(src);
 170                         bytes -= 4;
 171                         src++;
 172                         dst++;
 173                 }
 174         }
 175
 176         if (!bytes)
 177                 return;
 178
 179         /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
 180          * allocated.
 181          */
 182         if (src_offset < PAYLOAD_OFFSET)
 183                 val = le32_to_cpu(__raw_readl(src));
 184         else
 185                 val = __raw_readl(src);
 186
 187         dst_byteptr = (void *) dst;
 188         src_byteptr = (void *) &val;
 189         while (bytes > 0) {
 190                 *dst_byteptr = *src_byteptr;
 191                 dst_byteptr++;
 192                 src_byteptr++;
 193                 bytes--;
 194         }
 195 }
 196
 197 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
 198                                                                 u32 bytes)
 199 {
 200         reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
 201         ndelay(90);
 202         bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
 203 }
 204
 205 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
 206                                                 __u32 const *src, u32 bytes)
 207 {
 208         __u32 __iomem *dst;
 209
 210         dst = dst_base + dst_offset;
 211
 212         if (dst_offset < PAYLOAD_OFFSET) {
 213                 while (bytes >= 4) {
 214                         __raw_writel(cpu_to_le32(*src), dst);
 215                         bytes -= 4;
 216                         src++;
 217                         dst++;
 218                 }
 219         } else {
 220                 while (bytes >= 4) {
 221                         __raw_writel(*src, dst);
 222                         bytes -= 4;
 223                         src++;
 224                         dst++;
 225                 }
 226         }
 227
 228         if (!bytes)
 229                 return;
 230         /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
 231          * extra bytes should not be read by the HW.
 232          */
 233
 234         if (dst_offset < PAYLOAD_OFFSET)
 235                 __raw_writel(cpu_to_le32(*src), dst);
 236         else
 237                 __raw_writel(*src, dst);
 238 }
 239
 240 /*
 241  * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
 242  * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
 243  */
 244 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
 245                                                                 struct ptd *ptd)
 246 {
 247         reg_write32(base, HC_MEMORY_REG,
 248                                 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
 249         ndelay(90);
 250         bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
 251                                                 (void *) ptd, sizeof(*ptd));
 252 }
 253
 254 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
 255                                                                 struct ptd *ptd)
 256 {
 257         mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
 258                                                 &ptd->dw1, 7*sizeof(ptd->dw1));
 259         /* Make sure dw0 gets written last (after other dw's and after payload)
 260            since it contains the enable bit */
 261         wmb();
 262         mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
 263                                                         sizeof(ptd->dw0));
 264 }
 265
 266
 267 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
 268 static void init_memory(struct isp1760_hcd *priv)
 269 {
 270         int i, curr;
 271         u32 payload_addr;
 272
 273         payload_addr = PAYLOAD_OFFSET;
 274         for (i = 0; i < BLOCK_1_NUM; i++) {
 275                 priv->memory_pool[i].start = payload_addr;
 276                 priv->memory_pool[i].size = BLOCK_1_SIZE;
 277                 priv->memory_pool[i].free = 1;
 278                 payload_addr += priv->memory_pool[i].size;
 279         }
 280
 281         curr = i;
 282         for (i = 0; i < BLOCK_2_NUM; i++) {
 283                 priv->memory_pool[curr + i].start = payload_addr;
 284                 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
 285                 priv->memory_pool[curr + i].free = 1;
 286                 payload_addr += priv->memory_pool[curr + i].size;
 287         }
 288
 289         curr = i;
 290         for (i = 0; i < BLOCK_3_NUM; i++) {
 291                 priv->memory_pool[curr + i].start = payload_addr;
 292                 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
 293                 priv->memory_pool[curr + i].free = 1;
 294                 payload_addr += priv->memory_pool[curr + i].size;
 295         }
 296
 297         WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
 298 }
 299
 300 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 301 {
 302         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 303         int i;
 304
 305         WARN_ON(qtd->payload_addr);
 306
 307         if (!qtd->length)
 308                 return;
 309
 310         for (i = 0; i < BLOCKS; i++) {
 311                 if (priv->memory_pool[i].size >= qtd->length &&
 312                                 priv->memory_pool[i].free) {
 313                         priv->memory_pool[i].free = 0;
 314                         qtd->payload_addr = priv->memory_pool[i].start;
 315                         return;
 316                 }
 317         }
 318 }
 319
 320 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
 321 {
 322         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 323         int i;
 324
 325         if (!qtd->payload_addr)
 326                 return;
 327
 328         for (i = 0; i < BLOCKS; i++) {
 329                 if (priv->memory_pool[i].start == qtd->payload_addr) {
 330                         WARN_ON(priv->memory_pool[i].free);
 331                         priv->memory_pool[i].free = 1;
 332                         qtd->payload_addr = 0;
 333                         return;
 334                 }
 335         }
 336
 337         dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
 338                                                 __func__, qtd->payload_addr);
 339         WARN_ON(1);
 340         qtd->payload_addr = 0;
 341 }
 342
 343 static int handshake(struct usb_hcd *hcd, u32 reg,
 344                       u32 mask, u32 done, int usec)
 345 {
 346         u32 result;
 347
 348         do {
 349                 result = reg_read32(hcd->regs, reg);
 350                 if (result == ~0)
 351                         return -ENODEV;
 352                 result &= mask;
 353                 if (result == done)
 354                         return 0;
 355                 udelay(1);
 356                 usec--;
 357         } while (usec > 0);
 358         return -ETIMEDOUT;
 359 }
 360
 361 /* reset a non-running (STS_HALT == 1) controller */
 362 static int ehci_reset(struct usb_hcd *hcd)
 363 {
 364         int retval;
 365         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 366
 367         u32 command = reg_read32(hcd->regs, HC_USBCMD);
 368
 369         command |= CMD_RESET;
 370         reg_write32(hcd->regs, HC_USBCMD, command);
 371         hcd->state = HC_STATE_HALT;
 372         priv->next_statechange = jiffies;
 373         retval = handshake(hcd, HC_USBCMD,
 374                             CMD_RESET, 0, 250 * 1000);
 375         return retval;
 376 }
 377
 378 static struct isp1760_qh *qh_alloc(gfp_t flags)
 379 {
 380         struct isp1760_qh *qh;
 381
 382         qh = kmem_cache_zalloc(qh_cachep, flags);
 383         if (!qh)
 384                 return NULL;
 385
 386         INIT_LIST_HEAD(&qh->qh_list);
 387         INIT_LIST_HEAD(&qh->qtd_list);
 388         qh->slot = -1;
 389
 390         return qh;
 391 }
 392
 393 static void qh_free(struct isp1760_qh *qh)
 394 {
 395         WARN_ON(!list_empty(&qh->qtd_list));
 396         WARN_ON(qh->slot > -1);
 397         kmem_cache_free(qh_cachep, qh);
 398 }
 399
 400 /* one-time init, only for memory state */
 401 static int priv_init(struct usb_hcd *hcd)
 402 {
 403         struct isp1760_hcd              *priv = hcd_to_priv(hcd);
 404         u32                     hcc_params;
 405
 406         spin_lock_init(&priv->lock);
 407
 408         INIT_LIST_HEAD(&priv->interruptqhs);
 409         INIT_LIST_HEAD(&priv->controlqhs);
 410         INIT_LIST_HEAD(&priv->bulkqhs);
 411
 412         /*
 413          * hw default: 1K periodic list heads, one per frame.
 414          * periodic_size can shrink by USBCMD update if hcc_params allows.
 415          */
 416         priv->periodic_size = DEFAULT_I_TDPS;
 417
 418         /* controllers may cache some of the periodic schedule ... */
 419         hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
 420         /* full frame cache */
 421         if (HCC_ISOC_CACHE(hcc_params))
 422                 priv->i_thresh = 8;
 423         else /* N microframes cached */
 424                 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 425
 426         return 0;
 427 }
 428
 429 static int isp1760_hc_setup(struct usb_hcd *hcd)
 430 {
 431         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 432         int result;
 433         u32 scratch, hwmode;
 434
 435         /* Setup HW Mode Control: This assumes a level active-low interrupt */
 436         hwmode = HW_DATA_BUS_32BIT;
 437
 438         if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
 439                 hwmode &= ~HW_DATA_BUS_32BIT;
 440         if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
 441                 hwmode |= HW_ANA_DIGI_OC;
 442         if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
 443                 hwmode |= HW_DACK_POL_HIGH;
 444         if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
 445                 hwmode |= HW_DREQ_POL_HIGH;
 446         if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
 447                 hwmode |= HW_INTR_HIGH_ACT;
 448         if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
 449                 hwmode |= HW_INTR_EDGE_TRIG;
 450
 451         /*
 452          * We have to set this first in case we're in 16-bit mode.
 453          * Write it twice to ensure correct upper bits if switching
 454          * to 16-bit mode.
 455          */
 456         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 457         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 458
 459         reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
 460         /* Change bus pattern */
 461         scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
 462         scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
 463         if (scratch != 0xdeadbabe) {
 464                 dev_err(hcd->self.controller, "Scratch test failed.\n");
 465                 return -ENODEV;
 466         }
 467
 468         /* pre reset */
 469         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
 470         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 471         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 472         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
 473
 474         /* reset */
 475         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
 476         mdelay(100);
 477
 478         reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
 479         mdelay(100);
 480
 481         result = ehci_reset(hcd);
 482         if (result)
 483                 return result;
 484
 485         /* Step 11 passed */
 486
 487         dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
 488                            (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
 489                            16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
 490                            "analog" : "digital");
 491
 492         /* This is weird: at the first plug-in of a device there seems to be
 493            one packet queued that never gets returned? */
 494         priv->active_ptds = -1;
 495
 496         /* ATL reset */
 497         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
 498         mdelay(10);
 499         reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
 500
 501         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
 502
 503         /*
 504          * PORT 1 Control register of the ISP1760 is the OTG control
 505          * register on ISP1761. Since there is no OTG or device controller
 506          * support in this driver, we use port 1 as a "normal" USB host port on
 507          * both chips.
 508          */
 509         reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
 510         mdelay(10);
 511
 512         priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
 513
 514         return priv_init(hcd);
 515 }
 516
 517 static u32 base_to_chip(u32 base)
 518 {
 519         return ((base - 0x400) >> 3);
 520 }
 521
 522 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
 523 {
 524         struct urb *urb;
 525
 526         if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 527                 return 1;
 528
 529         urb = qtd->urb;
 530         qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
 531         return (qtd->urb != urb);
 532 }
 533
 534 /* magic numbers that can affect system performance */
 535 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
 536 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
 537 #define EHCI_TUNE_RL_TT         0
 538 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
 539 #define EHCI_TUNE_MULT_TT       1
 540 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
 541
 542 static void create_ptd_atl(struct isp1760_qh *qh,
 543                         struct isp1760_qtd *qtd, struct ptd *ptd)
 544 {
 545         u32 maxpacket;
 546         u32 multi;
 547         u32 rl = RL_COUNTER;
 548         u32 nak = NAK_COUNTER;
 549
 550         memset(ptd, 0, sizeof(*ptd));
 551
 552         /* according to 3.6.2, max packet len can not be > 0x400 */
 553         maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
 554                                                 usb_pipeout(qtd->urb->pipe));
 555         multi =  1 + ((maxpacket >> 11) & 0x3);
 556         maxpacket &= 0x7ff;
 557
 558         /* DW0 */
 559         ptd->dw0 = DW0_VALID_BIT;
 560         ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
 561         ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
 562         ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
 563
 564         /* DW1 */
 565         ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
 566         ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
 567         ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
 568
 569         if (usb_pipebulk(qtd->urb->pipe))
 570                 ptd->dw1 |= DW1_TRANS_BULK;
 571         else if  (usb_pipeint(qtd->urb->pipe))
 572                 ptd->dw1 |= DW1_TRANS_INT;
 573
 574         if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
 575                 /* split transaction */
 576
 577                 ptd->dw1 |= DW1_TRANS_SPLIT;
 578                 if (qtd->urb->dev->speed == USB_SPEED_LOW)
 579                         ptd->dw1 |= DW1_SE_USB_LOSPEED;
 580
 581                 ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
 582                 ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
 583
 584                 /* SE bit for Split INT transfers */
 585                 if (usb_pipeint(qtd->urb->pipe) &&
 586                                 (qtd->urb->dev->speed == USB_SPEED_LOW))
 587                         ptd->dw1 |= 2 << 16;
 588
 589                 rl = 0;
 590                 nak = 0;
 591         } else {
 592                 ptd->dw0 |= TO_DW0_MULTI(multi);
 593                 if (usb_pipecontrol(qtd->urb->pipe) ||
 594                                                 usb_pipebulk(qtd->urb->pipe))
 595                         ptd->dw3 |= TO_DW3_PING(qh->ping);
 596         }
 597         /* DW2 */
 598         ptd->dw2 = 0;
 599         ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
 600         ptd->dw2 |= TO_DW2_RL(rl);
 601
 602         /* DW3 */
 603         ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
 604         ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
 605         if (usb_pipecontrol(qtd->urb->pipe)) {
 606                 if (qtd->data_buffer == qtd->urb->setup_packet)
 607                         ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
 608                 else if (last_qtd_of_urb(qtd, qh))
 609                         ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
 610         }
 611
 612         ptd->dw3 |= DW3_ACTIVE_BIT;
 613         /* Cerr */
 614         ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
 615 }
 616
 617 static void transform_add_int(struct isp1760_qh *qh,
 618                         struct isp1760_qtd *qtd, struct ptd *ptd)
 619 {
 620         u32 usof;
 621         u32 period;
 622
 623         /*
 624          * Most of this is guessing. ISP1761 datasheet is quite unclear, and
 625          * the algorithm from the original Philips driver code, which was
 626          * pretty much used in this driver before as well, is quite horrendous
 627          * and, i believe, incorrect. The code below follows the datasheet and
 628          * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
 629          * more reliable this way (fingers crossed...).
 630          */
 631
 632         if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
 633                 /* urb->interval is in units of microframes (1/8 ms) */
 634                 period = qtd->urb->interval >> 3;
 635
 636                 if (qtd->urb->interval > 4)
 637                         usof = 0x01; /* One bit set =>
 638                                                 interval 1 ms * uFrame-match */
 639                 else if (qtd->urb->interval > 2)
 640                         usof = 0x22; /* Two bits set => interval 1/2 ms */
 641                 else if (qtd->urb->interval > 1)
 642                         usof = 0x55; /* Four bits set => interval 1/4 ms */
 643                 else
 644                         usof = 0xff; /* All bits set => interval 1/8 ms */
 645         } else {
 646                 /* urb->interval is in units of frames (1 ms) */
 647                 period = qtd->urb->interval;
 648                 usof = 0x0f;            /* Execute Start Split on any of the
 649                                            four first uFrames */
 650
 651                 /*
 652                  * First 8 bits in dw5 is uSCS and "specifies which uSOF the
 653                  * complete split needs to be sent. Valid only for IN." Also,
 654                  * "All bits can be set to one for every transfer." (p 82,
 655                  * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
 656                  * that number come from? 0xff seems to work fine...
 657                  */
 658                 /* ptd->dw5 = 0x1c; */
 659                 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
 660         }
 661
 662         period = period >> 1;/* Ensure equal or shorter period than requested */
 663         period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
 664
 665         ptd->dw2 |= period;
 666         ptd->dw4 = usof;
 667 }
 668
 669 static void create_ptd_int(struct isp1760_qh *qh,
 670                         struct isp1760_qtd *qtd, struct ptd *ptd)
 671 {
 672         create_ptd_atl(qh, qtd, ptd);
 673         transform_add_int(qh, qtd, ptd);
 674 }
 675
 676 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
 677 __releases(priv->lock)
 678 __acquires(priv->lock)
 679 {
 680         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 681
 682         if (!urb->unlinked) {
 683                 if (urb->status == -EINPROGRESS)
 684                         urb->status = 0;
 685         }
 686
 687         if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
 688                 void *ptr;
 689                 for (ptr = urb->transfer_buffer;
 690                      ptr < urb->transfer_buffer + urb->transfer_buffer_length;
 691                      ptr += PAGE_SIZE)
 692                         flush_dcache_page(virt_to_page(ptr));
 693         }
 694
 695         /* complete() can reenter this HCD */
 696         usb_hcd_unlink_urb_from_ep(hcd, urb);
 697         spin_unlock(&priv->lock);
 698         usb_hcd_giveback_urb(hcd, urb, urb->status);
 699         spin_lock(&priv->lock);
 700 }
 701
 702 static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
 703                                                                 u8 packet_type)
 704 {
 705         struct isp1760_qtd *qtd;
 706
 707         qtd = kmem_cache_zalloc(qtd_cachep, flags);
 708         if (!qtd)
 709                 return NULL;
 710
 711         INIT_LIST_HEAD(&qtd->qtd_list);
 712         qtd->urb = urb;
 713         qtd->packet_type = packet_type;
 714         qtd->status = QTD_ENQUEUED;
 715         qtd->actual_length = 0;
 716
 717         return qtd;
 718 }
 719
 720 static void qtd_free(struct isp1760_qtd *qtd)
 721 {
 722         WARN_ON(qtd->payload_addr);
 723         kmem_cache_free(qtd_cachep, qtd);
 724 }
 725
 726 static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
 727                                 struct slotinfo *slots, struct isp1760_qtd *qtd,
 728                                 struct isp1760_qh *qh, struct ptd *ptd)
 729 {
 730         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 731         int skip_map;
 732
 733         WARN_ON((slot < 0) || (slot > 31));
 734         WARN_ON(qtd->length && !qtd->payload_addr);
 735         WARN_ON(slots[slot].qtd);
 736         WARN_ON(slots[slot].qh);
 737         WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
 738
 739         slots[slot].qtd = qtd;
 740         slots[slot].qh = qh;
 741         qh->slot = slot;
 742         qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since
 743                 interrupt routine may preempt and expects this value. */
 744         ptd_write(hcd->regs, ptd_offset, slot, ptd);
 745         priv->active_ptds++;
 746
 747         /* Make sure done map has not triggered from some unlinked transfer */
 748         if (ptd_offset == ATL_PTD_OFFSET) {
 749                 priv->atl_done_map |= reg_read32(hcd->regs,
 750                                                 HC_ATL_PTD_DONEMAP_REG);
 751                 priv->atl_done_map &= ~(1 << qh->slot);
 752
 753                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
 754                 skip_map &= ~(1 << qh->slot);
 755                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
 756         } else {
 757                 priv->int_done_map |= reg_read32(hcd->regs,
 758                                                 HC_INT_PTD_DONEMAP_REG);
 759                 priv->int_done_map &= ~(1 << qh->slot);
 760
 761                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
 762                 skip_map &= ~(1 << qh->slot);
 763                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
 764         }
 765 }
 766
 767 static int is_short_bulk(struct isp1760_qtd *qtd)
 768 {
 769         return (usb_pipebulk(qtd->urb->pipe) &&
 770                                         (qtd->actual_length < qtd->length));
 771 }
 772
 773 static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
 774                                                 struct list_head *urb_list)
 775 {
 776         int last_qtd;
 777         struct isp1760_qtd *qtd, *qtd_next;
 778         struct urb_listitem *urb_listitem;
 779
 780         list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
 781                 if (qtd->status < QTD_XFER_COMPLETE)
 782                         break;
 783
 784                 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
 785                         last_qtd = 1;
 786                 else
 787                         last_qtd = qtd->urb != qtd_next->urb;
 788
 789                 if ((!last_qtd) && (qtd->status == QTD_RETIRE))
 790                         qtd_next->status = QTD_RETIRE;
 791
 792                 if (qtd->status == QTD_XFER_COMPLETE) {
 793                         if (qtd->actual_length) {
 794                                 switch (qtd->packet_type) {
 795                                 case IN_PID:
 796                                         mem_reads8(hcd->regs, qtd->payload_addr,
 797                                                         qtd->data_buffer,
 798                                                         qtd->actual_length);
 799                                         /* Fall through (?) */
 800                                 case OUT_PID:
 801                                         qtd->urb->actual_length +=
 802                                                         qtd->actual_length;
 803                                         /* Fall through ... */
 804                                 case SETUP_PID:
 805                                         break;
 806                                 }
 807                         }
 808
 809                         if (is_short_bulk(qtd)) {
 810                                 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
 811                                         qtd->urb->status = -EREMOTEIO;
 812                                 if (!last_qtd)
 813                                         qtd_next->status = QTD_RETIRE;
 814                         }
 815                 }
 816
 817                 if (qtd->payload_addr)
 818                         free_mem(hcd, qtd);
 819
 820                 if (last_qtd) {
 821                         if ((qtd->status == QTD_RETIRE) &&
 822                                         (qtd->urb->status == -EINPROGRESS))
 823                                 qtd->urb->status = -EPIPE;
 824                         /* Defer calling of urb_done() since it releases lock */
 825                         urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
 826                                                                 GFP_ATOMIC);
 827                         if (unlikely(!urb_listitem))
 828                                 break;
 829                         urb_listitem->urb = qtd->urb;
 830                         list_add_tail(&urb_listitem->urb_list, urb_list);
 831                 }
 832
 833                 list_del(&qtd->qtd_list);
 834                 qtd_free(qtd);
 835         }
 836 }
 837
 838 #define ENQUEUE_DEPTH   2
 839 static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
 840 {
 841         struct isp1760_hcd *priv = hcd_to_priv(hcd);
 842         int ptd_offset;
 843         struct slotinfo *slots;
 844         int curr_slot, free_slot;
 845         int n;
 846         struct ptd ptd;
 847         struct isp1760_qtd *qtd;
 848
 849         if (unlikely(list_empty(&qh->qtd_list))) {
 850                 WARN_ON(1);
 851                 return;
 852         }
 853
 854         if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
 855                                                         qtd_list)->urb->pipe)) {
 856                 ptd_offset = INT_PTD_OFFSET;
 857                 slots = priv->int_slots;
 858         } else {
 859                 ptd_offset = ATL_PTD_OFFSET;
 860                 slots = priv->atl_slots;
 861         }
 862
 863         free_slot = -1;
 864         for (curr_slot = 0; curr_slot < 32; curr_slot++) {
 865                 if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
 866                         free_slot = curr_slot;
 867                 if (slots[curr_slot].qh == qh)
 868                         break;
 869         }
 870
 871         n = 0;
 872         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
 873                 if (qtd->status == QTD_ENQUEUED) {
 874                         WARN_ON(qtd->payload_addr);
 875                         alloc_mem(hcd, qtd);
 876                         if ((qtd->length) && (!qtd->payload_addr))
 877                                 break;
 878
 879                         if ((qtd->length) &&
 880                             ((qtd->packet_type == SETUP_PID) ||
 881                              (qtd->packet_type == OUT_PID))) {
 882                                 mem_writes8(hcd->regs, qtd->payload_addr,
 883                                                 qtd->data_buffer, qtd->length);
 884                         }
 885
 886                         qtd->status = QTD_PAYLOAD_ALLOC;
 887                 }
 888
 889                 if (qtd->status == QTD_PAYLOAD_ALLOC) {
 890 /*
 891                         if ((curr_slot > 31) && (free_slot == -1))
 892                                 dev_dbg(hcd->self.controller, "%s: No slot "
 893                                         "available for transfer\n", __func__);
 894 */
 895                         /* Start xfer for this endpoint if not already done */
 896                         if ((curr_slot > 31) && (free_slot > -1)) {
 897                                 if (usb_pipeint(qtd->urb->pipe))
 898                                         create_ptd_int(qh, qtd, &ptd);
 899                                 else
 900                                         create_ptd_atl(qh, qtd, &ptd);
 901
 902                                 start_bus_transfer(hcd, ptd_offset, free_slot,
 903                                                         slots, qtd, qh, &ptd);
 904                                 curr_slot = free_slot;
 905                         }
 906
 907                         n++;
 908                         if (n >= ENQUEUE_DEPTH)
 909                                 break;
 910                 }
 911         }
 912 }
 913
 914 void schedule_ptds(struct usb_hcd *hcd)
 915 {
 916         struct isp1760_hcd *priv;
 917         struct isp1760_qh *qh, *qh_next;
 918         struct list_head *ep_queue;
 919         struct usb_host_endpoint *ep;
 920         LIST_HEAD(urb_list);
 921         struct urb_listitem *urb_listitem, *urb_listitem_next;
 922
 923         if (!hcd) {
 924                 WARN_ON(1);
 925                 return;
 926         }
 927
 928         priv = hcd_to_priv(hcd);
 929
 930         /*
 931          * check finished/retired xfers, transfer payloads, call urb_done()
 932          */
 933         ep_queue = &priv->interruptqhs;
 934         while (ep_queue) {
 935                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
 936                         ep = list_entry(qh->qtd_list.next, struct isp1760_qtd,
 937                                                         qtd_list)->urb->ep;
 938                         collect_qtds(hcd, qh, &urb_list);
 939                         if (list_empty(&qh->qtd_list)) {
 940                                 list_del(&qh->qh_list);
 941                                 if (ep->hcpriv == NULL) {
 942                                         /* Endpoint has been disabled, so we
 943                                         can free the associated queue head. */
 944                                         qh_free(qh);
 945                                 }
 946                         }
 947                 }
 948
 949                 if (ep_queue == &priv->interruptqhs)
 950                         ep_queue = &priv->controlqhs;
 951                 else if (ep_queue == &priv->controlqhs)
 952                         ep_queue = &priv->bulkqhs;
 953                 else
 954                         ep_queue = NULL;
 955         }
 956
 957         list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
 958                                                                 urb_list) {
 959                 isp1760_urb_done(hcd, urb_listitem->urb);
 960                 kmem_cache_free(urb_listitem_cachep, urb_listitem);
 961         }
 962
 963         /*
 964          * Schedule packets for transfer.
 965          *
 966          * According to USB2.0 specification:
 967          *
 968          * 1st prio: interrupt xfers, up to 80 % of bandwidth
 969          * 2nd prio: control xfers
 970          * 3rd prio: bulk xfers
 971          *
 972          * ... but let's use a simpler scheme here (mostly because ISP1761 doc
 973          * is very unclear on how to prioritize traffic):
 974          *
 975          * 1) Enqueue any queued control transfers, as long as payload chip mem
 976          *    and PTD ATL slots are available.
 977          * 2) Enqueue any queued INT transfers, as long as payload chip mem
 978          *    and PTD INT slots are available.
 979          * 3) Enqueue any queued bulk transfers, as long as payload chip mem
 980          *    and PTD ATL slots are available.
 981          *
 982          * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
 983          * conservation of chip mem and performance.
 984          *
 985          * I'm sure this scheme could be improved upon!
 986          */
 987         ep_queue = &priv->controlqhs;
 988         while (ep_queue) {
 989                 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
 990                         enqueue_qtds(hcd, qh);
 991
 992                 if (ep_queue == &priv->controlqhs)
 993                         ep_queue = &priv->interruptqhs;
 994                 else if (ep_queue == &priv->interruptqhs)
 995                         ep_queue = &priv->bulkqhs;
 996                 else
 997                         ep_queue = NULL;
 998         }
 999 }
1000
1001 #define PTD_STATE_QTD_DONE      1
1002 #define PTD_STATE_QTD_RELOAD    2
1003 #define PTD_STATE_URB_RETIRE    3
1004
1005 static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1006                                                                 struct urb *urb)
1007 {
1008         __dw dw4;
1009         int i;
1010
1011         dw4 = ptd->dw4;
1012         dw4 >>= 8;
1013
1014         /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
1015            need to handle these errors? Is it done in hardware? */
1016
1017         if (ptd->dw3 & DW3_HALT_BIT) {
1018
1019                 urb->status = -EPROTO; /* Default unknown error */
1020
1021                 for (i = 0; i < 8; i++) {
1022                         switch (dw4 & 0x7) {
1023                         case INT_UNDERRUN:
1024                                 dev_dbg(hcd->self.controller, "%s: underrun "
1025                                                 "during uFrame %d\n",
1026                                                 __func__, i);
1027                                 urb->status = -ECOMM; /* Could not write data */
1028                                 break;
1029                         case INT_EXACT:
1030                                 dev_dbg(hcd->self.controller, "%s: transaction "
1031                                                 "error during uFrame %d\n",
1032                                                 __func__, i);
1033                                 urb->status = -EPROTO; /* timeout, bad CRC, PID
1034                                                           error etc. */
1035                                 break;
1036                         case INT_BABBLE:
1037                                 dev_dbg(hcd->self.controller, "%s: babble "
1038                                                 "error during uFrame %d\n",
1039                                                 __func__, i);
1040                                 urb->status = -EOVERFLOW;
1041                                 break;
1042                         }
1043                         dw4 >>= 3;
1044                 }
1045
1046                 return PTD_STATE_URB_RETIRE;
1047         }
1048
1049         return PTD_STATE_QTD_DONE;
1050 }
1051
1052 static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
1053                                                                 struct urb *urb)
1054 {
1055         WARN_ON(!ptd);
1056         if (ptd->dw3 & DW3_HALT_BIT) {
1057                 if (ptd->dw3 & DW3_BABBLE_BIT)
1058                         urb->status = -EOVERFLOW;
1059                 else if (FROM_DW3_CERR(ptd->dw3))
1060                         urb->status = -EPIPE;  /* Stall */
1061                 else if (ptd->dw3 & DW3_ERROR_BIT)
1062                         urb->status = -EPROTO; /* XactErr */
1063                 else
1064                         urb->status = -EPROTO; /* Unknown */
1065 /*
1066                 dev_dbg(hcd->self.controller, "%s: ptd error:\n"
1067                         "        dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
1068                         "        dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
1069                         __func__,
1070                         ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
1071                         ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
1072 */
1073                 return PTD_STATE_URB_RETIRE;
1074         }
1075
1076         if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1077                 /* Transfer Error, *but* active and no HALT -> reload */
1078                 dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
1079                 return PTD_STATE_QTD_RELOAD;
1080         }
1081
1082         if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
1083                 /*
1084                  * NAKs are handled in HW by the chip. Usually if the
1085                  * device is not able to send data fast enough.
1086                  * This happens mostly on slower hardware.
1087                  */
1088                 return PTD_STATE_QTD_RELOAD;
1089         }
1090
1091         return PTD_STATE_QTD_DONE;
1092 }
1093
1094 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1095 {
1096         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1097         u32 imask;
1098         irqreturn_t irqret = IRQ_NONE;
1099         struct ptd ptd;
1100         struct isp1760_qh *qh;
1101         int slot;
1102         int state;
1103         struct slotinfo *slots;
1104         u32 ptd_offset;
1105         struct isp1760_qtd *qtd;
1106         int modified;
1107         static int last_active_ptds;
1108         int int_skip_map, atl_skip_map;
1109
1110         spin_lock(&priv->lock);
1111
1112         if (!(hcd->state & HC_STATE_RUNNING))
1113                 goto leave;
1114
1115         imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1116         if (unlikely(!imask))
1117                 goto leave;
1118         reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
1119
1120         int_skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1121         atl_skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1122         priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1123         priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1124         priv->int_done_map &= ~int_skip_map;
1125         priv->atl_done_map &= ~atl_skip_map;
1126
1127         modified = priv->int_done_map | priv->atl_done_map;
1128
1129         while (priv->int_done_map || priv->atl_done_map) {
1130                 if (priv->int_done_map) {
1131                         /* INT ptd */
1132                         slot = __ffs(priv->int_done_map);
1133                         priv->int_done_map &= ~(1 << slot);
1134                         slots = priv->int_slots;
1135                         /* This should not trigger, and could be removed if
1136                            noone have any problems with it triggering: */
1137                         if (!slots[slot].qh) {
1138                                 WARN_ON(1);
1139                                 continue;
1140                         }
1141                         ptd_offset = INT_PTD_OFFSET;
1142                         ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1143                         state = check_int_transfer(hcd, &ptd,
1144                                                         slots[slot].qtd->urb);
1145                 } else {
1146                         /* ATL ptd */
1147                         slot = __ffs(priv->atl_done_map);
1148                         priv->atl_done_map &= ~(1 << slot);
1149                         slots = priv->atl_slots;
1150                         /* This should not trigger, and could be removed if
1151                            noone have any problems with it triggering: */
1152                         if (!slots[slot].qh) {
1153                                 WARN_ON(1);
1154                                 continue;
1155                         }
1156                         ptd_offset = ATL_PTD_OFFSET;
1157                         ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1158                         state = check_atl_transfer(hcd, &ptd,
1159                                                         slots[slot].qtd->urb);
1160                 }
1161
1162                 qtd = slots[slot].qtd;
1163                 slots[slot].qtd = NULL;
1164                 qh = slots[slot].qh;
1165                 slots[slot].qh = NULL;
1166                 priv->active_ptds--;
1167                 qh->slot = -1;
1168
1169                 WARN_ON(qtd->status != QTD_XFER_STARTED);
1170
1171                 switch (state) {
1172                 case PTD_STATE_QTD_DONE:
1173                         if ((usb_pipeint(qtd->urb->pipe)) &&
1174                                        (qtd->urb->dev->speed != USB_SPEED_HIGH))
1175                                 qtd->actual_length =
1176                                        FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
1177                         else
1178                                 qtd->actual_length =
1179                                         FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
1180
1181                         qtd->status = QTD_XFER_COMPLETE;
1182                         if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
1183                                                         is_short_bulk(qtd))
1184                                 qtd = NULL;
1185                         else
1186                                 qtd = list_entry(qtd->qtd_list.next,
1187                                                         typeof(*qtd), qtd_list);
1188
1189                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1190                         qh->ping = FROM_DW3_PING(ptd.dw3);
1191                         break;
1192
1193                 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
1194                         qtd->status = QTD_PAYLOAD_ALLOC;
1195                         ptd.dw0 |= DW0_VALID_BIT;
1196                         /* RL counter = ERR counter */
1197                         ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
1198                         ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
1199                         ptd.dw3 &= ~TO_DW3_CERR(3);
1200                         ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
1201                         qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
1202                         qh->ping = FROM_DW3_PING(ptd.dw3);
1203                         break;
1204
1205                 case PTD_STATE_URB_RETIRE:
1206                         qtd->status = QTD_RETIRE;
1207                         qtd = NULL;
1208                         qh->toggle = 0;
1209                         qh->ping = 0;
1210                         break;
1211
1212                 default:
1213                         WARN_ON(1);
1214                         continue;
1215                 }
1216
1217                 if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
1218                         if (slots == priv->int_slots) {
1219                                 if (state == PTD_STATE_QTD_RELOAD)
1220                                         dev_err(hcd->self.controller,
1221                                                 "%s: PTD_STATE_QTD_RELOAD on "
1222                                                 "interrupt packet\n", __func__);
1223                                 if (state != PTD_STATE_QTD_RELOAD)
1224                                         create_ptd_int(qh, qtd, &ptd);
1225                         } else {
1226                                 if (state != PTD_STATE_QTD_RELOAD)
1227                                         create_ptd_atl(qh, qtd, &ptd);
1228                         }
1229
1230                         start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
1231                                 qh, &ptd);
1232                 }
1233         }
1234
1235         if (modified)
1236                 schedule_ptds(hcd);
1237
1238         /* ISP1760 Errata 2 explains that interrupts may be missed (or not
1239            happen?) if two USB devices are running simultaneously. Perhaps
1240            this happens when a PTD is finished during interrupt handling;
1241            enable SOF interrupts if PTDs are still scheduled when exiting this
1242            interrupt handler, just to be safe. */
1243
1244         if (priv->active_ptds != last_active_ptds) {
1245                 if (priv->active_ptds > 0)
1246                         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1247                                                 INTERRUPT_ENABLE_SOT_MASK);
1248                 else
1249                         reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1250                                                 INTERRUPT_ENABLE_MASK);
1251                 last_active_ptds = priv->active_ptds;
1252         }
1253
1254         irqret = IRQ_HANDLED;
1255 leave:
1256         spin_unlock(&priv->lock);
1257
1258         return irqret;
1259 }
1260
1261 static int isp1760_run(struct usb_hcd *hcd)
1262 {
1263         int retval;
1264         u32 temp;
1265         u32 command;
1266         u32 chipid;
1267
1268         hcd->uses_new_polling = 1;
1269
1270         hcd->state = HC_STATE_RUNNING;
1271
1272         /* Set PTD interrupt AND & OR maps */
1273         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
1274         reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
1275         reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
1276         reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
1277         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
1278         reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
1279         /* step 23 passed */
1280
1281         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
1282         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
1283
1284         command = reg_read32(hcd->regs, HC_USBCMD);
1285         command &= ~(CMD_LRESET|CMD_RESET);
1286         command |= CMD_RUN;
1287         reg_write32(hcd->regs, HC_USBCMD, command);
1288
1289         retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
1290         if (retval)
1291                 return retval;
1292
1293         /*
1294          * XXX
1295          * Spec says to write FLAG_CF as last config action, priv code grabs
1296          * the semaphore while doing so.
1297          */
1298         down_write(&ehci_cf_port_reset_rwsem);
1299         reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
1300
1301         retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
1302         up_write(&ehci_cf_port_reset_rwsem);
1303         if (retval)
1304                 return retval;
1305
1306         chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
1307         dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
1308                                         chipid & 0xffff, chipid >> 16);
1309
1310         /* PTD Register Init Part 2, Step 28 */
1311
1312         /* Setup registers controlling PTD checking */
1313         reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
1314         reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
1315         reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
1316         reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
1317         reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
1318         reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
1319         reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1320                                                 ATL_BUF_FILL | INT_BUF_FILL);
1321
1322         /* GRR this is run-once init(), being done every time the HC starts.
1323          * So long as they're part of class devices, we can't do it init()
1324          * since the class device isn't created that early.
1325          */
1326         return 0;
1327 }
1328
1329 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
1330 {
1331         qtd->data_buffer = databuffer;
1332
1333         if (len > MAX_PAYLOAD_SIZE)
1334                 len = MAX_PAYLOAD_SIZE;
1335         qtd->length = len;
1336
1337         return qtd->length;
1338 }
1339
1340 static void qtd_list_free(struct list_head *qtd_list)
1341 {
1342         struct isp1760_qtd *qtd, *qtd_next;
1343
1344         list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
1345                 list_del(&qtd->qtd_list);
1346                 qtd_free(qtd);
1347         }
1348 }
1349
1350 /*
1351  * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
1352  * Also calculate the PID type (SETUP/IN/OUT) for each packet.
1353  */
1354 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1355 static void packetize_urb(struct usb_hcd *hcd,
1356                 struct urb *urb, struct list_head *head, gfp_t flags)
1357 {
1358         struct isp1760_qtd *qtd;
1359         void *buf;
1360         int len, maxpacketsize;
1361         u8 packet_type;
1362
1363         /*
1364          * URBs map to sequences of QTDs:  one logical transaction
1365          */
1366
1367         if (!urb->transfer_buffer && urb->transfer_buffer_length) {
1368                 /* XXX This looks like usb storage / SCSI bug */
1369                 dev_err(hcd->self.controller,
1370                                 "buf is null, dma is %08lx len is %d\n",
1371                                 (long unsigned)urb->transfer_dma,
1372                                 urb->transfer_buffer_length);
1373                 WARN_ON(1);
1374         }
1375
1376         if (usb_pipein(urb->pipe))
1377                 packet_type = IN_PID;
1378         else
1379                 packet_type = OUT_PID;
1380
1381         if (usb_pipecontrol(urb->pipe)) {
1382                 qtd = qtd_alloc(flags, urb, SETUP_PID);
1383                 if (!qtd)
1384                         goto cleanup;
1385                 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
1386                 list_add_tail(&qtd->qtd_list, head);
1387
1388                 /* for zero length DATA stages, STATUS is always IN */
1389                 if (urb->transfer_buffer_length == 0)
1390                         packet_type = IN_PID;
1391         }
1392
1393         maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
1394                                                 usb_pipeout(urb->pipe)));
1395
1396         /*
1397          * buffer gets wrapped in one or more qtds;
1398          * last one may be "short" (including zero len)
1399          * and may serve as a control status ack
1400          */
1401         buf = urb->transfer_buffer;
1402         len = urb->transfer_buffer_length;
1403
1404         for (;;) {
1405                 int this_qtd_len;
1406
1407                 qtd = qtd_alloc(flags, urb, packet_type);
1408                 if (!qtd)
1409                         goto cleanup;
1410                 this_qtd_len = qtd_fill(qtd, buf, len);
1411                 list_add_tail(&qtd->qtd_list, head);
1412
1413                 len -= this_qtd_len;
1414                 buf += this_qtd_len;
1415
1416                 if (len <= 0)
1417                         break;
1418         }
1419
1420         /*
1421          * control requests may need a terminating data "status" ack;
1422          * bulk ones may need a terminating short packet (zero length).
1423          */
1424         if (urb->transfer_buffer_length != 0) {
1425                 int one_more = 0;
1426
1427                 if (usb_pipecontrol(urb->pipe)) {
1428                         one_more = 1;
1429                         if (packet_type == IN_PID)
1430                                 packet_type = OUT_PID;
1431                         else
1432                                 packet_type = IN_PID;
1433                 } else if (usb_pipebulk(urb->pipe)
1434                                 && (urb->transfer_flags & URB_ZERO_PACKET)
1435                                 && !(urb->transfer_buffer_length %
1436                                                         maxpacketsize)) {
1437                         one_more = 1;
1438                 }
1439                 if (one_more) {
1440                         qtd = qtd_alloc(flags, urb, packet_type);
1441                         if (!qtd)
1442                                 goto cleanup;
1443
1444                         /* never any data in such packets */
1445                         qtd_fill(qtd, NULL, 0);
1446                         list_add_tail(&qtd->qtd_list, head);
1447                 }
1448         }
1449
1450         return;
1451
1452 cleanup:
1453         qtd_list_free(head);
1454 }
1455
1456 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1457                 gfp_t mem_flags)
1458 {
1459         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1460         struct list_head *ep_queue;
1461         struct isp1760_qh *qh, *qhit;
1462         unsigned long spinflags;
1463         LIST_HEAD(new_qtds);
1464         int retval;
1465         int qh_in_queue;
1466
1467         switch (usb_pipetype(urb->pipe)) {
1468         case PIPE_CONTROL:
1469                 ep_queue = &priv->controlqhs;
1470                 break;
1471         case PIPE_BULK:
1472                 ep_queue = &priv->bulkqhs;
1473                 break;
1474         case PIPE_INTERRUPT:
1475                 if (urb->interval < 0)
1476                         return -EINVAL;
1477                 /* FIXME: Check bandwidth  */
1478                 ep_queue = &priv->interruptqhs;
1479                 break;
1480         case PIPE_ISOCHRONOUS:
1481                 dev_err(hcd->self.controller, "%s: isochronous USB packets "
1482                                                         "not yet supported\n",
1483                                                         __func__);
1484                 return -EPIPE;
1485         default:
1486                 dev_err(hcd->self.controller, "%s: unknown pipe type\n",
1487                                                         __func__);
1488                 return -EPIPE;
1489         }
1490
1491         if (usb_pipein(urb->pipe))
1492                 urb->actual_length = 0;
1493
1494         packetize_urb(hcd, urb, &new_qtds, mem_flags);
1495         if (list_empty(&new_qtds))
1496                 return -ENOMEM;
1497         urb->hcpriv = NULL; /* Used to signal unlink to interrupt handler */
1498
1499         retval = 0;
1500         spin_lock_irqsave(&priv->lock, spinflags);
1501
1502         if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
1503                 retval = -ESHUTDOWN;
1504                 goto out;
1505         }
1506         retval = usb_hcd_link_urb_to_ep(hcd, urb);
1507         if (retval)
1508                 goto out;
1509
1510         qh = urb->ep->hcpriv;
1511         if (qh) {
1512                 qh_in_queue = 0;
1513                 list_for_each_entry(qhit, ep_queue, qh_list) {
1514                         if (qhit == qh) {
1515                                 qh_in_queue = 1;
1516                                 break;
1517                         }
1518                 }
1519                 if (!qh_in_queue)
1520                         list_add_tail(&qh->qh_list, ep_queue);
1521         } else {
1522                 qh = qh_alloc(GFP_ATOMIC);
1523                 if (!qh) {
1524                         retval = -ENOMEM;
1525                         goto out;
1526                 }
1527                 list_add_tail(&qh->qh_list, ep_queue);
1528                 urb->ep->hcpriv = qh;
1529         }
1530
1531         list_splice_tail(&new_qtds, &qh->qtd_list);
1532         schedule_ptds(hcd);
1533
1534 out:
1535         spin_unlock_irqrestore(&priv->lock, spinflags);
1536         return retval;
1537 }
1538
1539 static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
1540                 struct isp1760_qh *qh)
1541 {
1542         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1543         int skip_map;
1544
1545         WARN_ON(qh->slot == -1);
1546
1547         /* We need to forcefully reclaim the slot since some transfers never
1548            return, e.g. interrupt transfers and NAKed bulk transfers. */
1549         if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
1550                 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1551                 skip_map |= (1 << qh->slot);
1552                 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1553                 priv->atl_slots[qh->slot].qh = NULL;
1554                 priv->atl_slots[qh->slot].qtd = NULL;
1555         } else {
1556                 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1557                 skip_map |= (1 << qh->slot);
1558                 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1559                 priv->int_slots[qh->slot].qh = NULL;
1560                 priv->int_slots[qh->slot].qtd = NULL;
1561         }
1562
1563         qh->slot = -1;
1564         priv->active_ptds--;
1565 }
1566
1567 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1568                 int status)
1569 {
1570         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1571         unsigned long spinflags;
1572         struct isp1760_qh *qh;
1573         struct isp1760_qtd *qtd;
1574         int retval = 0;
1575
1576         spin_lock_irqsave(&priv->lock, spinflags);
1577         retval = usb_hcd_check_unlink_urb(hcd, urb, status);
1578         if (retval)
1579                 goto out;
1580
1581         qh = urb->ep->hcpriv;
1582         if (!qh) {
1583                 retval = -EINVAL;
1584                 goto out;
1585         }
1586
1587         list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
1588                 if (qtd->urb == urb) {
1589                         if (qtd->status == QTD_XFER_STARTED)
1590                                 kill_transfer(hcd, urb, qh);
1591                         qtd->status = QTD_RETIRE;
1592                 }
1593
1594         urb->status = status;
1595         schedule_ptds(hcd);
1596
1597 out:
1598         spin_unlock_irqrestore(&priv->lock, spinflags);
1599         return retval;
1600 }
1601
1602 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
1603                 struct usb_host_endpoint *ep)
1604 {
1605         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1606         unsigned long spinflags;
1607         struct isp1760_qh *qh;
1608         struct isp1760_qtd *qtd;
1609
1610         spin_lock_irqsave(&priv->lock, spinflags);
1611
1612         qh = ep->hcpriv;
1613         if (!qh)
1614                 goto out;
1615
1616         list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
1617                 if (qtd->status == QTD_XFER_STARTED)
1618                         kill_transfer(hcd, qtd->urb, qh);
1619                 qtd->status = QTD_RETIRE;
1620                 qtd->urb->status = -ECONNRESET;
1621         }
1622
1623         ep->hcpriv = NULL;
1624         /* Cannot free qh here since it will be parsed by schedule_ptds() */
1625
1626         schedule_ptds(hcd);
1627
1628 out:
1629         spin_unlock_irqrestore(&priv->lock, spinflags);
1630 }
1631
1632 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1633 {
1634         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1635         u32 temp, status = 0;
1636         u32 mask;
1637         int retval = 1;
1638         unsigned long flags;
1639
1640         /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1641         if (!HC_IS_RUNNING(hcd->state))
1642                 return 0;
1643
1644         /* init status to no-changes */
1645         buf[0] = 0;
1646         mask = PORT_CSC;
1647
1648         spin_lock_irqsave(&priv->lock, flags);
1649         temp = reg_read32(hcd->regs, HC_PORTSC1);
1650
1651         if (temp & PORT_OWNER) {
1652                 if (temp & PORT_CSC) {
1653                         temp &= ~PORT_CSC;
1654                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1655                         goto done;
1656                 }
1657         }
1658
1659         /*
1660          * Return status information even for ports with OWNER set.
1661          * Otherwise khubd wouldn't see the disconnect event when a
1662          * high-speed device is switched over to the companion
1663          * controller by the user.
1664          */
1665
1666         if ((temp & mask) != 0
1667                         || ((temp & PORT_RESUME) != 0
1668                                 && time_after_eq(jiffies,
1669                                         priv->reset_done))) {
1670                 buf [0] |= 1 << (0 + 1);
1671                 status = STS_PCD;
1672         }
1673         /* FIXME autosuspend idle root hubs */
1674 done:
1675         spin_unlock_irqrestore(&priv->lock, flags);
1676         return status ? retval : 0;
1677 }
1678
1679 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1680                 struct usb_hub_descriptor *desc)
1681 {
1682         int ports = HCS_N_PORTS(priv->hcs_params);
1683         u16 temp;
1684
1685         desc->bDescriptorType = 0x29;
1686         /* priv 1.0, 2.3.9 says 20ms max */
1687         desc->bPwrOn2PwrGood = 10;
1688         desc->bHubContrCurrent = 0;
1689
1690         desc->bNbrPorts = ports;
1691         temp = 1 + (ports / 8);
1692         desc->bDescLength = 7 + 2 * temp;
1693
1694         /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1695         memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
1696         memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
1697
1698         /* per-port overcurrent reporting */
1699         temp = 0x0008;
1700         if (HCS_PPC(priv->hcs_params))
1701                 /* per-port power control */
1702                 temp |= 0x0001;
1703         else
1704                 /* no power switching */
1705                 temp |= 0x0002;
1706         desc->wHubCharacteristics = cpu_to_le16(temp);
1707 }
1708
1709 #define PORT_WAKE_BITS  (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1710
1711 static int check_reset_complete(struct usb_hcd *hcd, int index,
1712                 int port_status)
1713 {
1714         if (!(port_status & PORT_CONNECT))
1715                 return port_status;
1716
1717         /* if reset finished and it's still not enabled -- handoff */
1718         if (!(port_status & PORT_PE)) {
1719
1720                 dev_info(hcd->self.controller,
1721                                         "port %d full speed --> companion\n",
1722                                         index + 1);
1723
1724                 port_status |= PORT_OWNER;
1725                 port_status &= ~PORT_RWC_BITS;
1726                 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1727
1728         } else
1729                 dev_info(hcd->self.controller, "port %d high speed\n",
1730                                                                 index + 1);
1731
1732         return port_status;
1733 }
1734
1735 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1736                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1737 {
1738         struct isp1760_hcd *priv = hcd_to_priv(hcd);
1739         int ports = HCS_N_PORTS(priv->hcs_params);
1740         u32 temp, status;
1741         unsigned long flags;
1742         int retval = 0;
1743         unsigned selector;
1744
1745         /*
1746          * FIXME:  support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1747          * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1748          * (track current state ourselves) ... blink for diagnostics,
1749          * power, "this is the one", etc.  EHCI spec supports this.
1750          */
1751
1752         spin_lock_irqsave(&priv->lock, flags);
1753         switch (typeReq) {
1754         case ClearHubFeature:
1755                 switch (wValue) {
1756                 case C_HUB_LOCAL_POWER:
1757                 case C_HUB_OVER_CURRENT:
1758                         /* no hub-wide feature/status flags */
1759                         break;
1760                 default:
1761                         goto error;
1762                 }
1763                 break;
1764         case ClearPortFeature:
1765                 if (!wIndex || wIndex > ports)
1766                         goto error;
1767                 wIndex--;
1768                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1769
1770                 /*
1771                  * Even if OWNER is set, so the port is owned by the
1772                  * companion controller, khubd needs to be able to clear
1773                  * the port-change status bits (especially
1774                  * USB_PORT_STAT_C_CONNECTION).
1775                  */
1776
1777                 switch (wValue) {
1778                 case USB_PORT_FEAT_ENABLE:
1779                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1780                         break;
1781                 case USB_PORT_FEAT_C_ENABLE:
1782                         /* XXX error? */
1783                         break;
1784                 case USB_PORT_FEAT_SUSPEND:
1785                         if (temp & PORT_RESET)
1786                                 goto error;
1787
1788                         if (temp & PORT_SUSPEND) {
1789                                 if ((temp & PORT_PE) == 0)
1790                                         goto error;
1791                                 /* resume signaling for 20 msec */
1792                                 temp &= ~(PORT_RWC_BITS);
1793                                 reg_write32(hcd->regs, HC_PORTSC1,
1794                                                         temp | PORT_RESUME);
1795                                 priv->reset_done = jiffies +
1796                                         msecs_to_jiffies(20);
1797                         }
1798                         break;
1799                 case USB_PORT_FEAT_C_SUSPEND:
1800                         /* we auto-clear this feature */
1801                         break;
1802                 case USB_PORT_FEAT_POWER:
1803                         if (HCS_PPC(priv->hcs_params))
1804                                 reg_write32(hcd->regs, HC_PORTSC1,
1805                                                         temp & ~PORT_POWER);
1806                         break;
1807                 case USB_PORT_FEAT_C_CONNECTION:
1808                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1809                         break;
1810                 case USB_PORT_FEAT_C_OVER_CURRENT:
1811                         /* XXX error ?*/
1812                         break;
1813                 case USB_PORT_FEAT_C_RESET:
1814                         /* GetPortStatus clears reset */
1815                         break;
1816                 default:
1817                         goto error;
1818                 }
1819                 reg_read32(hcd->regs, HC_USBCMD);
1820                 break;
1821         case GetHubDescriptor:
1822                 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1823                         buf);
1824                 break;
1825         case GetHubStatus:
1826                 /* no hub-wide feature/status flags */
1827                 memset(buf, 0, 4);
1828                 break;
1829         case GetPortStatus:
1830                 if (!wIndex || wIndex > ports)
1831                         goto error;
1832                 wIndex--;
1833                 status = 0;
1834                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1835
1836                 /* wPortChange bits */
1837                 if (temp & PORT_CSC)
1838                         status |= USB_PORT_STAT_C_CONNECTION << 16;
1839
1840
1841                 /* whoever resumes must GetPortStatus to complete it!! */
1842                 if (temp & PORT_RESUME) {
1843                         dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1844
1845                         /* Remote Wakeup received? */
1846                         if (!priv->reset_done) {
1847                                 /* resume signaling for 20 msec */
1848                                 priv->reset_done = jiffies
1849                                                 + msecs_to_jiffies(20);
1850                                 /* check the port again */
1851                                 mod_timer(&hcd->rh_timer, priv->reset_done);
1852                         }
1853
1854                         /* resume completed? */
1855                         else if (time_after_eq(jiffies,
1856                                         priv->reset_done)) {
1857                                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1858                                 priv->reset_done = 0;
1859
1860                                 /* stop resume signaling */
1861                                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1862                                 reg_write32(hcd->regs, HC_PORTSC1,
1863                                         temp & ~(PORT_RWC_BITS | PORT_RESUME));
1864                                 retval = handshake(hcd, HC_PORTSC1,
1865                                            PORT_RESUME, 0, 2000 /* 2msec */);
1866                                 if (retval != 0) {
1867                                         dev_err(hcd->self.controller,
1868                                                 "port %d resume error %d\n",
1869                                                 wIndex + 1, retval);
1870                                         goto error;
1871                                 }
1872                                 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1873                         }
1874                 }
1875
1876                 /* whoever resets must GetPortStatus to complete it!! */
1877                 if ((temp & PORT_RESET)
1878                                 && time_after_eq(jiffies,
1879                                         priv->reset_done)) {
1880                         status |= USB_PORT_STAT_C_RESET << 16;
1881                         priv->reset_done = 0;
1882
1883                         /* force reset to complete */
1884                         reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1885                         /* REVISIT:  some hardware needs 550+ usec to clear
1886                          * this bit; seems too long to spin routinely...
1887                          */
1888                         retval = handshake(hcd, HC_PORTSC1,
1889                                         PORT_RESET, 0, 750);
1890                         if (retval != 0) {
1891                                 dev_err(hcd->self.controller, "port %d reset error %d\n",
1892                                                 wIndex + 1, retval);
1893                                 goto error;
1894                         }
1895
1896                         /* see what we found out */
1897                         temp = check_reset_complete(hcd, wIndex,
1898                                         reg_read32(hcd->regs, HC_PORTSC1));
1899                 }
1900                 /*
1901                  * Even if OWNER is set, there's no harm letting khubd
1902                  * see the wPortStatus values (they should all be 0 except
1903                  * for PORT_POWER anyway).
1904                  */
1905
1906                 if (temp & PORT_OWNER)
1907                         dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1908
1909                 if (temp & PORT_CONNECT) {
1910                         status |= USB_PORT_STAT_CONNECTION;
1911                         /* status may be from integrated TT */
1912                         status |= USB_PORT_STAT_HIGH_SPEED;
1913                 }
1914                 if (temp & PORT_PE)
1915                         status |= USB_PORT_STAT_ENABLE;
1916                 if (temp & (PORT_SUSPEND|PORT_RESUME))
1917                         status |= USB_PORT_STAT_SUSPEND;
1918                 if (temp & PORT_RESET)
1919                         status |= USB_PORT_STAT_RESET;
1920                 if (temp & PORT_POWER)
1921                         status |= USB_PORT_STAT_POWER;
1922
1923                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1924                 break;
1925         case SetHubFeature:
1926                 switch (wValue) {
1927                 case C_HUB_LOCAL_POWER:
1928                 case C_HUB_OVER_CURRENT:
1929                         /* no hub-wide feature/status flags */
1930                         break;
1931                 default:
1932                         goto error;
1933                 }
1934                 break;
1935         case SetPortFeature:
1936                 selector = wIndex >> 8;
1937                 wIndex &= 0xff;
1938                 if (!wIndex || wIndex > ports)
1939                         goto error;
1940                 wIndex--;
1941                 temp = reg_read32(hcd->regs, HC_PORTSC1);
1942                 if (temp & PORT_OWNER)
1943                         break;
1944
1945 /*              temp &= ~PORT_RWC_BITS; */
1946                 switch (wValue) {
1947                 case USB_PORT_FEAT_ENABLE:
1948                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
1949                         break;
1950
1951                 case USB_PORT_FEAT_SUSPEND:
1952                         if ((temp & PORT_PE) == 0
1953                                         || (temp & PORT_RESET) != 0)
1954                                 goto error;
1955
1956                         reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
1957                         break;
1958                 case USB_PORT_FEAT_POWER:
1959                         if (HCS_PPC(priv->hcs_params))
1960                                 reg_write32(hcd->regs, HC_PORTSC1,
1961                                                         temp | PORT_POWER);
1962                         break;
1963                 case USB_PORT_FEAT_RESET:
1964                         if (temp & PORT_RESUME)
1965                                 goto error;
1966                         /* line status bits may report this as low speed,
1967                          * which can be fine if this root hub has a
1968                          * transaction translator built in.
1969                          */
1970                         if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
1971                                         && PORT_USB11(temp)) {
1972                                 temp |= PORT_OWNER;
1973                         } else {
1974                                 temp |= PORT_RESET;
1975                                 temp &= ~PORT_PE;
1976
1977                                 /*
1978                                  * caller must wait, then call GetPortStatus
1979                                  * usb 2.0 spec says 50 ms resets on root
1980                                  */
1981                                 priv->reset_done = jiffies +
1982                                         msecs_to_jiffies(50);
1983                         }
1984                         reg_write32(hcd->regs, HC_PORTSC1, temp);
1985                         break;
1986                 default:
1987                         goto error;
1988                 }
1989                 reg_read32(hcd->regs, HC_USBCMD);
1990                 break;
1991
1992         default:
1993 error:
1994                 /* "stall" on error */
1995                 retval = -EPIPE;
1996         }
1997         spin_unlock_irqrestore(&priv->lock, flags);
1998         return retval;
1999 }
2000
2001 static int isp1760_get_frame(struct usb_hcd *hcd)
2002 {
2003         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2004         u32 fr;
2005
2006         fr = reg_read32(hcd->regs, HC_FRINDEX);
2007         return (fr >> 3) % priv->periodic_size;
2008 }
2009
2010 static void isp1760_stop(struct usb_hcd *hcd)
2011 {
2012         struct isp1760_hcd *priv = hcd_to_priv(hcd);
2013         u32 temp;
2014
2015         isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2016                         NULL, 0);
2017         mdelay(20);
2018
2019         spin_lock_irq(&priv->lock);
2020         ehci_reset(hcd);
2021         /* Disable IRQ */
2022         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2023         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2024         spin_unlock_irq(&priv->lock);
2025
2026         reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2027 }
2028
2029 static void isp1760_shutdown(struct usb_hcd *hcd)
2030 {
2031         u32 command, temp;
2032
2033         isp1760_stop(hcd);
2034         temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2035         reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2036
2037         command = reg_read32(hcd->regs, HC_USBCMD);
2038         command &= ~CMD_RUN;
2039         reg_write32(hcd->regs, HC_USBCMD, command);
2040 }
2041
2042 static const struct hc_driver isp1760_hc_driver = {
2043         .description            = "isp1760-hcd",
2044         .product_desc           = "NXP ISP1760 USB Host Controller",
2045         .hcd_priv_size          = sizeof(struct isp1760_hcd),
2046         .irq                    = isp1760_irq,
2047         .flags                  = HCD_MEMORY | HCD_USB2,
2048         .reset                  = isp1760_hc_setup,
2049         .start                  = isp1760_run,
2050         .stop                   = isp1760_stop,
2051         .shutdown               = isp1760_shutdown,
2052         .urb_enqueue            = isp1760_urb_enqueue,
2053         .urb_dequeue            = isp1760_urb_dequeue,
2054         .endpoint_disable       = isp1760_endpoint_disable,
2055         .get_frame_number       = isp1760_get_frame,
2056         .hub_status_data        = isp1760_hub_status_data,
2057         .hub_control            = isp1760_hub_control,
2058 };
2059
2060 int __init init_kmem_once(void)
2061 {
2062         urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem",
2063                         sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
2064                         SLAB_MEM_SPREAD, NULL);
2065
2066         if (!urb_listitem_cachep)
2067                 return -ENOMEM;
2068
2069         qtd_cachep = kmem_cache_create("isp1760_qtd",
2070                         sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2071                         SLAB_MEM_SPREAD, NULL);
2072
2073         if (!qtd_cachep)
2074                 return -ENOMEM;
2075
2076         qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2077                         0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2078
2079         if (!qh_cachep) {
2080                 kmem_cache_destroy(qtd_cachep);
2081                 return -ENOMEM;
2082         }
2083
2084         return 0;
2085 }
2086
2087 void deinit_kmem_cache(void)
2088 {
2089         kmem_cache_destroy(qtd_cachep);
2090         kmem_cache_destroy(qh_cachep);
2091         kmem_cache_destroy(urb_listitem_cachep);
2092 }
2093
2094 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2095                                  int irq, unsigned long irqflags,
2096                                  struct device *dev, const char *busname,
2097                                  unsigned int devflags)
2098 {
2099         struct usb_hcd *hcd;
2100         struct isp1760_hcd *priv;
2101         int ret;
2102
2103         if (usb_disabled())
2104                 return ERR_PTR(-ENODEV);
2105
2106         /* prevent usb-core allocating DMA pages */
2107         dev->dma_mask = NULL;
2108
2109         hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2110         if (!hcd)
2111                 return ERR_PTR(-ENOMEM);
2112
2113         priv = hcd_to_priv(hcd);
2114         priv->devflags = devflags;
2115         init_memory(priv);
2116         hcd->regs = ioremap(res_start, res_len);
2117         if (!hcd->regs) {
2118                 ret = -EIO;
2119                 goto err_put;
2120         }
2121
2122         hcd->irq = irq;
2123         hcd->rsrc_start = res_start;
2124         hcd->rsrc_len = res_len;
2125
2126         ret = usb_add_hcd(hcd, irq, irqflags);
2127         if (ret)
2128                 goto err_unmap;
2129
2130         return hcd;
2131
2132 err_unmap:
2133          iounmap(hcd->regs);
2134
2135 err_put:
2136          usb_put_hcd(hcd);
2137
2138          return ERR_PTR(ret);
2139 }
2140
2141 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2142 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2143 MODULE_LICENSE("GPL v2");