drivers/ntb/ntb_hw.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  *   redistributing this file, you may do so under either license.
   4  *
   5  *   GPL LICENSE SUMMARY
   6  *
   7  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify
  10  *   it under the terms of version 2 of the GNU General Public License as
  11  *   published by the Free Software Foundation.
  12  *
  13  *   BSD LICENSE
  14  *
  15  *   Copyright(c) 2012 Intel Corporation. All rights reserved.
  16  *
  17  *   Redistribution and use in source and binary forms, with or without
  18  *   modification, are permitted provided that the following conditions
  19  *   are met:
  20  *
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copy
  24  *       notice, this list of conditions and the following disclaimer in
  25  *       the documentation and/or other materials provided with the
  26  *       distribution.
  27  *     * Neither the name of Intel Corporation nor the names of its
  28  *       contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  34  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  36  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  37  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  39  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  * Intel PCIe NTB Linux driver
  44  *
  45  * Contact Information:
  46  * Jon Mason <jon.mason@intel.com>
  47  */
  48 #include <linux/debugfs.h>
  49 #include <linux/delay.h>
  50 #include <linux/init.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/module.h>
  53 #include <linux/pci.h>
  54 #include <linux/random.h>
  55 #include <linux/slab.h>
  56 #include "ntb_hw.h"
  57 #include "ntb_regs.h"
  58
  59 #define NTB_NAME        "Intel(R) PCI-E Non-Transparent Bridge Driver"
  60 #define NTB_VER         "0.25"
  61
  62 MODULE_DESCRIPTION(NTB_NAME);
  63 MODULE_VERSION(NTB_VER);
  64 MODULE_LICENSE("Dual BSD/GPL");
  65 MODULE_AUTHOR("Intel Corporation");
  66
  67 static bool xeon_errata_workaround = true;
  68 module_param(xeon_errata_workaround, bool, 0644);
  69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
  70
  71 enum {
  72         NTB_CONN_TRANSPARENT = 0,
  73         NTB_CONN_B2B,
  74         NTB_CONN_RP,
  75 };
  76
  77 enum {
  78         NTB_DEV_USD = 0,
  79         NTB_DEV_DSD,
  80 };
  81
  82 enum {
  83         SNB_HW = 0,
  84         BWD_HW,
  85 };
  86
  87 static struct dentry *debugfs_dir;
  88
  89 #define BWD_LINK_RECOVERY_TIME  500
  90
  91 /* Translate memory window 0,1 to BAR 2,4 */
  92 #define MW_TO_BAR(mw)   (mw * NTB_MAX_NUM_MW + 2)
  93
  94 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl) = {
  95         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
  96         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
  97         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
  98         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
  99         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
 100         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
 101         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
 102         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
 103         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
 104         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
 105         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
 106         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
 107         {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
 108         {0}
 109 };
 110 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
 111
 112 /**
 113  * ntb_register_event_callback() - register event callback
 114  * @ndev: pointer to ntb_device instance
 115  * @func: callback function to register
 116  *
 117  * This function registers a callback for any HW driver events such as link
 118  * up/down, power management notices and etc.
 119  *
 120  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 121  */
 122 int ntb_register_event_callback(struct ntb_device *ndev,
 123                             void (*func)(void *handle, enum ntb_hw_event event))
 124 {
 125         if (ndev->event_cb)
 126                 return -EINVAL;
 127
 128         ndev->event_cb = func;
 129
 130         return 0;
 131 }
 132
 133 /**
 134  * ntb_unregister_event_callback() - unregisters the event callback
 135  * @ndev: pointer to ntb_device instance
 136  *
 137  * This function unregisters the existing callback from transport
 138  */
 139 void ntb_unregister_event_callback(struct ntb_device *ndev)
 140 {
 141         ndev->event_cb = NULL;
 142 }
 143
 144 /**
 145  * ntb_register_db_callback() - register a callback for doorbell interrupt
 146  * @ndev: pointer to ntb_device instance
 147  * @idx: doorbell index to register callback, zero based
 148  * @func: callback function to register
 149  *
 150  * This function registers a callback function for the doorbell interrupt
 151  * on the primary side. The function will unmask the doorbell as well to
 152  * allow interrupt.
 153  *
 154  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 155  */
 156 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
 157                              void *data, void (*func)(void *data, int db_num))
 158 {
 159         unsigned long mask;
 160
 161         if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
 162                 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
 163                 return -EINVAL;
 164         }
 165
 166         ndev->db_cb[idx].callback = func;
 167         ndev->db_cb[idx].data = data;
 168
 169         /* unmask interrupt */
 170         mask = readw(ndev->reg_ofs.ldb_mask);
 171         clear_bit(idx * ndev->bits_per_vector, &mask);
 172         writew(mask, ndev->reg_ofs.ldb_mask);
 173
 174         return 0;
 175 }
 176
 177 /**
 178  * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
 179  * @ndev: pointer to ntb_device instance
 180  * @idx: doorbell index to register callback, zero based
 181  *
 182  * This function unregisters a callback function for the doorbell interrupt
 183  * on the primary side. The function will also mask the said doorbell.
 184  */
 185 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
 186 {
 187         unsigned long mask;
 188
 189         if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
 190                 return;
 191
 192         mask = readw(ndev->reg_ofs.ldb_mask);
 193         set_bit(idx * ndev->bits_per_vector, &mask);
 194         writew(mask, ndev->reg_ofs.ldb_mask);
 195
 196         ndev->db_cb[idx].callback = NULL;
 197 }
 198
 199 /**
 200  * ntb_find_transport() - find the transport pointer
 201  * @transport: pointer to pci device
 202  *
 203  * Given the pci device pointer, return the transport pointer passed in when
 204  * the transport attached when it was inited.
 205  *
 206  * RETURNS: pointer to transport.
 207  */
 208 void *ntb_find_transport(struct pci_dev *pdev)
 209 {
 210         struct ntb_device *ndev = pci_get_drvdata(pdev);
 211         return ndev->ntb_transport;
 212 }
 213
 214 /**
 215  * ntb_register_transport() - Register NTB transport with NTB HW driver
 216  * @transport: transport identifier
 217  *
 218  * This function allows a transport to reserve the hardware driver for
 219  * NTB usage.
 220  *
 221  * RETURNS: pointer to ntb_device, NULL on error.
 222  */
 223 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
 224 {
 225         struct ntb_device *ndev = pci_get_drvdata(pdev);
 226
 227         if (ndev->ntb_transport)
 228                 return NULL;
 229
 230         ndev->ntb_transport = transport;
 231         return ndev;
 232 }
 233
 234 /**
 235  * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
 236  * @ndev - ntb_device of the transport to be freed
 237  *
 238  * This function unregisters the transport from the HW driver and performs any
 239  * necessary cleanups.
 240  */
 241 void ntb_unregister_transport(struct ntb_device *ndev)
 242 {
 243         int i;
 244
 245         if (!ndev->ntb_transport)
 246                 return;
 247
 248         for (i = 0; i < ndev->max_cbs; i++)
 249                 ntb_unregister_db_callback(ndev, i);
 250
 251         ntb_unregister_event_callback(ndev);
 252         ndev->ntb_transport = NULL;
 253 }
 254
 255 /**
 256  * ntb_write_local_spad() - write to the secondary scratchpad register
 257  * @ndev: pointer to ntb_device instance
 258  * @idx: index to the scratchpad register, 0 based
 259  * @val: the data value to put into the register
 260  *
 261  * This function allows writing of a 32bit value to the indexed scratchpad
 262  * register. This writes over the data mirrored to the local scratchpad register
 263  * by the remote system.
 264  *
 265  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 266  */
 267 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
 268 {
 269         if (idx >= ndev->limits.max_spads)
 270                 return -EINVAL;
 271
 272         dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
 273                 val, idx);
 274         writel(val, ndev->reg_ofs.spad_read + idx * 4);
 275
 276         return 0;
 277 }
 278
 279 /**
 280  * ntb_read_local_spad() - read from the primary scratchpad register
 281  * @ndev: pointer to ntb_device instance
 282  * @idx: index to scratchpad register, 0 based
 283  * @val: pointer to 32bit integer for storing the register value
 284  *
 285  * This function allows reading of the 32bit scratchpad register on
 286  * the primary (internal) side.  This allows the local system to read data
 287  * written and mirrored to the scratchpad register by the remote system.
 288  *
 289  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 290  */
 291 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
 292 {
 293         if (idx >= ndev->limits.max_spads)
 294                 return -EINVAL;
 295
 296         *val = readl(ndev->reg_ofs.spad_write + idx * 4);
 297         dev_dbg(&ndev->pdev->dev,
 298                 "Reading %x from local scratch pad index %d\n", *val, idx);
 299
 300         return 0;
 301 }
 302
 303 /**
 304  * ntb_write_remote_spad() - write to the secondary scratchpad register
 305  * @ndev: pointer to ntb_device instance
 306  * @idx: index to the scratchpad register, 0 based
 307  * @val: the data value to put into the register
 308  *
 309  * This function allows writing of a 32bit value to the indexed scratchpad
 310  * register. The register resides on the secondary (external) side.  This allows
 311  * the local system to write data to be mirrored to the remote systems
 312  * scratchpad register.
 313  *
 314  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 315  */
 316 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
 317 {
 318         if (idx >= ndev->limits.max_spads)
 319                 return -EINVAL;
 320
 321         dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
 322                 val, idx);
 323         writel(val, ndev->reg_ofs.spad_write + idx * 4);
 324
 325         return 0;
 326 }
 327
 328 /**
 329  * ntb_read_remote_spad() - read from the primary scratchpad register
 330  * @ndev: pointer to ntb_device instance
 331  * @idx: index to scratchpad register, 0 based
 332  * @val: pointer to 32bit integer for storing the register value
 333  *
 334  * This function allows reading of the 32bit scratchpad register on
 335  * the primary (internal) side.  This alloows the local system to read the data
 336  * it wrote to be mirrored on the remote system.
 337  *
 338  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 339  */
 340 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
 341 {
 342         if (idx >= ndev->limits.max_spads)
 343                 return -EINVAL;
 344
 345         *val = readl(ndev->reg_ofs.spad_read + idx * 4);
 346         dev_dbg(&ndev->pdev->dev,
 347                 "Reading %x from remote scratch pad index %d\n", *val, idx);
 348
 349         return 0;
 350 }
 351
 352 /**
 353  * ntb_get_mw_base() - get addr for the NTB memory window
 354  * @ndev: pointer to ntb_device instance
 355  * @mw: memory window number
 356  *
 357  * This function provides the base address of the memory window specified.
 358  *
 359  * RETURNS: address, or NULL on error.
 360  */
 361 resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw)
 362 {
 363         if (mw >= ntb_max_mw(ndev))
 364                 return 0;
 365
 366         return pci_resource_start(ndev->pdev, MW_TO_BAR(mw));
 367 }
 368
 369 /**
 370  * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
 371  * @ndev: pointer to ntb_device instance
 372  * @mw: memory window number
 373  *
 374  * This function provides the base virtual address of the memory window
 375  * specified.
 376  *
 377  * RETURNS: pointer to virtual address, or NULL on error.
 378  */
 379 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
 380 {
 381         if (mw >= ntb_max_mw(ndev))
 382                 return NULL;
 383
 384         return ndev->mw[mw].vbase;
 385 }
 386
 387 /**
 388  * ntb_get_mw_size() - return size of NTB memory window
 389  * @ndev: pointer to ntb_device instance
 390  * @mw: memory window number
 391  *
 392  * This function provides the physical size of the memory window specified
 393  *
 394  * RETURNS: the size of the memory window or zero on error
 395  */
 396 u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
 397 {
 398         if (mw >= ntb_max_mw(ndev))
 399                 return 0;
 400
 401         return ndev->mw[mw].bar_sz;
 402 }
 403
 404 /**
 405  * ntb_set_mw_addr - set the memory window address
 406  * @ndev: pointer to ntb_device instance
 407  * @mw: memory window number
 408  * @addr: base address for data
 409  *
 410  * This function sets the base physical address of the memory window.  This
 411  * memory address is where data from the remote system will be transfered into
 412  * or out of depending on how the transport is configured.
 413  */
 414 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
 415 {
 416         if (mw >= ntb_max_mw(ndev))
 417                 return;
 418
 419         dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
 420                 MW_TO_BAR(mw));
 421
 422         ndev->mw[mw].phys_addr = addr;
 423
 424         switch (MW_TO_BAR(mw)) {
 425         case NTB_BAR_23:
 426                 writeq(addr, ndev->reg_ofs.bar2_xlat);
 427                 break;
 428         case NTB_BAR_45:
 429                 writeq(addr, ndev->reg_ofs.bar4_xlat);
 430                 break;
 431         }
 432 }
 433
 434 /**
 435  * ntb_ring_doorbell() - Set the doorbell on the secondary/external side
 436  * @ndev: pointer to ntb_device instance
 437  * @db: doorbell to ring
 438  *
 439  * This function allows triggering of a doorbell on the secondary/external
 440  * side that will initiate an interrupt on the remote host
 441  *
 442  * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 443  */
 444 void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int db)
 445 {
 446         dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
 447
 448         if (ndev->hw_type == BWD_HW)
 449                 writeq((u64) 1 << db, ndev->reg_ofs.rdb);
 450         else
 451                 writew(((1 << ndev->bits_per_vector) - 1) <<
 452                        (db * ndev->bits_per_vector), ndev->reg_ofs.rdb);
 453 }
 454
 455 static void bwd_recover_link(struct ntb_device *ndev)
 456 {
 457         u32 status;
 458
 459         /* Driver resets the NTB ModPhy lanes - magic! */
 460         writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
 461         writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
 462         writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
 463         writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
 464
 465         /* Driver waits 100ms to allow the NTB ModPhy to settle */
 466         msleep(100);
 467
 468         /* Clear AER Errors, write to clear */
 469         status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
 470         dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
 471         status &= PCI_ERR_COR_REP_ROLL;
 472         writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
 473
 474         /* Clear unexpected electrical idle event in LTSSM, write to clear */
 475         status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
 476         dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
 477         status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
 478         writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
 479
 480         /* Clear DeSkew Buffer error, write to clear */
 481         status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
 482         dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
 483         status |= BWD_DESKEWSTS_DBERR;
 484         writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
 485
 486         status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 487         dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
 488         status &= BWD_IBIST_ERR_OFLOW;
 489         writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 490
 491         /* Releases the NTB state machine to allow the link to retrain */
 492         status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 493         dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
 494         status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
 495         writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 496 }
 497
 498 static void ntb_link_event(struct ntb_device *ndev, int link_state)
 499 {
 500         unsigned int event;
 501
 502         if (ndev->link_status == link_state)
 503                 return;
 504
 505         if (link_state == NTB_LINK_UP) {
 506                 u16 status;
 507
 508                 dev_info(&ndev->pdev->dev, "Link Up\n");
 509                 ndev->link_status = NTB_LINK_UP;
 510                 event = NTB_EVENT_HW_LINK_UP;
 511
 512                 if (ndev->hw_type == BWD_HW ||
 513                     ndev->conn_type == NTB_CONN_TRANSPARENT)
 514                         status = readw(ndev->reg_ofs.lnk_stat);
 515                 else {
 516                         int rc = pci_read_config_word(ndev->pdev,
 517                                                       SNB_LINK_STATUS_OFFSET,
 518                                                       &status);
 519                         if (rc)
 520                                 return;
 521                 }
 522
 523                 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
 524                 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
 525                 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
 526                          ndev->link_width, ndev->link_speed);
 527         } else {
 528                 dev_info(&ndev->pdev->dev, "Link Down\n");
 529                 ndev->link_status = NTB_LINK_DOWN;
 530                 event = NTB_EVENT_HW_LINK_DOWN;
 531                 /* Don't modify link width/speed, we need it in link recovery */
 532         }
 533
 534         /* notify the upper layer if we have an event change */
 535         if (ndev->event_cb)
 536                 ndev->event_cb(ndev->ntb_transport, event);
 537 }
 538
 539 static int ntb_link_status(struct ntb_device *ndev)
 540 {
 541         int link_state;
 542
 543         if (ndev->hw_type == BWD_HW) {
 544                 u32 ntb_cntl;
 545
 546                 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
 547                 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
 548                         link_state = NTB_LINK_DOWN;
 549                 else
 550                         link_state = NTB_LINK_UP;
 551         } else {
 552                 u16 status;
 553                 int rc;
 554
 555                 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
 556                                           &status);
 557                 if (rc)
 558                         return rc;
 559
 560                 if (status & NTB_LINK_STATUS_ACTIVE)
 561                         link_state = NTB_LINK_UP;
 562                 else
 563                         link_state = NTB_LINK_DOWN;
 564         }
 565
 566         ntb_link_event(ndev, link_state);
 567
 568         return 0;
 569 }
 570
 571 static void bwd_link_recovery(struct work_struct *work)
 572 {
 573         struct ntb_device *ndev = container_of(work, struct ntb_device,
 574                                                lr_timer.work);
 575         u32 status32;
 576
 577         bwd_recover_link(ndev);
 578         /* There is a potential race between the 2 NTB devices recovering at the
 579          * same time.  If the times are the same, the link will not recover and
 580          * the driver will be stuck in this loop forever.  Add a random interval
 581          * to the recovery time to prevent this race.
 582          */
 583         msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
 584
 585         status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
 586         if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
 587                 goto retry;
 588
 589         status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
 590         if (status32 & BWD_IBIST_ERR_OFLOW)
 591                 goto retry;
 592
 593         status32 = readl(ndev->reg_ofs.lnk_cntl);
 594         if (!(status32 & BWD_CNTL_LINK_DOWN)) {
 595                 unsigned char speed, width;
 596                 u16 status16;
 597
 598                 status16 = readw(ndev->reg_ofs.lnk_stat);
 599                 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
 600                 speed = (status16 & NTB_LINK_SPEED_MASK);
 601                 if (ndev->link_width != width || ndev->link_speed != speed)
 602                         goto retry;
 603         }
 604
 605         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 606         return;
 607
 608 retry:
 609         schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
 610 }
 611
 612 /* BWD doesn't have link status interrupt, poll on that platform */
 613 static void bwd_link_poll(struct work_struct *work)
 614 {
 615         struct ntb_device *ndev = container_of(work, struct ntb_device,
 616                                                hb_timer.work);
 617         unsigned long ts = jiffies;
 618
 619         /* If we haven't gotten an interrupt in a while, check the BWD link
 620          * status bit
 621          */
 622         if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
 623                 int rc = ntb_link_status(ndev);
 624                 if (rc)
 625                         dev_err(&ndev->pdev->dev,
 626                                 "Error determining link status\n");
 627
 628                 /* Check to see if a link error is the cause of the link down */
 629                 if (ndev->link_status == NTB_LINK_DOWN) {
 630                         u32 status32 = readl(ndev->reg_base +
 631                                              BWD_LTSSMSTATEJMP_OFFSET);
 632                         if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
 633                                 schedule_delayed_work(&ndev->lr_timer, 0);
 634                                 return;
 635                         }
 636                 }
 637         }
 638
 639         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 640 }
 641
 642 static int ntb_xeon_setup(struct ntb_device *ndev)
 643 {
 644         int rc;
 645         u8 val;
 646
 647         ndev->hw_type = SNB_HW;
 648
 649         rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
 650         if (rc)
 651                 return rc;
 652
 653         if (val & SNB_PPD_DEV_TYPE)
 654                 ndev->dev_type = NTB_DEV_USD;
 655         else
 656                 ndev->dev_type = NTB_DEV_DSD;
 657
 658         switch (val & SNB_PPD_CONN_TYPE) {
 659         case NTB_CONN_B2B:
 660                 dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
 661                 ndev->conn_type = NTB_CONN_B2B;
 662                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 663                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
 664                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
 665                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
 666                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
 667                 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
 668
 669                 /* There is a Xeon hardware errata related to writes to
 670                  * SDOORBELL or B2BDOORBELL in conjunction with inbound access
 671                  * to NTB MMIO Space, which may hang the system.  To workaround
 672                  * this use the second memory window to access the interrupt and
 673                  * scratch pad registers on the remote system.
 674                  */
 675                 if (xeon_errata_workaround) {
 676                         if (!ndev->mw[1].bar_sz)
 677                                 return -EINVAL;
 678
 679                         ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
 680                         ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
 681                                                    SNB_SPAD_OFFSET;
 682                         ndev->reg_ofs.rdb = ndev->mw[1].vbase +
 683                                             SNB_PDOORBELL_OFFSET;
 684
 685                         /* Set the Limit register to 4k, the minimum size, to
 686                          * prevent an illegal access
 687                          */
 688                         writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
 689                                SNB_PBAR4LMT_OFFSET);
 690                 } else {
 691                         ndev->limits.max_mw = SNB_MAX_MW;
 692                         ndev->reg_ofs.spad_write = ndev->reg_base +
 693                                                    SNB_B2B_SPAD_OFFSET;
 694                         ndev->reg_ofs.rdb = ndev->reg_base +
 695                                             SNB_B2B_DOORBELL_OFFSET;
 696
 697                         /* Disable the Limit register, just incase it is set to
 698                          * something silly
 699                          */
 700                         writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
 701                 }
 702
 703                 /* The Xeon errata workaround requires setting SBAR Base
 704                  * addresses to known values, so that the PBAR XLAT can be
 705                  * pointed at SBAR0 of the remote system.
 706                  */
 707                 if (ndev->dev_type == NTB_DEV_USD) {
 708                         writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
 709                                SNB_PBAR2XLAT_OFFSET);
 710                         if (xeon_errata_workaround)
 711                                 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
 712                                        SNB_PBAR4XLAT_OFFSET);
 713                         else {
 714                                 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
 715                                        SNB_PBAR4XLAT_OFFSET);
 716                                 /* B2B_XLAT_OFFSET is a 64bit register, but can
 717                                  * only take 32bit writes
 718                                  */
 719                                 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
 720                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
 721                                 writel(SNB_MBAR01_DSD_ADDR >> 32,
 722                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
 723                         }
 724
 725                         writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
 726                                SNB_SBAR0BASE_OFFSET);
 727                         writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
 728                                SNB_SBAR2BASE_OFFSET);
 729                         writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
 730                                SNB_SBAR4BASE_OFFSET);
 731                 } else {
 732                         writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
 733                                SNB_PBAR2XLAT_OFFSET);
 734                         if (xeon_errata_workaround)
 735                                 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
 736                                        SNB_PBAR4XLAT_OFFSET);
 737                         else {
 738                                 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
 739                                        SNB_PBAR4XLAT_OFFSET);
 740                                 /* B2B_XLAT_OFFSET is a 64bit register, but can
 741                                  * only take 32bit writes
 742                                  */
 743                                 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
 744                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
 745                                 writel(SNB_MBAR01_USD_ADDR >> 32,
 746                                        ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
 747                         }
 748                         writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
 749                                SNB_SBAR0BASE_OFFSET);
 750                         writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
 751                                SNB_SBAR2BASE_OFFSET);
 752                         writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
 753                                SNB_SBAR4BASE_OFFSET);
 754                 }
 755                 break;
 756         case NTB_CONN_RP:
 757                 dev_info(&ndev->pdev->dev, "Conn Type = RP\n");
 758                 ndev->conn_type = NTB_CONN_RP;
 759
 760                 if (xeon_errata_workaround) {
 761                         dev_err(&ndev->pdev->dev,
 762                                 "NTB-RP disabled due to hardware errata.  To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
 763                         return -EINVAL;
 764                 }
 765
 766                 /* Scratch pads need to have exclusive access from the primary
 767                  * or secondary side.  Halve the num spads so that each side can
 768                  * have an equal amount.
 769                  */
 770                 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
 771                 /* Note: The SDOORBELL is the cause of the errata.  You REALLY
 772                  * don't want to touch it.
 773                  */
 774                 ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
 775                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 776                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
 777                 /* Offset the start of the spads to correspond to whether it is
 778                  * primary or secondary
 779                  */
 780                 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
 781                                            ndev->limits.max_spads * 4;
 782                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
 783                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
 784                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
 785                 ndev->limits.max_mw = SNB_MAX_MW;
 786                 break;
 787         case NTB_CONN_TRANSPARENT:
 788                 dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n");
 789                 ndev->conn_type = NTB_CONN_TRANSPARENT;
 790                 /* Scratch pads need to have exclusive access from the primary
 791                  * or secondary side.  Halve the num spads so that each side can
 792                  * have an equal amount.
 793                  */
 794                 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
 795                 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
 796                 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
 797                 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
 798                 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
 799                 /* Offset the start of the spads to correspond to whether it is
 800                  * primary or secondary
 801                  */
 802                 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
 803                                           ndev->limits.max_spads * 4;
 804                 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
 805                 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
 806
 807                 ndev->limits.max_mw = SNB_MAX_MW;
 808                 break;
 809         default:
 810                 /* Most likely caused by the remote NTB-RP device not being
 811                  * configured
 812                  */
 813                 dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", val);
 814                 return -EINVAL;
 815         }
 816
 817         ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
 818         ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
 819         ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
 820
 821         ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
 822         ndev->limits.msix_cnt = SNB_MSIX_CNT;
 823         ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
 824
 825         return 0;
 826 }
 827
 828 static int ntb_bwd_setup(struct ntb_device *ndev)
 829 {
 830         int rc;
 831         u32 val;
 832
 833         ndev->hw_type = BWD_HW;
 834
 835         rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
 836         if (rc)
 837                 return rc;
 838
 839         switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
 840         case NTB_CONN_B2B:
 841                 ndev->conn_type = NTB_CONN_B2B;
 842                 break;
 843         case NTB_CONN_RP:
 844         default:
 845                 dev_err(&ndev->pdev->dev, "Unsupported NTB configuration\n");
 846                 return -EINVAL;
 847         }
 848
 849         if (val & BWD_PPD_DEV_TYPE)
 850                 ndev->dev_type = NTB_DEV_DSD;
 851         else
 852                 ndev->dev_type = NTB_DEV_USD;
 853
 854         /* Initiate PCI-E link training */
 855         rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
 856                                     val | BWD_PPD_INIT_LINK);
 857         if (rc)
 858                 return rc;
 859
 860         ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
 861         ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
 862         ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
 863         ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
 864         ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
 865         ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
 866         ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
 867         ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
 868         ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
 869         ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
 870         ndev->limits.max_mw = BWD_MAX_MW;
 871         ndev->limits.max_spads = BWD_MAX_SPADS;
 872         ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
 873         ndev->limits.msix_cnt = BWD_MSIX_CNT;
 874         ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
 875
 876         /* Since bwd doesn't have a link interrupt, setup a poll timer */
 877         INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
 878         INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
 879         schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
 880
 881         return 0;
 882 }
 883
 884 static int ntb_device_setup(struct ntb_device *ndev)
 885 {
 886         int rc;
 887
 888         switch (ndev->pdev->device) {
 889         case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
 890         case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
 891         case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
 892         case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
 893         case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
 894         case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
 895         case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
 896         case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
 897         case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
 898         case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
 899         case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
 900         case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
 901                 rc = ntb_xeon_setup(ndev);
 902                 break;
 903         case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
 904                 rc = ntb_bwd_setup(ndev);
 905                 break;
 906         default:
 907                 rc = -ENODEV;
 908         }
 909
 910         if (rc)
 911                 return rc;
 912
 913         dev_info(&ndev->pdev->dev, "Device Type = %s\n",
 914                  ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
 915
 916         if (ndev->conn_type == NTB_CONN_B2B)
 917                 /* Enable Bus Master and Memory Space on the secondary side */
 918                 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
 919                        ndev->reg_ofs.spci_cmd);
 920
 921         return 0;
 922 }
 923
 924 static void ntb_device_free(struct ntb_device *ndev)
 925 {
 926         if (ndev->hw_type == BWD_HW) {
 927                 cancel_delayed_work_sync(&ndev->hb_timer);
 928                 cancel_delayed_work_sync(&ndev->lr_timer);
 929         }
 930 }
 931
 932 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
 933 {
 934         struct ntb_db_cb *db_cb = data;
 935         struct ntb_device *ndev = db_cb->ndev;
 936
 937         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
 938                 db_cb->db_num);
 939
 940         if (db_cb->callback)
 941                 db_cb->callback(db_cb->data, db_cb->db_num);
 942
 943         /* No need to check for the specific HB irq, any interrupt means
 944          * we're connected.
 945          */
 946         ndev->last_ts = jiffies;
 947
 948         writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.ldb);
 949
 950         return IRQ_HANDLED;
 951 }
 952
 953 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
 954 {
 955         struct ntb_db_cb *db_cb = data;
 956         struct ntb_device *ndev = db_cb->ndev;
 957
 958         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
 959                 db_cb->db_num);
 960
 961         if (db_cb->callback)
 962                 db_cb->callback(db_cb->data, db_cb->db_num);
 963
 964         /* On Sandybridge, there are 16 bits in the interrupt register
 965          * but only 4 vectors.  So, 5 bits are assigned to the first 3
 966          * vectors, with the 4th having a single bit for link
 967          * interrupts.
 968          */
 969         writew(((1 << ndev->bits_per_vector) - 1) <<
 970                (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.ldb);
 971
 972         return IRQ_HANDLED;
 973 }
 974
 975 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
 976 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
 977 {
 978         struct ntb_device *ndev = dev;
 979         int rc;
 980
 981         dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
 982
 983         rc = ntb_link_status(ndev);
 984         if (rc)
 985                 dev_err(&ndev->pdev->dev, "Error determining link status\n");
 986
 987         /* bit 15 is always the link bit */
 988         writew(1 << ndev->limits.max_db_bits, ndev->reg_ofs.ldb);
 989
 990         return IRQ_HANDLED;
 991 }
 992
 993 static irqreturn_t ntb_interrupt(int irq, void *dev)
 994 {
 995         struct ntb_device *ndev = dev;
 996         unsigned int i = 0;
 997
 998         if (ndev->hw_type == BWD_HW) {
 999                 u64 ldb = readq(ndev->reg_ofs.ldb);
1000
1001                 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %Lx\n", irq, ldb);
1002
1003                 while (ldb) {
1004                         i = __ffs(ldb);
1005                         ldb &= ldb - 1;
1006                         bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
1007                 }
1008         } else {
1009                 u16 ldb = readw(ndev->reg_ofs.ldb);
1010
1011                 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %x\n", irq, ldb);
1012
1013                 if (ldb & SNB_DB_HW_LINK) {
1014                         xeon_event_msix_irq(irq, dev);
1015                         ldb &= ~SNB_DB_HW_LINK;
1016                 }
1017
1018                 while (ldb) {
1019                         i = __ffs(ldb);
1020                         ldb &= ldb - 1;
1021                         xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
1022                 }
1023         }
1024
1025         return IRQ_HANDLED;
1026 }
1027
1028 static int ntb_setup_msix(struct ntb_device *ndev)
1029 {
1030         struct pci_dev *pdev = ndev->pdev;
1031         struct msix_entry *msix;
1032         int msix_entries;
1033         int rc, i, pos;
1034         u16 val;
1035
1036         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
1037         if (!pos) {
1038                 rc = -EIO;
1039                 goto err;
1040         }
1041
1042         rc = pci_read_config_word(pdev, pos + PCI_MSIX_FLAGS, &val);
1043         if (rc)
1044                 goto err;
1045
1046         msix_entries = msix_table_size(val);
1047         if (msix_entries > ndev->limits.msix_cnt) {
1048                 rc = -EINVAL;
1049                 goto err;
1050         }
1051
1052         ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
1053                                      GFP_KERNEL);
1054         if (!ndev->msix_entries) {
1055                 rc = -ENOMEM;
1056                 goto err;
1057         }
1058
1059         for (i = 0; i < msix_entries; i++)
1060                 ndev->msix_entries[i].entry = i;
1061
1062         rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1063         if (rc < 0)
1064                 goto err1;
1065         if (rc > 0) {
1066                 /* On SNB, the link interrupt is always tied to 4th vector.  If
1067                  * we can't get all 4, then we can't use MSI-X.
1068                  */
1069                 if (ndev->hw_type != BWD_HW) {
1070                         rc = -EIO;
1071                         goto err1;
1072                 }
1073
1074                 dev_warn(&pdev->dev,
1075                          "Only %d MSI-X vectors.  Limiting the number of queues to that number.\n",
1076                          rc);
1077                 msix_entries = rc;
1078         }
1079
1080         for (i = 0; i < msix_entries; i++) {
1081                 msix = &ndev->msix_entries[i];
1082                 WARN_ON(!msix->vector);
1083
1084                 /* Use the last MSI-X vector for Link status */
1085                 if (ndev->hw_type == BWD_HW) {
1086                         rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1087                                          "ntb-callback-msix", &ndev->db_cb[i]);
1088                         if (rc)
1089                                 goto err2;
1090                 } else {
1091                         if (i == msix_entries - 1) {
1092                                 rc = request_irq(msix->vector,
1093                                                  xeon_event_msix_irq, 0,
1094                                                  "ntb-event-msix", ndev);
1095                                 if (rc)
1096                                         goto err2;
1097                         } else {
1098                                 rc = request_irq(msix->vector,
1099                                                  xeon_callback_msix_irq, 0,
1100                                                  "ntb-callback-msix",
1101                                                  &ndev->db_cb[i]);
1102                                 if (rc)
1103                                         goto err2;
1104                         }
1105                 }
1106         }
1107
1108         ndev->num_msix = msix_entries;
1109         if (ndev->hw_type == BWD_HW)
1110                 ndev->max_cbs = msix_entries;
1111         else
1112                 ndev->max_cbs = msix_entries - 1;
1113
1114         return 0;
1115
1116 err2:
1117         while (--i >= 0) {
1118                 msix = &ndev->msix_entries[i];
1119                 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1120                         free_irq(msix->vector, ndev);
1121                 else
1122                         free_irq(msix->vector, &ndev->db_cb[i]);
1123         }
1124         pci_disable_msix(pdev);
1125 err1:
1126         kfree(ndev->msix_entries);
1127         dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1128 err:
1129         ndev->num_msix = 0;
1130         return rc;
1131 }
1132
1133 static int ntb_setup_msi(struct ntb_device *ndev)
1134 {
1135         struct pci_dev *pdev = ndev->pdev;
1136         int rc;
1137
1138         rc = pci_enable_msi(pdev);
1139         if (rc)
1140                 return rc;
1141
1142         rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1143         if (rc) {
1144                 pci_disable_msi(pdev);
1145                 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1146                 return rc;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int ntb_setup_intx(struct ntb_device *ndev)
1153 {
1154         struct pci_dev *pdev = ndev->pdev;
1155         int rc;
1156
1157         pci_msi_off(pdev);
1158
1159         /* Verify intx is enabled */
1160         pci_intx(pdev, 1);
1161
1162         rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1163                          ndev);
1164         if (rc)
1165                 return rc;
1166
1167         return 0;
1168 }
1169
1170 static int ntb_setup_interrupts(struct ntb_device *ndev)
1171 {
1172         int rc;
1173
1174         /* On BWD, disable all interrupts.  On SNB, disable all but Link
1175          * Interrupt.  The rest will be unmasked as callbacks are registered.
1176          */
1177         if (ndev->hw_type == BWD_HW)
1178                 writeq(~0, ndev->reg_ofs.ldb_mask);
1179         else
1180                 writew(~(1 << ndev->limits.max_db_bits),
1181                        ndev->reg_ofs.ldb_mask);
1182
1183         rc = ntb_setup_msix(ndev);
1184         if (!rc)
1185                 goto done;
1186
1187         ndev->bits_per_vector = 1;
1188         ndev->max_cbs = ndev->limits.max_db_bits;
1189
1190         rc = ntb_setup_msi(ndev);
1191         if (!rc)
1192                 goto done;
1193
1194         rc = ntb_setup_intx(ndev);
1195         if (rc) {
1196                 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1197                 return rc;
1198         }
1199
1200 done:
1201         return 0;
1202 }
1203
1204 static void ntb_free_interrupts(struct ntb_device *ndev)
1205 {
1206         struct pci_dev *pdev = ndev->pdev;
1207
1208         /* mask interrupts */
1209         if (ndev->hw_type == BWD_HW)
1210                 writeq(~0, ndev->reg_ofs.ldb_mask);
1211         else
1212                 writew(~0, ndev->reg_ofs.ldb_mask);
1213
1214         if (ndev->num_msix) {
1215                 struct msix_entry *msix;
1216                 u32 i;
1217
1218                 for (i = 0; i < ndev->num_msix; i++) {
1219                         msix = &ndev->msix_entries[i];
1220                         if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1221                                 free_irq(msix->vector, ndev);
1222                         else
1223                                 free_irq(msix->vector, &ndev->db_cb[i]);
1224                 }
1225                 pci_disable_msix(pdev);
1226         } else {
1227                 free_irq(pdev->irq, ndev);
1228
1229                 if (pci_dev_msi_enabled(pdev))
1230                         pci_disable_msi(pdev);
1231         }
1232 }
1233
1234 static int ntb_create_callbacks(struct ntb_device *ndev)
1235 {
1236         int i;
1237
1238         /* Checken-egg issue.  We won't know how many callbacks are necessary
1239          * until we see how many MSI-X vectors we get, but these pointers need
1240          * to be passed into the MSI-X register fucntion.  So, we allocate the
1241          * max, knowing that they might not all be used, to work around this.
1242          */
1243         ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1244                               sizeof(struct ntb_db_cb),
1245                               GFP_KERNEL);
1246         if (!ndev->db_cb)
1247                 return -ENOMEM;
1248
1249         for (i = 0; i < ndev->limits.max_db_bits; i++) {
1250                 ndev->db_cb[i].db_num = i;
1251                 ndev->db_cb[i].ndev = ndev;
1252         }
1253
1254         return 0;
1255 }
1256
1257 static void ntb_free_callbacks(struct ntb_device *ndev)
1258 {
1259         int i;
1260
1261         for (i = 0; i < ndev->limits.max_db_bits; i++)
1262                 ntb_unregister_db_callback(ndev, i);
1263
1264         kfree(ndev->db_cb);
1265 }
1266
1267 static void ntb_setup_debugfs(struct ntb_device *ndev)
1268 {
1269         if (!debugfs_initialized())
1270                 return;
1271
1272         if (!debugfs_dir)
1273                 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1274
1275         ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1276                                                debugfs_dir);
1277 }
1278
1279 static void ntb_free_debugfs(struct ntb_device *ndev)
1280 {
1281         debugfs_remove_recursive(ndev->debugfs_dir);
1282
1283         if (debugfs_dir && simple_empty(debugfs_dir)) {
1284                 debugfs_remove_recursive(debugfs_dir);
1285                 debugfs_dir = NULL;
1286         }
1287 }
1288
1289 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1290 {
1291         struct ntb_device *ndev;
1292         int rc, i;
1293
1294         ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1295         if (!ndev)
1296                 return -ENOMEM;
1297
1298         ndev->pdev = pdev;
1299         ndev->link_status = NTB_LINK_DOWN;
1300         pci_set_drvdata(pdev, ndev);
1301         ntb_setup_debugfs(ndev);
1302
1303         rc = pci_enable_device(pdev);
1304         if (rc)
1305                 goto err;
1306
1307         pci_set_master(ndev->pdev);
1308
1309         rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1310         if (rc)
1311                 goto err1;
1312
1313         ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1314         if (!ndev->reg_base) {
1315                 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1316                 rc = -EIO;
1317                 goto err2;
1318         }
1319
1320         for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1321                 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1322                 ndev->mw[i].vbase =
1323                     ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1324                                ndev->mw[i].bar_sz);
1325                 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1326                          (unsigned long long) ndev->mw[i].bar_sz);
1327                 if (!ndev->mw[i].vbase) {
1328                         dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1329                                  MW_TO_BAR(i));
1330                         rc = -EIO;
1331                         goto err3;
1332                 }
1333         }
1334
1335         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1336         if (rc) {
1337                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1338                 if (rc)
1339                         goto err3;
1340
1341                 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1342         }
1343
1344         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1345         if (rc) {
1346                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1347                 if (rc)
1348                         goto err3;
1349
1350                 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1351         }
1352
1353         rc = ntb_device_setup(ndev);
1354         if (rc)
1355                 goto err3;
1356
1357         rc = ntb_create_callbacks(ndev);
1358         if (rc)
1359                 goto err4;
1360
1361         rc = ntb_setup_interrupts(ndev);
1362         if (rc)
1363                 goto err5;
1364
1365         /* The scratchpad registers keep the values between rmmod/insmod,
1366          * blast them now
1367          */
1368         for (i = 0; i < ndev->limits.max_spads; i++) {
1369                 ntb_write_local_spad(ndev, i, 0);
1370                 ntb_write_remote_spad(ndev, i, 0);
1371         }
1372
1373         rc = ntb_transport_init(pdev);
1374         if (rc)
1375                 goto err6;
1376
1377         /* Let's bring the NTB link up */
1378         writel(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP,
1379                ndev->reg_ofs.lnk_cntl);
1380
1381         return 0;
1382
1383 err6:
1384         ntb_free_interrupts(ndev);
1385 err5:
1386         ntb_free_callbacks(ndev);
1387 err4:
1388         ntb_device_free(ndev);
1389 err3:
1390         for (i--; i >= 0; i--)
1391                 iounmap(ndev->mw[i].vbase);
1392         iounmap(ndev->reg_base);
1393 err2:
1394         pci_release_selected_regions(pdev, NTB_BAR_MASK);
1395 err1:
1396         pci_disable_device(pdev);
1397 err:
1398         ntb_free_debugfs(ndev);
1399         kfree(ndev);
1400
1401         dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1402         return rc;
1403 }
1404
1405 static void ntb_pci_remove(struct pci_dev *pdev)
1406 {
1407         struct ntb_device *ndev = pci_get_drvdata(pdev);
1408         int i;
1409         u32 ntb_cntl;
1410
1411         /* Bring NTB link down */
1412         ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1413         ntb_cntl |= NTB_CNTL_LINK_DISABLE;
1414         writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1415
1416         ntb_transport_free(ndev->ntb_transport);
1417
1418         ntb_free_interrupts(ndev);
1419         ntb_free_callbacks(ndev);
1420         ntb_device_free(ndev);
1421
1422         for (i = 0; i < NTB_MAX_NUM_MW; i++)
1423                 iounmap(ndev->mw[i].vbase);
1424
1425         iounmap(ndev->reg_base);
1426         pci_release_selected_regions(pdev, NTB_BAR_MASK);
1427         pci_disable_device(pdev);
1428         ntb_free_debugfs(ndev);
1429         kfree(ndev);
1430 }
1431
1432 static struct pci_driver ntb_pci_driver = {
1433         .name = KBUILD_MODNAME,
1434         .id_table = ntb_pci_tbl,
1435         .probe = ntb_pci_probe,
1436         .remove = ntb_pci_remove,
1437 };
1438 module_pci_driver(ntb_pci_driver);