drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00pci.h"
  45 #include "rt2x00soc.h"
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800pci.h"
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static int modparam_nohwcrypt = 0;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  58 {
  59         unsigned int i;
  60         u32 reg;
  61
  62         /*
  63          * SOC devices don't support MCU requests.
  64          */
  65         if (rt2x00_is_soc(rt2x00dev))
  66                 return;
  67
  68         for (i = 0; i < 200; i++) {
  69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  70
  71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  75                         break;
  76
  77                 udelay(REGISTER_BUSY_DELAY);
  78         }
  79
  80         if (i == 200)
  81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  82
  83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  85 }
  86
  87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  89 {
  90         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
  91
  92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  93
  94         iounmap(base_addr);
  95 }
  96 #else
  97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  98 {
  99 }
 100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
 101
 102 #ifdef CONFIG_PCI
 103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 104 {
 105         struct rt2x00_dev *rt2x00dev = eeprom->data;
 106         u32 reg;
 107
 108         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 109
 110         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 111         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 112         eeprom->reg_data_clock =
 113             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 114         eeprom->reg_chip_select =
 115             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 116 }
 117
 118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 119 {
 120         struct rt2x00_dev *rt2x00dev = eeprom->data;
 121         u32 reg = 0;
 122
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 126                            !!eeprom->reg_data_clock);
 127         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 128                            !!eeprom->reg_chip_select);
 129
 130         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 131 }
 132
 133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 134 {
 135         struct eeprom_93cx6 eeprom;
 136         u32 reg;
 137
 138         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 139
 140         eeprom.data = rt2x00dev;
 141         eeprom.register_read = rt2800pci_eepromregister_read;
 142         eeprom.register_write = rt2800pci_eepromregister_write;
 143         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 144         {
 145         case 0:
 146                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 147                 break;
 148         case 1:
 149                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 150                 break;
 151         default:
 152                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 153                 break;
 154         }
 155         eeprom.reg_data_in = 0;
 156         eeprom.reg_data_out = 0;
 157         eeprom.reg_data_clock = 0;
 158         eeprom.reg_chip_select = 0;
 159
 160         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 161                                EEPROM_SIZE / sizeof(u16));
 162 }
 163
 164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 165 {
 166         return rt2800_efuse_detect(rt2x00dev);
 167 }
 168
 169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 170 {
 171         rt2800_read_eeprom_efuse(rt2x00dev);
 172 }
 173 #else
 174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 175 {
 176 }
 177
 178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 179 {
 180         return 0;
 181 }
 182
 183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 184 {
 185 }
 186 #endif /* CONFIG_PCI */
 187
 188 /*
 189  * Queue handlers.
 190  */
 191 static void rt2800pci_start_queue(struct data_queue *queue)
 192 {
 193         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 194         u32 reg;
 195
 196         switch (queue->qid) {
 197         case QID_RX:
 198                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 199                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 200                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 201                 break;
 202         case QID_BEACON:
 203                 /*
 204                  * Allow beacon tasklets to be scheduled for periodic
 205                  * beacon updates.
 206                  */
 207                 tasklet_enable(&rt2x00dev->tbtt_tasklet);
 208                 tasklet_enable(&rt2x00dev->pretbtt_tasklet);
 209
 210                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 211                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 212                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 213                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 214                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 215
 216                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 217                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
 218                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
 219                 break;
 220         default:
 221                 break;
 222         };
 223 }
 224
 225 static void rt2800pci_kick_queue(struct data_queue *queue)
 226 {
 227         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 228         struct queue_entry *entry;
 229
 230         switch (queue->qid) {
 231         case QID_AC_VO:
 232         case QID_AC_VI:
 233         case QID_AC_BE:
 234         case QID_AC_BK:
 235                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 236                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
 237                 break;
 238         case QID_MGMT:
 239                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 240                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
 241                 break;
 242         default:
 243                 break;
 244         }
 245 }
 246
 247 static void rt2800pci_stop_queue(struct data_queue *queue)
 248 {
 249         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 250         u32 reg;
 251
 252         switch (queue->qid) {
 253         case QID_RX:
 254                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 255                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 256                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 257                 break;
 258         case QID_BEACON:
 259                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 260                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
 261                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
 262                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 263                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 264
 265                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 266                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
 267                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
 268
 269                 /*
 270                  * Wait for tbtt tasklets to finish.
 271                  */
 272                 tasklet_disable(&rt2x00dev->tbtt_tasklet);
 273                 tasklet_disable(&rt2x00dev->pretbtt_tasklet);
 274                 break;
 275         default:
 276                 break;
 277         }
 278 }
 279
 280 /*
 281  * Firmware functions
 282  */
 283 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 284 {
 285         return FIRMWARE_RT2860;
 286 }
 287
 288 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 289                                     const u8 *data, const size_t len)
 290 {
 291         u32 reg;
 292
 293         /*
 294          * enable Host program ram write selection
 295          */
 296         reg = 0;
 297         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 298         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 299
 300         /*
 301          * Write firmware to device.
 302          */
 303         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 304                                    data, len);
 305
 306         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 307         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 308
 309         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 310         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * Initialization functions.
 317  */
 318 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 319 {
 320         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 321         u32 word;
 322
 323         if (entry->queue->qid == QID_RX) {
 324                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 325
 326                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 327         } else {
 328                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 329
 330                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 331         }
 332 }
 333
 334 static void rt2800pci_clear_entry(struct queue_entry *entry)
 335 {
 336         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 337         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 338         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 339         u32 word;
 340
 341         if (entry->queue->qid == QID_RX) {
 342                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 343                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 344                 rt2x00_desc_write(entry_priv->desc, 0, word);
 345
 346                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 347                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 348                 rt2x00_desc_write(entry_priv->desc, 1, word);
 349
 350                 /*
 351                  * Set RX IDX in register to inform hardware that we have
 352                  * handled this entry and it is available for reuse again.
 353                  */
 354                 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
 355                                       entry->entry_idx);
 356         } else {
 357                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 358                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 359                 rt2x00_desc_write(entry_priv->desc, 1, word);
 360         }
 361 }
 362
 363 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 364 {
 365         struct queue_entry_priv_pci *entry_priv;
 366         u32 reg;
 367
 368         /*
 369          * Initialize registers.
 370          */
 371         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 372         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 373         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 374         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 375         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 376
 377         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 378         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 379         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 380         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 381         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 382
 383         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 384         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 385         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 386         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 387         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 388
 389         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 390         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 391         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 392         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 393         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 394
 395         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 396         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 397         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 398         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 399         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 400
 401         /*
 402          * Enable global DMA configuration
 403          */
 404         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 405         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 406         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 407         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 408         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 409
 410         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 411
 412         return 0;
 413 }
 414
 415 /*
 416  * Device state switch handlers.
 417  */
 418 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 419                                  enum dev_state state)
 420 {
 421         int mask = (state == STATE_RADIO_IRQ_ON);
 422         u32 reg;
 423         unsigned long flags;
 424
 425         /*
 426          * When interrupts are being enabled, the interrupt registers
 427          * should clear the register to assure a clean state.
 428          */
 429         if (state == STATE_RADIO_IRQ_ON) {
 430                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 431                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 432
 433                 /*
 434                  * Enable tasklets. The beacon related tasklets are
 435                  * enabled when the beacon queue is started.
 436                  */
 437                 tasklet_enable(&rt2x00dev->txstatus_tasklet);
 438                 tasklet_enable(&rt2x00dev->rxdone_tasklet);
 439                 tasklet_enable(&rt2x00dev->autowake_tasklet);
 440         }
 441
 442         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 443         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 444         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
 445         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
 446         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 447         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
 448         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
 449         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
 450         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
 451         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
 452         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
 453         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
 454         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
 455         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 456         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 457         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 458         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 459         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
 460         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
 461         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
 462         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 463         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 464
 465         if (state == STATE_RADIO_IRQ_OFF) {
 466                 /*
 467                  * Ensure that all tasklets are finished before
 468                  * disabling the interrupts.
 469                  */
 470                 tasklet_disable(&rt2x00dev->txstatus_tasklet);
 471                 tasklet_disable(&rt2x00dev->rxdone_tasklet);
 472                 tasklet_disable(&rt2x00dev->autowake_tasklet);
 473         }
 474 }
 475
 476 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 477 {
 478         u32 reg;
 479
 480         /*
 481          * Reset DMA indexes
 482          */
 483         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 484         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 485         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 486         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 487         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 488         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 489         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 490         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 491         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 492
 493         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 494         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 495
 496         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 497
 498         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 499         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 500         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 501         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 502
 503         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 504
 505         return 0;
 506 }
 507
 508 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 509 {
 510         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 511                      rt2800pci_init_queues(rt2x00dev)))
 512                 return -EIO;
 513
 514         return rt2800_enable_radio(rt2x00dev);
 515 }
 516
 517 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 518 {
 519         if (rt2x00_is_soc(rt2x00dev)) {
 520                 rt2800_disable_radio(rt2x00dev);
 521                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 522                 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
 523         }
 524 }
 525
 526 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 527                                enum dev_state state)
 528 {
 529         if (state == STATE_AWAKE) {
 530                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
 531                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 532         } else if (state == STATE_SLEEP) {
 533                 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff);
 534                 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff);
 535                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
 536         }
 537
 538         return 0;
 539 }
 540
 541 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 542                                       enum dev_state state)
 543 {
 544         int retval = 0;
 545
 546         switch (state) {
 547         case STATE_RADIO_ON:
 548                 /*
 549                  * Before the radio can be enabled, the device first has
 550                  * to be woken up. After that it needs a bit of time
 551                  * to be fully awake and then the radio can be enabled.
 552                  */
 553                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 554                 msleep(1);
 555                 retval = rt2800pci_enable_radio(rt2x00dev);
 556                 break;
 557         case STATE_RADIO_OFF:
 558                 /*
 559                  * After the radio has been disabled, the device should
 560                  * be put to sleep for powersaving.
 561                  */
 562                 rt2800pci_disable_radio(rt2x00dev);
 563                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 564                 break;
 565         case STATE_RADIO_IRQ_ON:
 566         case STATE_RADIO_IRQ_OFF:
 567                 rt2800pci_toggle_irq(rt2x00dev, state);
 568                 break;
 569         case STATE_DEEP_SLEEP:
 570         case STATE_SLEEP:
 571         case STATE_STANDBY:
 572         case STATE_AWAKE:
 573                 retval = rt2800pci_set_state(rt2x00dev, state);
 574                 break;
 575         default:
 576                 retval = -ENOTSUPP;
 577                 break;
 578         }
 579
 580         if (unlikely(retval))
 581                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 582                       state, retval);
 583
 584         return retval;
 585 }
 586
 587 /*
 588  * TX descriptor initialization
 589  */
 590 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 591 {
 592         return (__le32 *) entry->skb->data;
 593 }
 594
 595 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 596                                     struct txentry_desc *txdesc)
 597 {
 598         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 599         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 600         __le32 *txd = entry_priv->desc;
 601         u32 word;
 602
 603         /*
 604          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 605          * must contains a TXWI structure + 802.11 header + padding + 802.11
 606          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 607          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 608          * data. It means that LAST_SEC0 is always 0.
 609          */
 610
 611         /*
 612          * Initialize TX descriptor
 613          */
 614         rt2x00_desc_read(txd, 0, &word);
 615         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 616         rt2x00_desc_write(txd, 0, word);
 617
 618         rt2x00_desc_read(txd, 1, &word);
 619         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
 620         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 621                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 622         rt2x00_set_field32(&word, TXD_W1_BURST,
 623                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 624         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 625         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 626         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 627         rt2x00_desc_write(txd, 1, word);
 628
 629         rt2x00_desc_read(txd, 2, &word);
 630         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 631                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 632         rt2x00_desc_write(txd, 2, word);
 633
 634         rt2x00_desc_read(txd, 3, &word);
 635         rt2x00_set_field32(&word, TXD_W3_WIV,
 636                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 637         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 638         rt2x00_desc_write(txd, 3, word);
 639
 640         /*
 641          * Register descriptor details in skb frame descriptor.
 642          */
 643         skbdesc->desc = txd;
 644         skbdesc->desc_len = TXD_DESC_SIZE;
 645 }
 646
 647 /*
 648  * RX control handlers
 649  */
 650 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 651                                   struct rxdone_entry_desc *rxdesc)
 652 {
 653         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 654         __le32 *rxd = entry_priv->desc;
 655         u32 word;
 656
 657         rt2x00_desc_read(rxd, 3, &word);
 658
 659         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 660                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 661
 662         /*
 663          * Unfortunately we don't know the cipher type used during
 664          * decryption. This prevents us from correct providing
 665          * correct statistics through debugfs.
 666          */
 667         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 668
 669         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 670                 /*
 671                  * Hardware has stripped IV/EIV data from 802.11 frame during
 672                  * decryption. Unfortunately the descriptor doesn't contain
 673                  * any fields with the EIV/IV data either, so they can't
 674                  * be restored by rt2x00lib.
 675                  */
 676                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 677
 678                 /*
 679                  * The hardware has already checked the Michael Mic and has
 680                  * stripped it from the frame. Signal this to mac80211.
 681                  */
 682                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
 683
 684                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 685                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 686                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 687                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 688         }
 689
 690         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 691                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 692
 693         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 694                 rxdesc->dev_flags |= RXDONE_L2PAD;
 695
 696         /*
 697          * Process the RXWI structure that is at the start of the buffer.
 698          */
 699         rt2800_process_rxwi(entry, rxdesc);
 700 }
 701
 702 /*
 703  * Interrupt functions.
 704  */
 705 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 706 {
 707         struct ieee80211_conf conf = { .flags = 0 };
 708         struct rt2x00lib_conf libconf = { .conf = &conf };
 709
 710         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 711 }
 712
 713 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 714 {
 715         struct data_queue *queue;
 716         struct queue_entry *entry;
 717         u32 status;
 718         u8 qid;
 719
 720         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
 721                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
 722                 if (qid >= QID_RX) {
 723                         /*
 724                          * Unknown queue, this shouldn't happen. Just drop
 725                          * this tx status.
 726                          */
 727                         WARNING(rt2x00dev, "Got TX status report with "
 728                                            "unexpected pid %u, dropping\n", qid);
 729                         break;
 730                 }
 731
 732                 queue = rt2x00queue_get_queue(rt2x00dev, qid);
 733                 if (unlikely(queue == NULL)) {
 734                         /*
 735                          * The queue is NULL, this shouldn't happen. Stop
 736                          * processing here and drop the tx status
 737                          */
 738                         WARNING(rt2x00dev, "Got TX status for an unavailable "
 739                                            "queue %u, dropping\n", qid);
 740                         break;
 741                 }
 742
 743                 if (rt2x00queue_empty(queue)) {
 744                         /*
 745                          * The queue is empty. Stop processing here
 746                          * and drop the tx status.
 747                          */
 748                         WARNING(rt2x00dev, "Got TX status for an empty "
 749                                            "queue %u, dropping\n", qid);
 750                         break;
 751                 }
 752
 753                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 754                 rt2800_txdone_entry(entry, status);
 755         }
 756 }
 757
 758 static void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
 759                                        struct rt2x00_field32 irq_field)
 760 {
 761         unsigned long flags;
 762         u32 reg;
 763
 764         /*
 765          * Enable a single interrupt. The interrupt mask register
 766          * access needs locking.
 767          */
 768         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 769         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 770         rt2x00_set_field32(&reg, irq_field, 1);
 771         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 772         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 773 }
 774
 775 static void rt2800pci_txstatus_tasklet(unsigned long data)
 776 {
 777         rt2800pci_txdone((struct rt2x00_dev *)data);
 778
 779         /*
 780          * No need to enable the tx status interrupt here as we always
 781          * leave it enabled to minimize the possibility of a tx status
 782          * register overflow. See comment in interrupt handler.
 783          */
 784 }
 785
 786 static void rt2800pci_pretbtt_tasklet(unsigned long data)
 787 {
 788         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 789         rt2x00lib_pretbtt(rt2x00dev);
 790         rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
 791 }
 792
 793 static void rt2800pci_tbtt_tasklet(unsigned long data)
 794 {
 795         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 796         rt2x00lib_beacondone(rt2x00dev);
 797         rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
 798 }
 799
 800 static void rt2800pci_rxdone_tasklet(unsigned long data)
 801 {
 802         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 803         rt2x00pci_rxdone(rt2x00dev);
 804         rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
 805 }
 806
 807 static void rt2800pci_autowake_tasklet(unsigned long data)
 808 {
 809         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 810         rt2800pci_wakeup(rt2x00dev);
 811         rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
 812 }
 813
 814 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
 815 {
 816         u32 status;
 817         int i;
 818
 819         /*
 820          * The TX_FIFO_STATUS interrupt needs special care. We should
 821          * read TX_STA_FIFO but we should do it immediately as otherwise
 822          * the register can overflow and we would lose status reports.
 823          *
 824          * Hence, read the TX_STA_FIFO register and copy all tx status
 825          * reports into a kernel FIFO which is handled in the txstatus
 826          * tasklet. We use a tasklet to process the tx status reports
 827          * because we can schedule the tasklet multiple times (when the
 828          * interrupt fires again during tx status processing).
 829          *
 830          * Furthermore we don't disable the TX_FIFO_STATUS
 831          * interrupt here but leave it enabled so that the TX_STA_FIFO
 832          * can also be read while the interrupt thread gets executed.
 833          *
 834          * Since we have only one producer and one consumer we don't
 835          * need to lock the kfifo.
 836          */
 837         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 838                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
 839
 840                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
 841                         break;
 842
 843                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
 844                         WARNING(rt2x00dev, "TX status FIFO overrun,"
 845                                 "drop tx status report.\n");
 846                         break;
 847                 }
 848         }
 849
 850         /* Schedule the tasklet for processing the tx status. */
 851         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 852 }
 853
 854 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 855 {
 856         struct rt2x00_dev *rt2x00dev = dev_instance;
 857         u32 reg, mask;
 858         unsigned long flags;
 859
 860         /* Read status and ACK all interrupts */
 861         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 862         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 863
 864         if (!reg)
 865                 return IRQ_NONE;
 866
 867         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 868                 return IRQ_HANDLED;
 869
 870         /*
 871          * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
 872          * for interrupts and interrupt masks we can just use the value of
 873          * INT_SOURCE_CSR to create the interrupt mask.
 874          */
 875         mask = ~reg;
 876
 877         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
 878                 rt2800pci_txstatus_interrupt(rt2x00dev);
 879                 /*
 880                  * Never disable the TX_FIFO_STATUS interrupt.
 881                  */
 882                 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 883         }
 884
 885         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 886                 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
 887
 888         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 889                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
 890
 891         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 892                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 893
 894         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 895                 tasklet_schedule(&rt2x00dev->autowake_tasklet);
 896
 897         /*
 898          * Disable all interrupts for which a tasklet was scheduled right now,
 899          * the tasklet will reenable the appropriate interrupts.
 900          */
 901         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 902         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 903         reg &= mask;
 904         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 905         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 906
 907         return IRQ_HANDLED;
 908 }
 909
 910 /*
 911  * Device probe functions.
 912  */
 913 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 914 {
 915         /*
 916          * Read EEPROM into buffer
 917          */
 918         if (rt2x00_is_soc(rt2x00dev))
 919                 rt2800pci_read_eeprom_soc(rt2x00dev);
 920         else if (rt2800pci_efuse_detect(rt2x00dev))
 921                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 922         else
 923                 rt2800pci_read_eeprom_pci(rt2x00dev);
 924
 925         return rt2800_validate_eeprom(rt2x00dev);
 926 }
 927
 928 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
 929 {
 930         int retval;
 931
 932         /*
 933          * Allocate eeprom data.
 934          */
 935         retval = rt2800pci_validate_eeprom(rt2x00dev);
 936         if (retval)
 937                 return retval;
 938
 939         retval = rt2800_init_eeprom(rt2x00dev);
 940         if (retval)
 941                 return retval;
 942
 943         /*
 944          * Initialize hw specifications.
 945          */
 946         retval = rt2800_probe_hw_mode(rt2x00dev);
 947         if (retval)
 948                 return retval;
 949
 950         /*
 951          * This device has multiple filters for control frames
 952          * and has a separate filter for PS Poll frames.
 953          */
 954         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
 955         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
 956
 957         /*
 958          * This device has a pre tbtt interrupt and thus fetches
 959          * a new beacon directly prior to transmission.
 960          */
 961         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
 962
 963         /*
 964          * This device requires firmware.
 965          */
 966         if (!rt2x00_is_soc(rt2x00dev))
 967                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
 968         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
 969         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
 970         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
 971         __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
 972         if (!modparam_nohwcrypt)
 973                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 974         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
 975
 976         /*
 977          * Set the rssi offset.
 978          */
 979         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
 980
 981         return 0;
 982 }
 983
 984 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
 985         .tx                     = rt2x00mac_tx,
 986         .start                  = rt2x00mac_start,
 987         .stop                   = rt2x00mac_stop,
 988         .add_interface          = rt2x00mac_add_interface,
 989         .remove_interface       = rt2x00mac_remove_interface,
 990         .config                 = rt2x00mac_config,
 991         .configure_filter       = rt2x00mac_configure_filter,
 992         .set_key                = rt2x00mac_set_key,
 993         .sw_scan_start          = rt2x00mac_sw_scan_start,
 994         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
 995         .get_stats              = rt2x00mac_get_stats,
 996         .get_tkip_seq           = rt2800_get_tkip_seq,
 997         .set_rts_threshold      = rt2800_set_rts_threshold,
 998         .bss_info_changed       = rt2x00mac_bss_info_changed,
 999         .conf_tx                = rt2800_conf_tx,
1000         .get_tsf                = rt2800_get_tsf,
1001         .rfkill_poll            = rt2x00mac_rfkill_poll,
1002         .ampdu_action           = rt2800_ampdu_action,
1003         .flush                  = rt2x00mac_flush,
1004         .get_survey             = rt2800_get_survey,
1005 };
1006
1007 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1008         .register_read          = rt2x00pci_register_read,
1009         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1010         .register_write         = rt2x00pci_register_write,
1011         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1012         .register_multiread     = rt2x00pci_register_multiread,
1013         .register_multiwrite    = rt2x00pci_register_multiwrite,
1014         .regbusy_read           = rt2x00pci_regbusy_read,
1015         .drv_write_firmware     = rt2800pci_write_firmware,
1016         .drv_init_registers     = rt2800pci_init_registers,
1017         .drv_get_txwi           = rt2800pci_get_txwi,
1018 };
1019
1020 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1021         .irq_handler            = rt2800pci_interrupt,
1022         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
1023         .pretbtt_tasklet        = rt2800pci_pretbtt_tasklet,
1024         .tbtt_tasklet           = rt2800pci_tbtt_tasklet,
1025         .rxdone_tasklet         = rt2800pci_rxdone_tasklet,
1026         .autowake_tasklet       = rt2800pci_autowake_tasklet,
1027         .probe_hw               = rt2800pci_probe_hw,
1028         .get_firmware_name      = rt2800pci_get_firmware_name,
1029         .check_firmware         = rt2800_check_firmware,
1030         .load_firmware          = rt2800_load_firmware,
1031         .initialize             = rt2x00pci_initialize,
1032         .uninitialize           = rt2x00pci_uninitialize,
1033         .get_entry_state        = rt2800pci_get_entry_state,
1034         .clear_entry            = rt2800pci_clear_entry,
1035         .set_device_state       = rt2800pci_set_device_state,
1036         .rfkill_poll            = rt2800_rfkill_poll,
1037         .link_stats             = rt2800_link_stats,
1038         .reset_tuner            = rt2800_reset_tuner,
1039         .link_tuner             = rt2800_link_tuner,
1040         .start_queue            = rt2800pci_start_queue,
1041         .kick_queue             = rt2800pci_kick_queue,
1042         .stop_queue             = rt2800pci_stop_queue,
1043         .write_tx_desc          = rt2800pci_write_tx_desc,
1044         .write_tx_data          = rt2800_write_tx_data,
1045         .write_beacon           = rt2800_write_beacon,
1046         .clear_beacon           = rt2800_clear_beacon,
1047         .fill_rxdone            = rt2800pci_fill_rxdone,
1048         .config_shared_key      = rt2800_config_shared_key,
1049         .config_pairwise_key    = rt2800_config_pairwise_key,
1050         .config_filter          = rt2800_config_filter,
1051         .config_intf            = rt2800_config_intf,
1052         .config_erp             = rt2800_config_erp,
1053         .config_ant             = rt2800_config_ant,
1054         .config                 = rt2800_config,
1055 };
1056
1057 static const struct data_queue_desc rt2800pci_queue_rx = {
1058         .entry_num              = 128,
1059         .data_size              = AGGREGATION_SIZE,
1060         .desc_size              = RXD_DESC_SIZE,
1061         .priv_size              = sizeof(struct queue_entry_priv_pci),
1062 };
1063
1064 static const struct data_queue_desc rt2800pci_queue_tx = {
1065         .entry_num              = 64,
1066         .data_size              = AGGREGATION_SIZE,
1067         .desc_size              = TXD_DESC_SIZE,
1068         .priv_size              = sizeof(struct queue_entry_priv_pci),
1069 };
1070
1071 static const struct data_queue_desc rt2800pci_queue_bcn = {
1072         .entry_num              = 8,
1073         .data_size              = 0, /* No DMA required for beacons */
1074         .desc_size              = TXWI_DESC_SIZE,
1075         .priv_size              = sizeof(struct queue_entry_priv_pci),
1076 };
1077
1078 static const struct rt2x00_ops rt2800pci_ops = {
1079         .name                   = KBUILD_MODNAME,
1080         .max_sta_intf           = 1,
1081         .max_ap_intf            = 8,
1082         .eeprom_size            = EEPROM_SIZE,
1083         .rf_size                = RF_SIZE,
1084         .tx_queues              = NUM_TX_QUEUES,
1085         .extra_tx_headroom      = TXWI_DESC_SIZE,
1086         .rx                     = &rt2800pci_queue_rx,
1087         .tx                     = &rt2800pci_queue_tx,
1088         .bcn                    = &rt2800pci_queue_bcn,
1089         .lib                    = &rt2800pci_rt2x00_ops,
1090         .drv                    = &rt2800pci_rt2800_ops,
1091         .hw                     = &rt2800pci_mac80211_ops,
1092 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1093         .debugfs                = &rt2800_rt2x00debug,
1094 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1095 };
1096
1097 /*
1098  * RT2800pci module information.
1099  */
1100 #ifdef CONFIG_PCI
1101 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1102         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1103         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1104         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1105         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1106         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1107         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1108         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1109         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1110         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1111         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1112         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1113         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1114         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1115         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1116         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1117         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1118 #ifdef CONFIG_RT2800PCI_RT33XX
1119         { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1120 #endif
1121 #ifdef CONFIG_RT2800PCI_RT35XX
1122         { PCI_DEVICE(0x1432, 0x7711), PCI_DEVICE_DATA(&rt2800pci_ops) },
1123         { PCI_DEVICE(0x1432, 0x7722), PCI_DEVICE_DATA(&rt2800pci_ops) },
1124         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1125         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1126         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1127         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1128         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1129 #endif
1130         { 0, }
1131 };
1132 #endif /* CONFIG_PCI */
1133
1134 MODULE_AUTHOR(DRV_PROJECT);
1135 MODULE_VERSION(DRV_VERSION);
1136 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1137 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1138 #ifdef CONFIG_PCI
1139 MODULE_FIRMWARE(FIRMWARE_RT2860);
1140 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1141 #endif /* CONFIG_PCI */
1142 MODULE_LICENSE("GPL");
1143
1144 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1145 static int rt2800soc_probe(struct platform_device *pdev)
1146 {
1147         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1148 }
1149
1150 static struct platform_driver rt2800soc_driver = {
1151         .driver         = {
1152                 .name           = "rt2800_wmac",
1153                 .owner          = THIS_MODULE,
1154                 .mod_name       = KBUILD_MODNAME,
1155         },
1156         .probe          = rt2800soc_probe,
1157         .remove         = __devexit_p(rt2x00soc_remove),
1158         .suspend        = rt2x00soc_suspend,
1159         .resume         = rt2x00soc_resume,
1160 };
1161 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1162
1163 #ifdef CONFIG_PCI
1164 static struct pci_driver rt2800pci_driver = {
1165         .name           = KBUILD_MODNAME,
1166         .id_table       = rt2800pci_device_table,
1167         .probe          = rt2x00pci_probe,
1168         .remove         = __devexit_p(rt2x00pci_remove),
1169         .suspend        = rt2x00pci_suspend,
1170         .resume         = rt2x00pci_resume,
1171 };
1172 #endif /* CONFIG_PCI */
1173
1174 static int __init rt2800pci_init(void)
1175 {
1176         int ret = 0;
1177
1178 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1179         ret = platform_driver_register(&rt2800soc_driver);
1180         if (ret)
1181                 return ret;
1182 #endif
1183 #ifdef CONFIG_PCI
1184         ret = pci_register_driver(&rt2800pci_driver);
1185         if (ret) {
1186 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1187                 platform_driver_unregister(&rt2800soc_driver);
1188 #endif
1189                 return ret;
1190         }
1191 #endif
1192
1193         return ret;
1194 }
1195
1196 static void __exit rt2800pci_exit(void)
1197 {
1198 #ifdef CONFIG_PCI
1199         pci_unregister_driver(&rt2800pci_driver);
1200 #endif
1201 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1202         platform_driver_unregister(&rt2800soc_driver);
1203 #endif
1204 }
1205
1206 module_init(rt2800pci_init);
1207 module_exit(rt2800pci_exit);