drivers/net/ethernet/amd/xgbe/xgbe-drv.c

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #include <linux/platform_device.h>
 118 #include <linux/spinlock.h>
 119 #include <linux/tcp.h>
 120 #include <linux/if_vlan.h>
 121 #include <net/busy_poll.h>
 122 #include <linux/clk.h>
 123 #include <linux/if_ether.h>
 124 #include <linux/net_tstamp.h>
 125 #include <linux/phy.h>
 126
 127 #include "xgbe.h"
 128 #include "xgbe-common.h"
 129
 130 static int xgbe_one_poll(struct napi_struct *, int);
 131 static int xgbe_all_poll(struct napi_struct *, int);
 132 static void xgbe_set_rx_mode(struct net_device *);
 133
 134 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
 135 {
 136         struct xgbe_channel *channel_mem, *channel;
 137         struct xgbe_ring *tx_ring, *rx_ring;
 138         unsigned int count, i;
 139         int ret = -ENOMEM;
 140
 141         count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
 142
 143         channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
 144         if (!channel_mem)
 145                 goto err_channel;
 146
 147         tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
 148                           GFP_KERNEL);
 149         if (!tx_ring)
 150                 goto err_tx_ring;
 151
 152         rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
 153                           GFP_KERNEL);
 154         if (!rx_ring)
 155                 goto err_rx_ring;
 156
 157         for (i = 0, channel = channel_mem; i < count; i++, channel++) {
 158                 snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
 159                 channel->pdata = pdata;
 160                 channel->queue_index = i;
 161                 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
 162                                     (DMA_CH_INC * i);
 163
 164                 if (pdata->per_channel_irq) {
 165                         /* Get the DMA interrupt (offset 1) */
 166                         ret = platform_get_irq(pdata->pdev, i + 1);
 167                         if (ret < 0) {
 168                                 netdev_err(pdata->netdev,
 169                                            "platform_get_irq %u failed\n",
 170                                            i + 1);
 171                                 goto err_irq;
 172                         }
 173
 174                         channel->dma_irq = ret;
 175                 }
 176
 177                 if (i < pdata->tx_ring_count) {
 178                         spin_lock_init(&tx_ring->lock);
 179                         channel->tx_ring = tx_ring++;
 180                 }
 181
 182                 if (i < pdata->rx_ring_count) {
 183                         spin_lock_init(&rx_ring->lock);
 184                         channel->rx_ring = rx_ring++;
 185                 }
 186
 187                 DBGPR("  %s: queue=%u, dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
 188                       channel->name, channel->queue_index, channel->dma_regs,
 189                       channel->dma_irq, channel->tx_ring, channel->rx_ring);
 190         }
 191
 192         pdata->channel = channel_mem;
 193         pdata->channel_count = count;
 194
 195         return 0;
 196
 197 err_irq:
 198         kfree(rx_ring);
 199
 200 err_rx_ring:
 201         kfree(tx_ring);
 202
 203 err_tx_ring:
 204         kfree(channel_mem);
 205
 206 err_channel:
 207         return ret;
 208 }
 209
 210 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
 211 {
 212         if (!pdata->channel)
 213                 return;
 214
 215         kfree(pdata->channel->rx_ring);
 216         kfree(pdata->channel->tx_ring);
 217         kfree(pdata->channel);
 218
 219         pdata->channel = NULL;
 220         pdata->channel_count = 0;
 221 }
 222
 223 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
 224 {
 225         return (ring->rdesc_count - (ring->cur - ring->dirty));
 226 }
 227
 228 static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
 229 {
 230         unsigned int rx_buf_size;
 231
 232         if (mtu > XGMAC_JUMBO_PACKET_MTU) {
 233                 netdev_alert(netdev, "MTU exceeds maximum supported value\n");
 234                 return -EINVAL;
 235         }
 236
 237         rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
 238         rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
 239
 240         rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
 241                       ~(XGBE_RX_BUF_ALIGN - 1);
 242
 243         return rx_buf_size;
 244 }
 245
 246 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
 247 {
 248         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 249         struct xgbe_channel *channel;
 250         enum xgbe_int int_id;
 251         unsigned int i;
 252
 253         channel = pdata->channel;
 254         for (i = 0; i < pdata->channel_count; i++, channel++) {
 255                 if (channel->tx_ring && channel->rx_ring)
 256                         int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 257                 else if (channel->tx_ring)
 258                         int_id = XGMAC_INT_DMA_CH_SR_TI;
 259                 else if (channel->rx_ring)
 260                         int_id = XGMAC_INT_DMA_CH_SR_RI;
 261                 else
 262                         continue;
 263
 264                 hw_if->enable_int(channel, int_id);
 265         }
 266 }
 267
 268 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
 269 {
 270         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 271         struct xgbe_channel *channel;
 272         enum xgbe_int int_id;
 273         unsigned int i;
 274
 275         channel = pdata->channel;
 276         for (i = 0; i < pdata->channel_count; i++, channel++) {
 277                 if (channel->tx_ring && channel->rx_ring)
 278                         int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
 279                 else if (channel->tx_ring)
 280                         int_id = XGMAC_INT_DMA_CH_SR_TI;
 281                 else if (channel->rx_ring)
 282                         int_id = XGMAC_INT_DMA_CH_SR_RI;
 283                 else
 284                         continue;
 285
 286                 hw_if->disable_int(channel, int_id);
 287         }
 288 }
 289
 290 static irqreturn_t xgbe_isr(int irq, void *data)
 291 {
 292         struct xgbe_prv_data *pdata = data;
 293         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 294         struct xgbe_channel *channel;
 295         unsigned int dma_isr, dma_ch_isr;
 296         unsigned int mac_isr, mac_tssr;
 297         unsigned int i;
 298
 299         /* The DMA interrupt status register also reports MAC and MTL
 300          * interrupts. So for polling mode, we just need to check for
 301          * this register to be non-zero
 302          */
 303         dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
 304         if (!dma_isr)
 305                 goto isr_done;
 306
 307         DBGPR("  DMA_ISR = %08x\n", dma_isr);
 308
 309         for (i = 0; i < pdata->channel_count; i++) {
 310                 if (!(dma_isr & (1 << i)))
 311                         continue;
 312
 313                 channel = pdata->channel + i;
 314
 315                 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
 316                 DBGPR("  DMA_CH%u_ISR = %08x\n", i, dma_ch_isr);
 317
 318                 /* If we get a TI or RI interrupt that means per channel DMA
 319                  * interrupts are not enabled, so we use the private data napi
 320                  * structure, not the per channel napi structure
 321                  */
 322                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
 323                     XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI)) {
 324                         if (napi_schedule_prep(&pdata->napi)) {
 325                                 /* Disable Tx and Rx interrupts */
 326                                 xgbe_disable_rx_tx_ints(pdata);
 327
 328                                 /* Turn on polling */
 329                                 __napi_schedule(&pdata->napi);
 330                         }
 331                 }
 332
 333                 /* Restart the device on a Fatal Bus Error */
 334                 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
 335                         schedule_work(&pdata->restart_work);
 336
 337                 /* Clear all interrupt signals */
 338                 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
 339         }
 340
 341         if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
 342                 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
 343
 344                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
 345                         hw_if->tx_mmc_int(pdata);
 346
 347                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
 348                         hw_if->rx_mmc_int(pdata);
 349
 350                 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
 351                         mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
 352
 353                         if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
 354                                 /* Read Tx Timestamp to clear interrupt */
 355                                 pdata->tx_tstamp =
 356                                         hw_if->get_tx_tstamp(pdata);
 357                                 schedule_work(&pdata->tx_tstamp_work);
 358                         }
 359                 }
 360         }
 361
 362         DBGPR("  DMA_ISR = %08x\n", XGMAC_IOREAD(pdata, DMA_ISR));
 363
 364 isr_done:
 365         return IRQ_HANDLED;
 366 }
 367
 368 static irqreturn_t xgbe_dma_isr(int irq, void *data)
 369 {
 370         struct xgbe_channel *channel = data;
 371
 372         /* Per channel DMA interrupts are enabled, so we use the per
 373          * channel napi structure and not the private data napi structure
 374          */
 375         if (napi_schedule_prep(&channel->napi)) {
 376                 /* Disable Tx and Rx interrupts */
 377                 disable_irq(channel->dma_irq);
 378
 379                 /* Turn on polling */
 380                 __napi_schedule(&channel->napi);
 381         }
 382
 383         return IRQ_HANDLED;
 384 }
 385
 386 static enum hrtimer_restart xgbe_tx_timer(struct hrtimer *timer)
 387 {
 388         struct xgbe_channel *channel = container_of(timer,
 389                                                     struct xgbe_channel,
 390                                                     tx_timer);
 391         struct xgbe_ring *ring = channel->tx_ring;
 392         struct xgbe_prv_data *pdata = channel->pdata;
 393         struct napi_struct *napi;
 394         unsigned long flags;
 395
 396         DBGPR("-->xgbe_tx_timer\n");
 397
 398         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
 399
 400         spin_lock_irqsave(&ring->lock, flags);
 401
 402         if (napi_schedule_prep(napi)) {
 403                 /* Disable Tx and Rx interrupts */
 404                 if (pdata->per_channel_irq)
 405                         disable_irq(channel->dma_irq);
 406                 else
 407                         xgbe_disable_rx_tx_ints(pdata);
 408
 409                 /* Turn on polling */
 410                 __napi_schedule(napi);
 411         }
 412
 413         channel->tx_timer_active = 0;
 414
 415         spin_unlock_irqrestore(&ring->lock, flags);
 416
 417         DBGPR("<--xgbe_tx_timer\n");
 418
 419         return HRTIMER_NORESTART;
 420 }
 421
 422 static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata)
 423 {
 424         struct xgbe_channel *channel;
 425         unsigned int i;
 426
 427         DBGPR("-->xgbe_init_tx_timers\n");
 428
 429         channel = pdata->channel;
 430         for (i = 0; i < pdata->channel_count; i++, channel++) {
 431                 if (!channel->tx_ring)
 432                         break;
 433
 434                 DBGPR("  %s adding tx timer\n", channel->name);
 435                 hrtimer_init(&channel->tx_timer, CLOCK_MONOTONIC,
 436                              HRTIMER_MODE_REL);
 437                 channel->tx_timer.function = xgbe_tx_timer;
 438         }
 439
 440         DBGPR("<--xgbe_init_tx_timers\n");
 441 }
 442
 443 static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata)
 444 {
 445         struct xgbe_channel *channel;
 446         unsigned int i;
 447
 448         DBGPR("-->xgbe_stop_tx_timers\n");
 449
 450         channel = pdata->channel;
 451         for (i = 0; i < pdata->channel_count; i++, channel++) {
 452                 if (!channel->tx_ring)
 453                         break;
 454
 455                 DBGPR("  %s deleting tx timer\n", channel->name);
 456                 channel->tx_timer_active = 0;
 457                 hrtimer_cancel(&channel->tx_timer);
 458         }
 459
 460         DBGPR("<--xgbe_stop_tx_timers\n");
 461 }
 462
 463 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
 464 {
 465         unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
 466         struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
 467
 468         DBGPR("-->xgbe_get_all_hw_features\n");
 469
 470         mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
 471         mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
 472         mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
 473
 474         memset(hw_feat, 0, sizeof(*hw_feat));
 475
 476         hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
 477
 478         /* Hardware feature register 0 */
 479         hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
 480         hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
 481         hw_feat->sma         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
 482         hw_feat->rwk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
 483         hw_feat->mgk         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
 484         hw_feat->mmc         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
 485         hw_feat->aoe         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
 486         hw_feat->ts          = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
 487         hw_feat->eee         = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
 488         hw_feat->tx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
 489         hw_feat->rx_coe      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
 490         hw_feat->addn_mac    = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
 491                                               ADDMACADRSEL);
 492         hw_feat->ts_src      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
 493         hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
 494
 495         /* Hardware feature register 1 */
 496         hw_feat->rx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 497                                                 RXFIFOSIZE);
 498         hw_feat->tx_fifo_size  = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 499                                                 TXFIFOSIZE);
 500         hw_feat->dcb           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
 501         hw_feat->sph           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
 502         hw_feat->tso           = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
 503         hw_feat->dma_debug     = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
 504         hw_feat->tc_cnt        = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
 505         hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 506                                                   HASHTBLSZ);
 507         hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
 508                                                   L3L4FNUM);
 509
 510         /* Hardware feature register 2 */
 511         hw_feat->rx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
 512         hw_feat->tx_q_cnt     = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
 513         hw_feat->rx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
 514         hw_feat->tx_ch_cnt    = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
 515         hw_feat->pps_out_num  = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
 516         hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
 517
 518         /* Translate the Hash Table size into actual number */
 519         switch (hw_feat->hash_table_size) {
 520         case 0:
 521                 break;
 522         case 1:
 523                 hw_feat->hash_table_size = 64;
 524                 break;
 525         case 2:
 526                 hw_feat->hash_table_size = 128;
 527                 break;
 528         case 3:
 529                 hw_feat->hash_table_size = 256;
 530                 break;
 531         }
 532
 533         /* The Queue and Channel counts are zero based so increment them
 534          * to get the actual number
 535          */
 536         hw_feat->rx_q_cnt++;
 537         hw_feat->tx_q_cnt++;
 538         hw_feat->rx_ch_cnt++;
 539         hw_feat->tx_ch_cnt++;
 540
 541         DBGPR("<--xgbe_get_all_hw_features\n");
 542 }
 543
 544 static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
 545 {
 546         struct xgbe_channel *channel;
 547         unsigned int i;
 548
 549         if (pdata->per_channel_irq) {
 550                 channel = pdata->channel;
 551                 for (i = 0; i < pdata->channel_count; i++, channel++) {
 552                         if (add)
 553                                 netif_napi_add(pdata->netdev, &channel->napi,
 554                                                xgbe_one_poll, NAPI_POLL_WEIGHT);
 555
 556                         napi_enable(&channel->napi);
 557                 }
 558         } else {
 559                 if (add)
 560                         netif_napi_add(pdata->netdev, &pdata->napi,
 561                                        xgbe_all_poll, NAPI_POLL_WEIGHT);
 562
 563                 napi_enable(&pdata->napi);
 564         }
 565 }
 566
 567 static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
 568 {
 569         struct xgbe_channel *channel;
 570         unsigned int i;
 571
 572         if (pdata->per_channel_irq) {
 573                 channel = pdata->channel;
 574                 for (i = 0; i < pdata->channel_count; i++, channel++) {
 575                         napi_disable(&channel->napi);
 576
 577                         if (del)
 578                                 netif_napi_del(&channel->napi);
 579                 }
 580         } else {
 581                 napi_disable(&pdata->napi);
 582
 583                 if (del)
 584                         netif_napi_del(&pdata->napi);
 585         }
 586 }
 587
 588 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
 589 {
 590         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 591
 592         DBGPR("-->xgbe_init_tx_coalesce\n");
 593
 594         pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
 595         pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
 596
 597         hw_if->config_tx_coalesce(pdata);
 598
 599         DBGPR("<--xgbe_init_tx_coalesce\n");
 600 }
 601
 602 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
 603 {
 604         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 605
 606         DBGPR("-->xgbe_init_rx_coalesce\n");
 607
 608         pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
 609         pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
 610
 611         hw_if->config_rx_coalesce(pdata);
 612
 613         DBGPR("<--xgbe_init_rx_coalesce\n");
 614 }
 615
 616 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
 617 {
 618         struct xgbe_desc_if *desc_if = &pdata->desc_if;
 619         struct xgbe_channel *channel;
 620         struct xgbe_ring *ring;
 621         struct xgbe_ring_data *rdata;
 622         unsigned int i, j;
 623
 624         DBGPR("-->xgbe_free_tx_data\n");
 625
 626         channel = pdata->channel;
 627         for (i = 0; i < pdata->channel_count; i++, channel++) {
 628                 ring = channel->tx_ring;
 629                 if (!ring)
 630                         break;
 631
 632                 for (j = 0; j < ring->rdesc_count; j++) {
 633                         rdata = XGBE_GET_DESC_DATA(ring, j);
 634                         desc_if->unmap_rdata(pdata, rdata);
 635                 }
 636         }
 637
 638         DBGPR("<--xgbe_free_tx_data\n");
 639 }
 640
 641 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
 642 {
 643         struct xgbe_desc_if *desc_if = &pdata->desc_if;
 644         struct xgbe_channel *channel;
 645         struct xgbe_ring *ring;
 646         struct xgbe_ring_data *rdata;
 647         unsigned int i, j;
 648
 649         DBGPR("-->xgbe_free_rx_data\n");
 650
 651         channel = pdata->channel;
 652         for (i = 0; i < pdata->channel_count; i++, channel++) {
 653                 ring = channel->rx_ring;
 654                 if (!ring)
 655                         break;
 656
 657                 for (j = 0; j < ring->rdesc_count; j++) {
 658                         rdata = XGBE_GET_DESC_DATA(ring, j);
 659                         desc_if->unmap_rdata(pdata, rdata);
 660                 }
 661         }
 662
 663         DBGPR("<--xgbe_free_rx_data\n");
 664 }
 665
 666 static void xgbe_adjust_link(struct net_device *netdev)
 667 {
 668         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 669         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 670         struct phy_device *phydev = pdata->phydev;
 671         int new_state = 0;
 672
 673         if (phydev == NULL)
 674                 return;
 675
 676         if (phydev->link) {
 677                 /* Flow control support */
 678                 if (pdata->pause_autoneg) {
 679                         if (phydev->pause || phydev->asym_pause) {
 680                                 pdata->tx_pause = 1;
 681                                 pdata->rx_pause = 1;
 682                         } else {
 683                                 pdata->tx_pause = 0;
 684                                 pdata->rx_pause = 0;
 685                         }
 686                 }
 687
 688                 if (pdata->tx_pause != pdata->phy_tx_pause) {
 689                         hw_if->config_tx_flow_control(pdata);
 690                         pdata->phy_tx_pause = pdata->tx_pause;
 691                 }
 692
 693                 if (pdata->rx_pause != pdata->phy_rx_pause) {
 694                         hw_if->config_rx_flow_control(pdata);
 695                         pdata->phy_rx_pause = pdata->rx_pause;
 696                 }
 697
 698                 /* Speed support */
 699                 if (phydev->speed != pdata->phy_speed) {
 700                         new_state = 1;
 701
 702                         switch (phydev->speed) {
 703                         case SPEED_10000:
 704                                 hw_if->set_xgmii_speed(pdata);
 705                                 break;
 706
 707                         case SPEED_2500:
 708                                 hw_if->set_gmii_2500_speed(pdata);
 709                                 break;
 710
 711                         case SPEED_1000:
 712                                 hw_if->set_gmii_speed(pdata);
 713                                 break;
 714                         }
 715                         pdata->phy_speed = phydev->speed;
 716                 }
 717
 718                 if (phydev->link != pdata->phy_link) {
 719                         new_state = 1;
 720                         pdata->phy_link = 1;
 721                 }
 722         } else if (pdata->phy_link) {
 723                 new_state = 1;
 724                 pdata->phy_link = 0;
 725                 pdata->phy_speed = SPEED_UNKNOWN;
 726         }
 727
 728         if (new_state)
 729                 phy_print_status(phydev);
 730 }
 731
 732 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
 733 {
 734         struct net_device *netdev = pdata->netdev;
 735         struct phy_device *phydev = pdata->phydev;
 736         int ret;
 737
 738         pdata->phy_link = -1;
 739         pdata->phy_speed = SPEED_UNKNOWN;
 740         pdata->phy_tx_pause = pdata->tx_pause;
 741         pdata->phy_rx_pause = pdata->rx_pause;
 742
 743         ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link,
 744                                  pdata->phy_mode);
 745         if (ret) {
 746                 netdev_err(netdev, "phy_connect_direct failed\n");
 747                 return ret;
 748         }
 749
 750         if (!phydev->drv || (phydev->drv->phy_id == 0)) {
 751                 netdev_err(netdev, "phy_id not valid\n");
 752                 ret = -ENODEV;
 753                 goto err_phy_connect;
 754         }
 755         DBGPR("  phy_connect_direct succeeded for PHY %s, link=%d\n",
 756               dev_name(&phydev->dev), phydev->link);
 757
 758         return 0;
 759
 760 err_phy_connect:
 761         phy_disconnect(phydev);
 762
 763         return ret;
 764 }
 765
 766 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
 767 {
 768         if (!pdata->phydev)
 769                 return;
 770
 771         phy_disconnect(pdata->phydev);
 772 }
 773
 774 int xgbe_powerdown(struct net_device *netdev, unsigned int caller)
 775 {
 776         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 777         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 778         unsigned long flags;
 779
 780         DBGPR("-->xgbe_powerdown\n");
 781
 782         if (!netif_running(netdev) ||
 783             (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
 784                 netdev_alert(netdev, "Device is already powered down\n");
 785                 DBGPR("<--xgbe_powerdown\n");
 786                 return -EINVAL;
 787         }
 788
 789         phy_stop(pdata->phydev);
 790
 791         spin_lock_irqsave(&pdata->lock, flags);
 792
 793         if (caller == XGMAC_DRIVER_CONTEXT)
 794                 netif_device_detach(netdev);
 795
 796         netif_tx_stop_all_queues(netdev);
 797         xgbe_napi_disable(pdata, 0);
 798
 799         /* Powerdown Tx/Rx */
 800         hw_if->powerdown_tx(pdata);
 801         hw_if->powerdown_rx(pdata);
 802
 803         pdata->power_down = 1;
 804
 805         spin_unlock_irqrestore(&pdata->lock, flags);
 806
 807         DBGPR("<--xgbe_powerdown\n");
 808
 809         return 0;
 810 }
 811
 812 int xgbe_powerup(struct net_device *netdev, unsigned int caller)
 813 {
 814         struct xgbe_prv_data *pdata = netdev_priv(netdev);
 815         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 816         unsigned long flags;
 817
 818         DBGPR("-->xgbe_powerup\n");
 819
 820         if (!netif_running(netdev) ||
 821             (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
 822                 netdev_alert(netdev, "Device is already powered up\n");
 823                 DBGPR("<--xgbe_powerup\n");
 824                 return -EINVAL;
 825         }
 826
 827         spin_lock_irqsave(&pdata->lock, flags);
 828
 829         pdata->power_down = 0;
 830
 831         phy_start(pdata->phydev);
 832
 833         /* Enable Tx/Rx */
 834         hw_if->powerup_tx(pdata);
 835         hw_if->powerup_rx(pdata);
 836
 837         if (caller == XGMAC_DRIVER_CONTEXT)
 838                 netif_device_attach(netdev);
 839
 840         xgbe_napi_enable(pdata, 0);
 841         netif_tx_start_all_queues(netdev);
 842
 843         spin_unlock_irqrestore(&pdata->lock, flags);
 844
 845         DBGPR("<--xgbe_powerup\n");
 846
 847         return 0;
 848 }
 849
 850 static int xgbe_start(struct xgbe_prv_data *pdata)
 851 {
 852         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 853         struct net_device *netdev = pdata->netdev;
 854
 855         DBGPR("-->xgbe_start\n");
 856
 857         xgbe_set_rx_mode(netdev);
 858
 859         hw_if->init(pdata);
 860
 861         phy_start(pdata->phydev);
 862
 863         hw_if->enable_tx(pdata);
 864         hw_if->enable_rx(pdata);
 865
 866         xgbe_init_tx_timers(pdata);
 867
 868         xgbe_napi_enable(pdata, 1);
 869         netif_tx_start_all_queues(netdev);
 870
 871         DBGPR("<--xgbe_start\n");
 872
 873         return 0;
 874 }
 875
 876 static void xgbe_stop(struct xgbe_prv_data *pdata)
 877 {
 878         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 879         struct net_device *netdev = pdata->netdev;
 880
 881         DBGPR("-->xgbe_stop\n");
 882
 883         phy_stop(pdata->phydev);
 884
 885         netif_tx_stop_all_queues(netdev);
 886         xgbe_napi_disable(pdata, 1);
 887
 888         xgbe_stop_tx_timers(pdata);
 889
 890         hw_if->disable_tx(pdata);
 891         hw_if->disable_rx(pdata);
 892
 893         DBGPR("<--xgbe_stop\n");
 894 }
 895
 896 static void xgbe_restart_dev(struct xgbe_prv_data *pdata, unsigned int reset)
 897 {
 898         struct xgbe_channel *channel;
 899         struct xgbe_hw_if *hw_if = &pdata->hw_if;
 900         unsigned int i;
 901
 902         DBGPR("-->xgbe_restart_dev\n");
 903
 904         /* If not running, "restart" will happen on open */
 905         if (!netif_running(pdata->netdev))
 906                 return;
 907
 908         xgbe_stop(pdata);
 909         synchronize_irq(pdata->dev_irq);
 910         if (pdata->per_channel_irq) {
 911                 channel = pdata->channel;
 912                 for (i = 0; i < pdata->channel_count; i++, channel++)
 913                         synchronize_irq(channel->dma_irq);
 914         }
 915
 916         xgbe_free_tx_data(pdata);
 917         xgbe_free_rx_data(pdata);
 918
 919         /* Issue software reset to device if requested */
 920         if (reset)
 921                 hw_if->exit(pdata);
 922
 923         xgbe_start(pdata);
 924
 925         DBGPR("<--xgbe_restart_dev\n");
 926 }
 927
 928 static void xgbe_restart(struct work_struct *work)
 929 {
 930         struct xgbe_prv_data *pdata = container_of(work,
 931                                                    struct xgbe_prv_data,
 932                                                    restart_work);
 933
 934         rtnl_lock();
 935
 936         xgbe_restart_dev(pdata, 1);
 937
 938         rtnl_unlock();
 939 }
 940
 941 static void xgbe_tx_tstamp(struct work_struct *work)
 942 {
 943         struct xgbe_prv_data *pdata = container_of(work,
 944                                                    struct xgbe_prv_data,
 945                                                    tx_tstamp_work);
 946         struct skb_shared_hwtstamps hwtstamps;
 947         u64 nsec;
 948         unsigned long flags;
 949
 950         if (pdata->tx_tstamp) {
 951                 nsec = timecounter_cyc2time(&pdata->tstamp_tc,
 952                                             pdata->tx_tstamp);
 953
 954                 memset(&hwtstamps, 0, sizeof(hwtstamps));
 955                 hwtstamps.hwtstamp = ns_to_ktime(nsec);
 956                 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
 957         }
 958
 959         dev_kfree_skb_any(pdata->tx_tstamp_skb);
 960
 961         spin_lock_irqsave(&pdata->tstamp_lock, flags);
 962         pdata->tx_tstamp_skb = NULL;
 963         spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
 964 }
 965
 966 static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
 967                                       struct ifreq *ifreq)
 968 {
 969         if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
 970                          sizeof(pdata->tstamp_config)))
 971                 return -EFAULT;
 972
 973         return 0;
 974 }
 975
 976 static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
 977                                       struct ifreq *ifreq)
 978 {
 979         struct hwtstamp_config config;
 980         unsigned int mac_tscr;
 981
 982         if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
 983                 return -EFAULT;
 984
 985         if (config.flags)
 986                 return -EINVAL;
 987
 988         mac_tscr = 0;
 989
 990         switch (config.tx_type) {
 991         case HWTSTAMP_TX_OFF:
 992                 break;
 993
 994         case HWTSTAMP_TX_ON:
 995                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
 996                 break;
 997
 998         default:
 999                 return -ERANGE;
1000         }
1001
1002         switch (config.rx_filter) {
1003         case HWTSTAMP_FILTER_NONE:
1004                 break;
1005
1006         case HWTSTAMP_FILTER_ALL:
1007                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1008                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1009                 break;
1010
1011         /* PTP v2, UDP, any kind of event packet */
1012         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1013                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1014         /* PTP v1, UDP, any kind of event packet */
1015         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1016                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1017                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1018                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1019                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1020                 break;
1021
1022         /* PTP v2, UDP, Sync packet */
1023         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1024                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1025         /* PTP v1, UDP, Sync packet */
1026         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1027                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1028                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1029                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1030                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1031                 break;
1032
1033         /* PTP v2, UDP, Delay_req packet */
1034         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1035                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1036         /* PTP v1, UDP, Delay_req packet */
1037         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1038                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1039                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1040                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1041                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1042                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1043                 break;
1044
1045         /* 802.AS1, Ethernet, any kind of event packet */
1046         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1047                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1048                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1049                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1050                 break;
1051
1052         /* 802.AS1, Ethernet, Sync packet */
1053         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1054                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1055                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1056                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1057                 break;
1058
1059         /* 802.AS1, Ethernet, Delay_req packet */
1060         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1061                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1062                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1063                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1064                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1065                 break;
1066
1067         /* PTP v2/802.AS1, any layer, any kind of event packet */
1068         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1069                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1070                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1071                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1072                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1073                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1074                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1075                 break;
1076
1077         /* PTP v2/802.AS1, any layer, Sync packet */
1078         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1079                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1080                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1081                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1082                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1083                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1084                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1085                 break;
1086
1087         /* PTP v2/802.AS1, any layer, Delay_req packet */
1088         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1089                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1090                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1091                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1092                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1093                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1094                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1095                 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1096                 break;
1097
1098         default:
1099                 return -ERANGE;
1100         }
1101
1102         pdata->hw_if.config_tstamp(pdata, mac_tscr);
1103
1104         memcpy(&pdata->tstamp_config, &config, sizeof(config));
1105
1106         return 0;
1107 }
1108
1109 static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1110                                 struct sk_buff *skb,
1111                                 struct xgbe_packet_data *packet)
1112 {
1113         unsigned long flags;
1114
1115         if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1116                 spin_lock_irqsave(&pdata->tstamp_lock, flags);
1117                 if (pdata->tx_tstamp_skb) {
1118                         /* Another timestamp in progress, ignore this one */
1119                         XGMAC_SET_BITS(packet->attributes,
1120                                        TX_PACKET_ATTRIBUTES, PTP, 0);
1121                 } else {
1122                         pdata->tx_tstamp_skb = skb_get(skb);
1123                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1124                 }
1125                 spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1126         }
1127
1128         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1129                 skb_tx_timestamp(skb);
1130 }
1131
1132 static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1133 {
1134         if (vlan_tx_tag_present(skb))
1135                 packet->vlan_ctag = vlan_tx_tag_get(skb);
1136 }
1137
1138 static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
1139 {
1140         int ret;
1141
1142         if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1143                             TSO_ENABLE))
1144                 return 0;
1145
1146         ret = skb_cow_head(skb, 0);
1147         if (ret)
1148                 return ret;
1149
1150         packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1151         packet->tcp_header_len = tcp_hdrlen(skb);
1152         packet->tcp_payload_len = skb->len - packet->header_len;
1153         packet->mss = skb_shinfo(skb)->gso_size;
1154         DBGPR("  packet->header_len=%u\n", packet->header_len);
1155         DBGPR("  packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
1156               packet->tcp_header_len, packet->tcp_payload_len);
1157         DBGPR("  packet->mss=%u\n", packet->mss);
1158
1159         return 0;
1160 }
1161
1162 static int xgbe_is_tso(struct sk_buff *skb)
1163 {
1164         if (skb->ip_summed != CHECKSUM_PARTIAL)
1165                 return 0;
1166
1167         if (!skb_is_gso(skb))
1168                 return 0;
1169
1170         DBGPR("  TSO packet to be processed\n");
1171
1172         return 1;
1173 }
1174
1175 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
1176                              struct xgbe_ring *ring, struct sk_buff *skb,
1177                              struct xgbe_packet_data *packet)
1178 {
1179         struct skb_frag_struct *frag;
1180         unsigned int context_desc;
1181         unsigned int len;
1182         unsigned int i;
1183
1184         context_desc = 0;
1185         packet->rdesc_count = 0;
1186
1187         if (xgbe_is_tso(skb)) {
1188                 /* TSO requires an extra descriptor if mss is different */
1189                 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
1190                         context_desc = 1;
1191                         packet->rdesc_count++;
1192                 }
1193
1194                 /* TSO requires an extra descriptor for TSO header */
1195                 packet->rdesc_count++;
1196
1197                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1198                                TSO_ENABLE, 1);
1199                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1200                                CSUM_ENABLE, 1);
1201         } else if (skb->ip_summed == CHECKSUM_PARTIAL)
1202                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1203                                CSUM_ENABLE, 1);
1204
1205         if (vlan_tx_tag_present(skb)) {
1206                 /* VLAN requires an extra descriptor if tag is different */
1207                 if (vlan_tx_tag_get(skb) != ring->tx.cur_vlan_ctag)
1208                         /* We can share with the TSO context descriptor */
1209                         if (!context_desc) {
1210                                 context_desc = 1;
1211                                 packet->rdesc_count++;
1212                         }
1213
1214                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1215                                VLAN_CTAG, 1);
1216         }
1217
1218         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1219             (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
1220                 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1221                                PTP, 1);
1222
1223         for (len = skb_headlen(skb); len;) {
1224                 packet->rdesc_count++;
1225                 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1226         }
1227
1228         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1229                 frag = &skb_shinfo(skb)->frags[i];
1230                 for (len = skb_frag_size(frag); len; ) {
1231                         packet->rdesc_count++;
1232                         len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
1233                 }
1234         }
1235 }
1236
1237 static int xgbe_open(struct net_device *netdev)
1238 {
1239         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1240         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1241         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1242         struct xgbe_channel *channel = NULL;
1243         char dma_irq_name[IFNAMSIZ + 32];
1244         unsigned int i = 0;
1245         int ret;
1246
1247         DBGPR("-->xgbe_open\n");
1248
1249         /* Initialize the phy */
1250         ret = xgbe_phy_init(pdata);
1251         if (ret)
1252                 return ret;
1253
1254         /* Enable the clocks */
1255         ret = clk_prepare_enable(pdata->sysclk);
1256         if (ret) {
1257                 netdev_alert(netdev, "dma clk_prepare_enable failed\n");
1258                 goto err_phy_init;
1259         }
1260
1261         ret = clk_prepare_enable(pdata->ptpclk);
1262         if (ret) {
1263                 netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
1264                 goto err_sysclk;
1265         }
1266
1267         /* Calculate the Rx buffer size before allocating rings */
1268         ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
1269         if (ret < 0)
1270                 goto err_ptpclk;
1271         pdata->rx_buf_size = ret;
1272
1273         /* Allocate the channel and ring structures */
1274         ret = xgbe_alloc_channels(pdata);
1275         if (ret)
1276                 goto err_ptpclk;
1277
1278         /* Allocate the ring descriptors and buffers */
1279         ret = desc_if->alloc_ring_resources(pdata);
1280         if (ret)
1281                 goto err_channels;
1282
1283         /* Initialize the device restart and Tx timestamp work struct */
1284         INIT_WORK(&pdata->restart_work, xgbe_restart);
1285         INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1286
1287         /* Request interrupts */
1288         ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
1289                                netdev->name, pdata);
1290         if (ret) {
1291                 netdev_alert(netdev, "error requesting irq %d\n",
1292                              pdata->dev_irq);
1293                 goto err_rings;
1294         }
1295
1296         if (pdata->per_channel_irq) {
1297                 channel = pdata->channel;
1298                 for (i = 0; i < pdata->channel_count; i++, channel++) {
1299                         snprintf(dma_irq_name, sizeof(dma_irq_name) - 1,
1300                                  "%s-TxRx-%u", netdev_name(netdev),
1301                                  channel->queue_index);
1302
1303                         ret = devm_request_irq(pdata->dev, channel->dma_irq,
1304                                                xgbe_dma_isr, 0, dma_irq_name,
1305                                                channel);
1306                         if (ret) {
1307                                 netdev_alert(netdev,
1308                                              "error requesting irq %d\n",
1309                                              channel->dma_irq);
1310                                 goto err_irq;
1311                         }
1312                 }
1313         }
1314
1315         ret = xgbe_start(pdata);
1316         if (ret)
1317                 goto err_start;
1318
1319         DBGPR("<--xgbe_open\n");
1320
1321         return 0;
1322
1323 err_start:
1324         hw_if->exit(pdata);
1325
1326 err_irq:
1327         if (pdata->per_channel_irq) {
1328                 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
1329                 for (i--, channel--; i < pdata->channel_count; i--, channel--)
1330                         devm_free_irq(pdata->dev, channel->dma_irq, channel);
1331         }
1332
1333         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1334
1335 err_rings:
1336         desc_if->free_ring_resources(pdata);
1337
1338 err_channels:
1339         xgbe_free_channels(pdata);
1340
1341 err_ptpclk:
1342         clk_disable_unprepare(pdata->ptpclk);
1343
1344 err_sysclk:
1345         clk_disable_unprepare(pdata->sysclk);
1346
1347 err_phy_init:
1348         xgbe_phy_exit(pdata);
1349
1350         return ret;
1351 }
1352
1353 static int xgbe_close(struct net_device *netdev)
1354 {
1355         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1356         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1357         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1358         struct xgbe_channel *channel;
1359         unsigned int i;
1360
1361         DBGPR("-->xgbe_close\n");
1362
1363         /* Stop the device */
1364         xgbe_stop(pdata);
1365
1366         /* Issue software reset to device */
1367         hw_if->exit(pdata);
1368
1369         /* Free the ring descriptors and buffers */
1370         desc_if->free_ring_resources(pdata);
1371
1372         /* Release the interrupts */
1373         devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
1374         if (pdata->per_channel_irq) {
1375                 channel = pdata->channel;
1376                 for (i = 0; i < pdata->channel_count; i++, channel++)
1377                         devm_free_irq(pdata->dev, channel->dma_irq, channel);
1378         }
1379
1380         /* Free the channel and ring structures */
1381         xgbe_free_channels(pdata);
1382
1383         /* Disable the clocks */
1384         clk_disable_unprepare(pdata->ptpclk);
1385         clk_disable_unprepare(pdata->sysclk);
1386
1387         /* Release the phy */
1388         xgbe_phy_exit(pdata);
1389
1390         DBGPR("<--xgbe_close\n");
1391
1392         return 0;
1393 }
1394
1395 static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
1396 {
1397         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1398         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1399         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1400         struct xgbe_channel *channel;
1401         struct xgbe_ring *ring;
1402         struct xgbe_packet_data *packet;
1403         unsigned long flags;
1404         int ret;
1405
1406         DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
1407
1408         channel = pdata->channel + skb->queue_mapping;
1409         ring = channel->tx_ring;
1410         packet = &ring->packet_data;
1411
1412         ret = NETDEV_TX_OK;
1413
1414         spin_lock_irqsave(&ring->lock, flags);
1415
1416         if (skb->len == 0) {
1417                 netdev_err(netdev, "empty skb received from stack\n");
1418                 dev_kfree_skb_any(skb);
1419                 goto tx_netdev_return;
1420         }
1421
1422         /* Calculate preliminary packet info */
1423         memset(packet, 0, sizeof(*packet));
1424         xgbe_packet_info(pdata, ring, skb, packet);
1425
1426         /* Check that there are enough descriptors available */
1427         if (packet->rdesc_count > xgbe_tx_avail_desc(ring)) {
1428                 DBGPR("  Tx queue stopped, not enough descriptors available\n");
1429                 netif_stop_subqueue(netdev, channel->queue_index);
1430                 ring->tx.queue_stopped = 1;
1431                 ret = NETDEV_TX_BUSY;
1432                 goto tx_netdev_return;
1433         }
1434
1435         ret = xgbe_prep_tso(skb, packet);
1436         if (ret) {
1437                 netdev_err(netdev, "error processing TSO packet\n");
1438                 dev_kfree_skb_any(skb);
1439                 goto tx_netdev_return;
1440         }
1441         xgbe_prep_vlan(skb, packet);
1442
1443         if (!desc_if->map_tx_skb(channel, skb)) {
1444                 dev_kfree_skb_any(skb);
1445                 goto tx_netdev_return;
1446         }
1447
1448         xgbe_prep_tx_tstamp(pdata, skb, packet);
1449
1450         /* Configure required descriptor fields for transmission */
1451         hw_if->dev_xmit(channel);
1452
1453 #ifdef XGMAC_ENABLE_TX_PKT_DUMP
1454         xgbe_print_pkt(netdev, skb, true);
1455 #endif
1456
1457 tx_netdev_return:
1458         spin_unlock_irqrestore(&ring->lock, flags);
1459
1460         DBGPR("<--xgbe_xmit\n");
1461
1462         return ret;
1463 }
1464
1465 static void xgbe_set_rx_mode(struct net_device *netdev)
1466 {
1467         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1468         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1469         unsigned int pr_mode, am_mode;
1470
1471         DBGPR("-->xgbe_set_rx_mode\n");
1472
1473         pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
1474         am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
1475
1476         hw_if->set_promiscuous_mode(pdata, pr_mode);
1477         hw_if->set_all_multicast_mode(pdata, am_mode);
1478
1479         hw_if->add_mac_addresses(pdata);
1480
1481         DBGPR("<--xgbe_set_rx_mode\n");
1482 }
1483
1484 static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
1485 {
1486         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1487         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1488         struct sockaddr *saddr = addr;
1489
1490         DBGPR("-->xgbe_set_mac_address\n");
1491
1492         if (!is_valid_ether_addr(saddr->sa_data))
1493                 return -EADDRNOTAVAIL;
1494
1495         memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
1496
1497         hw_if->set_mac_address(pdata, netdev->dev_addr);
1498
1499         DBGPR("<--xgbe_set_mac_address\n");
1500
1501         return 0;
1502 }
1503
1504 static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
1505 {
1506         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1507         int ret;
1508
1509         switch (cmd) {
1510         case SIOCGHWTSTAMP:
1511                 ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
1512                 break;
1513
1514         case SIOCSHWTSTAMP:
1515                 ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
1516                 break;
1517
1518         default:
1519                 ret = -EOPNOTSUPP;
1520         }
1521
1522         return ret;
1523 }
1524
1525 static int xgbe_change_mtu(struct net_device *netdev, int mtu)
1526 {
1527         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1528         int ret;
1529
1530         DBGPR("-->xgbe_change_mtu\n");
1531
1532         ret = xgbe_calc_rx_buf_size(netdev, mtu);
1533         if (ret < 0)
1534                 return ret;
1535
1536         pdata->rx_buf_size = ret;
1537         netdev->mtu = mtu;
1538
1539         xgbe_restart_dev(pdata, 0);
1540
1541         DBGPR("<--xgbe_change_mtu\n");
1542
1543         return 0;
1544 }
1545
1546 static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
1547                                                   struct rtnl_link_stats64 *s)
1548 {
1549         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1550         struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
1551
1552         DBGPR("-->%s\n", __func__);
1553
1554         pdata->hw_if.read_mmc_stats(pdata);
1555
1556         s->rx_packets = pstats->rxframecount_gb;
1557         s->rx_bytes = pstats->rxoctetcount_gb;
1558         s->rx_errors = pstats->rxframecount_gb -
1559                        pstats->rxbroadcastframes_g -
1560                        pstats->rxmulticastframes_g -
1561                        pstats->rxunicastframes_g;
1562         s->multicast = pstats->rxmulticastframes_g;
1563         s->rx_length_errors = pstats->rxlengtherror;
1564         s->rx_crc_errors = pstats->rxcrcerror;
1565         s->rx_fifo_errors = pstats->rxfifooverflow;
1566
1567         s->tx_packets = pstats->txframecount_gb;
1568         s->tx_bytes = pstats->txoctetcount_gb;
1569         s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
1570         s->tx_dropped = netdev->stats.tx_dropped;
1571
1572         DBGPR("<--%s\n", __func__);
1573
1574         return s;
1575 }
1576
1577 static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
1578                                 u16 vid)
1579 {
1580         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1581         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1582
1583         DBGPR("-->%s\n", __func__);
1584
1585         set_bit(vid, pdata->active_vlans);
1586         hw_if->update_vlan_hash_table(pdata);
1587
1588         DBGPR("<--%s\n", __func__);
1589
1590         return 0;
1591 }
1592
1593 static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
1594                                  u16 vid)
1595 {
1596         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1597         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1598
1599         DBGPR("-->%s\n", __func__);
1600
1601         clear_bit(vid, pdata->active_vlans);
1602         hw_if->update_vlan_hash_table(pdata);
1603
1604         DBGPR("<--%s\n", __func__);
1605
1606         return 0;
1607 }
1608
1609 #ifdef CONFIG_NET_POLL_CONTROLLER
1610 static void xgbe_poll_controller(struct net_device *netdev)
1611 {
1612         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1613         struct xgbe_channel *channel;
1614         unsigned int i;
1615
1616         DBGPR("-->xgbe_poll_controller\n");
1617
1618         if (pdata->per_channel_irq) {
1619                 channel = pdata->channel;
1620                 for (i = 0; i < pdata->channel_count; i++, channel++)
1621                         xgbe_dma_isr(channel->dma_irq, channel);
1622         } else {
1623                 disable_irq(pdata->dev_irq);
1624                 xgbe_isr(pdata->dev_irq, pdata);
1625                 enable_irq(pdata->dev_irq);
1626         }
1627
1628         DBGPR("<--xgbe_poll_controller\n");
1629 }
1630 #endif /* End CONFIG_NET_POLL_CONTROLLER */
1631
1632 static int xgbe_setup_tc(struct net_device *netdev, u8 tc)
1633 {
1634         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1635         unsigned int offset, queue;
1636         u8 i;
1637
1638         if (tc && (tc != pdata->hw_feat.tc_cnt))
1639                 return -EINVAL;
1640
1641         if (tc) {
1642                 netdev_set_num_tc(netdev, tc);
1643                 for (i = 0, queue = 0, offset = 0; i < tc; i++) {
1644                         while ((queue < pdata->tx_q_count) &&
1645                                (pdata->q2tc_map[queue] == i))
1646                                 queue++;
1647
1648                         DBGPR("  TC%u using TXq%u-%u\n", i, offset, queue - 1);
1649                         netdev_set_tc_queue(netdev, i, queue - offset, offset);
1650                         offset = queue;
1651                 }
1652         } else {
1653                 netdev_reset_tc(netdev);
1654         }
1655
1656         return 0;
1657 }
1658
1659 static int xgbe_set_features(struct net_device *netdev,
1660                              netdev_features_t features)
1661 {
1662         struct xgbe_prv_data *pdata = netdev_priv(netdev);
1663         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1664         netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
1665         int ret = 0;
1666
1667         rxhash = pdata->netdev_features & NETIF_F_RXHASH;
1668         rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
1669         rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
1670         rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
1671
1672         if ((features & NETIF_F_RXHASH) && !rxhash)
1673                 ret = hw_if->enable_rss(pdata);
1674         else if (!(features & NETIF_F_RXHASH) && rxhash)
1675                 ret = hw_if->disable_rss(pdata);
1676         if (ret)
1677                 return ret;
1678
1679         if ((features & NETIF_F_RXCSUM) && !rxcsum)
1680                 hw_if->enable_rx_csum(pdata);
1681         else if (!(features & NETIF_F_RXCSUM) && rxcsum)
1682                 hw_if->disable_rx_csum(pdata);
1683
1684         if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
1685                 hw_if->enable_rx_vlan_stripping(pdata);
1686         else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
1687                 hw_if->disable_rx_vlan_stripping(pdata);
1688
1689         if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
1690                 hw_if->enable_rx_vlan_filtering(pdata);
1691         else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
1692                 hw_if->disable_rx_vlan_filtering(pdata);
1693
1694         pdata->netdev_features = features;
1695
1696         DBGPR("<--xgbe_set_features\n");
1697
1698         return 0;
1699 }
1700
1701 static const struct net_device_ops xgbe_netdev_ops = {
1702         .ndo_open               = xgbe_open,
1703         .ndo_stop               = xgbe_close,
1704         .ndo_start_xmit         = xgbe_xmit,
1705         .ndo_set_rx_mode        = xgbe_set_rx_mode,
1706         .ndo_set_mac_address    = xgbe_set_mac_address,
1707         .ndo_validate_addr      = eth_validate_addr,
1708         .ndo_do_ioctl           = xgbe_ioctl,
1709         .ndo_change_mtu         = xgbe_change_mtu,
1710         .ndo_get_stats64        = xgbe_get_stats64,
1711         .ndo_vlan_rx_add_vid    = xgbe_vlan_rx_add_vid,
1712         .ndo_vlan_rx_kill_vid   = xgbe_vlan_rx_kill_vid,
1713 #ifdef CONFIG_NET_POLL_CONTROLLER
1714         .ndo_poll_controller    = xgbe_poll_controller,
1715 #endif
1716         .ndo_setup_tc           = xgbe_setup_tc,
1717         .ndo_set_features       = xgbe_set_features,
1718 };
1719
1720 struct net_device_ops *xgbe_get_netdev_ops(void)
1721 {
1722         return (struct net_device_ops *)&xgbe_netdev_ops;
1723 }
1724
1725 static void xgbe_rx_refresh(struct xgbe_channel *channel)
1726 {
1727         struct xgbe_prv_data *pdata = channel->pdata;
1728         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1729         struct xgbe_ring *ring = channel->rx_ring;
1730         struct xgbe_ring_data *rdata;
1731
1732         desc_if->realloc_rx_buffer(channel);
1733
1734         /* Update the Rx Tail Pointer Register with address of
1735          * the last cleaned entry */
1736         rdata = XGBE_GET_DESC_DATA(ring, ring->rx.realloc_index - 1);
1737         XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1738                           lower_32_bits(rdata->rdesc_dma));
1739 }
1740
1741 static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1742                                        struct xgbe_ring_data *rdata,
1743                                        unsigned int *len)
1744 {
1745         struct net_device *netdev = pdata->netdev;
1746         struct sk_buff *skb;
1747         u8 *packet;
1748         unsigned int copy_len;
1749
1750         skb = netdev_alloc_skb_ip_align(netdev, rdata->rx_hdr.dma_len);
1751         if (!skb)
1752                 return NULL;
1753
1754         packet = page_address(rdata->rx_hdr.pa.pages) +
1755                  rdata->rx_hdr.pa.pages_offset;
1756         copy_len = (rdata->hdr_len) ? rdata->hdr_len : *len;
1757         copy_len = min(rdata->rx_hdr.dma_len, copy_len);
1758         skb_copy_to_linear_data(skb, packet, copy_len);
1759         skb_put(skb, copy_len);
1760
1761         *len -= copy_len;
1762
1763         return skb;
1764 }
1765
1766 static int xgbe_tx_poll(struct xgbe_channel *channel)
1767 {
1768         struct xgbe_prv_data *pdata = channel->pdata;
1769         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1770         struct xgbe_desc_if *desc_if = &pdata->desc_if;
1771         struct xgbe_ring *ring = channel->tx_ring;
1772         struct xgbe_ring_data *rdata;
1773         struct xgbe_ring_desc *rdesc;
1774         struct net_device *netdev = pdata->netdev;
1775         unsigned long flags;
1776         int processed = 0;
1777
1778         DBGPR("-->xgbe_tx_poll\n");
1779
1780         /* Nothing to do if there isn't a Tx ring for this channel */
1781         if (!ring)
1782                 return 0;
1783
1784         spin_lock_irqsave(&ring->lock, flags);
1785
1786         while ((processed < XGBE_TX_DESC_MAX_PROC) &&
1787                (ring->dirty < ring->cur)) {
1788                 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
1789                 rdesc = rdata->rdesc;
1790
1791                 if (!hw_if->tx_complete(rdesc))
1792                         break;
1793
1794 #ifdef XGMAC_ENABLE_TX_DESC_DUMP
1795                 xgbe_dump_tx_desc(ring, ring->dirty, 1, 0);
1796 #endif
1797
1798                 /* Free the SKB and reset the descriptor for re-use */
1799                 desc_if->unmap_rdata(pdata, rdata);
1800                 hw_if->tx_desc_reset(rdata);
1801
1802                 processed++;
1803                 ring->dirty++;
1804         }
1805
1806         if ((ring->tx.queue_stopped == 1) &&
1807             (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
1808                 ring->tx.queue_stopped = 0;
1809                 netif_wake_subqueue(netdev, channel->queue_index);
1810         }
1811
1812         DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
1813
1814         spin_unlock_irqrestore(&ring->lock, flags);
1815
1816         return processed;
1817 }
1818
1819 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
1820 {
1821         struct xgbe_prv_data *pdata = channel->pdata;
1822         struct xgbe_hw_if *hw_if = &pdata->hw_if;
1823         struct xgbe_ring *ring = channel->rx_ring;
1824         struct xgbe_ring_data *rdata;
1825         struct xgbe_packet_data *packet;
1826         struct net_device *netdev = pdata->netdev;
1827         struct napi_struct *napi;
1828         struct sk_buff *skb;
1829         struct skb_shared_hwtstamps *hwtstamps;
1830         unsigned int incomplete, error, context_next, context;
1831         unsigned int len, put_len, max_len;
1832         unsigned int received = 0;
1833         int packet_count = 0;
1834
1835         DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
1836
1837         /* Nothing to do if there isn't a Rx ring for this channel */
1838         if (!ring)
1839                 return 0;
1840
1841         napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
1842
1843         rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1844         packet = &ring->packet_data;
1845         while (packet_count < budget) {
1846                 DBGPR("  cur = %d\n", ring->cur);
1847
1848                 /* First time in loop see if we need to restore state */
1849                 if (!received && rdata->state_saved) {
1850                         incomplete = rdata->state.incomplete;
1851                         context_next = rdata->state.context_next;
1852                         skb = rdata->state.skb;
1853                         error = rdata->state.error;
1854                         len = rdata->state.len;
1855                 } else {
1856                         memset(packet, 0, sizeof(*packet));
1857                         incomplete = 0;
1858                         context_next = 0;
1859                         skb = NULL;
1860                         error = 0;
1861                         len = 0;
1862                 }
1863
1864 read_again:
1865                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1866
1867                 if (ring->dirty > (XGBE_RX_DESC_CNT >> 3))
1868                         xgbe_rx_refresh(channel);
1869
1870                 if (hw_if->dev_read(channel))
1871                         break;
1872
1873                 received++;
1874                 ring->cur++;
1875                 ring->dirty++;
1876
1877                 incomplete = XGMAC_GET_BITS(packet->attributes,
1878                                             RX_PACKET_ATTRIBUTES,
1879                                             INCOMPLETE);
1880                 context_next = XGMAC_GET_BITS(packet->attributes,
1881                                               RX_PACKET_ATTRIBUTES,
1882                                               CONTEXT_NEXT);
1883                 context = XGMAC_GET_BITS(packet->attributes,
1884                                          RX_PACKET_ATTRIBUTES,
1885                                          CONTEXT);
1886
1887                 /* Earlier error, just drain the remaining data */
1888                 if ((incomplete || context_next) && error)
1889                         goto read_again;
1890
1891                 if (error || packet->errors) {
1892                         if (packet->errors)
1893                                 DBGPR("Error in received packet\n");
1894                         dev_kfree_skb(skb);
1895                         goto next_packet;
1896                 }
1897
1898                 if (!context) {
1899                         put_len = rdata->len - len;
1900                         len += put_len;
1901
1902                         if (!skb) {
1903                                 dma_sync_single_for_cpu(pdata->dev,
1904                                                         rdata->rx_hdr.dma,
1905                                                         rdata->rx_hdr.dma_len,
1906                                                         DMA_FROM_DEVICE);
1907
1908                                 skb = xgbe_create_skb(pdata, rdata, &put_len);
1909                                 if (!skb) {
1910                                         error = 1;
1911                                         goto read_again;
1912                                 }
1913                         }
1914
1915                         if (put_len) {
1916                                 dma_sync_single_for_cpu(pdata->dev,
1917                                                         rdata->rx_buf.dma,
1918                                                         rdata->rx_buf.dma_len,
1919                                                         DMA_FROM_DEVICE);
1920
1921                                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
1922                                                 rdata->rx_buf.pa.pages,
1923                                                 rdata->rx_buf.pa.pages_offset,
1924                                                 put_len, rdata->rx_buf.dma_len);
1925                                 rdata->rx_buf.pa.pages = NULL;
1926                         }
1927                 }
1928
1929                 if (incomplete || context_next)
1930                         goto read_again;
1931
1932                 /* Stray Context Descriptor? */
1933                 if (!skb)
1934                         goto next_packet;
1935
1936                 /* Be sure we don't exceed the configured MTU */
1937                 max_len = netdev->mtu + ETH_HLEN;
1938                 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1939                     (skb->protocol == htons(ETH_P_8021Q)))
1940                         max_len += VLAN_HLEN;
1941
1942                 if (skb->len > max_len) {
1943                         DBGPR("packet length exceeds configured MTU\n");
1944                         dev_kfree_skb(skb);
1945                         goto next_packet;
1946                 }
1947
1948 #ifdef XGMAC_ENABLE_RX_PKT_DUMP
1949                 xgbe_print_pkt(netdev, skb, false);
1950 #endif
1951
1952                 skb_checksum_none_assert(skb);
1953                 if (XGMAC_GET_BITS(packet->attributes,
1954                                    RX_PACKET_ATTRIBUTES, CSUM_DONE))
1955                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1956
1957                 if (XGMAC_GET_BITS(packet->attributes,
1958                                    RX_PACKET_ATTRIBUTES, VLAN_CTAG))
1959                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1960                                                packet->vlan_ctag);
1961
1962                 if (XGMAC_GET_BITS(packet->attributes,
1963                                    RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
1964                         u64 nsec;
1965
1966                         nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1967                                                     packet->rx_tstamp);
1968                         hwtstamps = skb_hwtstamps(skb);
1969                         hwtstamps->hwtstamp = ns_to_ktime(nsec);
1970                 }
1971
1972                 if (XGMAC_GET_BITS(packet->attributes,
1973                                    RX_PACKET_ATTRIBUTES, RSS_HASH))
1974                         skb_set_hash(skb, packet->rss_hash,
1975                                      packet->rss_hash_type);
1976
1977                 skb->dev = netdev;
1978                 skb->protocol = eth_type_trans(skb, netdev);
1979                 skb_record_rx_queue(skb, channel->queue_index);
1980                 skb_mark_napi_id(skb, napi);
1981
1982                 netdev->last_rx = jiffies;
1983                 napi_gro_receive(napi, skb);
1984
1985 next_packet:
1986                 packet_count++;
1987         }
1988
1989         /* Check if we need to save state before leaving */
1990         if (received && (incomplete || context_next)) {
1991                 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1992                 rdata->state_saved = 1;
1993                 rdata->state.incomplete = incomplete;
1994                 rdata->state.context_next = context_next;
1995                 rdata->state.skb = skb;
1996                 rdata->state.len = len;
1997                 rdata->state.error = error;
1998         }
1999
2000         DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
2001
2002         return packet_count;
2003 }
2004
2005 static int xgbe_one_poll(struct napi_struct *napi, int budget)
2006 {
2007         struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
2008                                                     napi);
2009         int processed = 0;
2010
2011         DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
2012
2013         /* Cleanup Tx ring first */
2014         xgbe_tx_poll(channel);
2015
2016         /* Process Rx ring next */
2017         processed = xgbe_rx_poll(channel, budget);
2018
2019         /* If we processed everything, we are done */
2020         if (processed < budget) {
2021                 /* Turn off polling */
2022                 napi_complete(napi);
2023
2024                 /* Enable Tx and Rx interrupts */
2025                 enable_irq(channel->dma_irq);
2026         }
2027
2028         DBGPR("<--xgbe_one_poll: received = %d\n", processed);
2029
2030         return processed;
2031 }
2032
2033 static int xgbe_all_poll(struct napi_struct *napi, int budget)
2034 {
2035         struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
2036                                                    napi);
2037         struct xgbe_channel *channel;
2038         int ring_budget;
2039         int processed, last_processed;
2040         unsigned int i;
2041
2042         DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
2043
2044         processed = 0;
2045         ring_budget = budget / pdata->rx_ring_count;
2046         do {
2047                 last_processed = processed;
2048
2049                 channel = pdata->channel;
2050                 for (i = 0; i < pdata->channel_count; i++, channel++) {
2051                         /* Cleanup Tx ring first */
2052                         xgbe_tx_poll(channel);
2053
2054                         /* Process Rx ring next */
2055                         if (ring_budget > (budget - processed))
2056                                 ring_budget = budget - processed;
2057                         processed += xgbe_rx_poll(channel, ring_budget);
2058                 }
2059         } while ((processed < budget) && (processed != last_processed));
2060
2061         /* If we processed everything, we are done */
2062         if (processed < budget) {
2063                 /* Turn off polling */
2064                 napi_complete(napi);
2065
2066                 /* Enable Tx and Rx interrupts */
2067                 xgbe_enable_rx_tx_ints(pdata);
2068         }
2069
2070         DBGPR("<--xgbe_all_poll: received = %d\n", processed);
2071
2072         return processed;
2073 }
2074
2075 void xgbe_dump_tx_desc(struct xgbe_ring *ring, unsigned int idx,
2076                        unsigned int count, unsigned int flag)
2077 {
2078         struct xgbe_ring_data *rdata;
2079         struct xgbe_ring_desc *rdesc;
2080
2081         while (count--) {
2082                 rdata = XGBE_GET_DESC_DATA(ring, idx);
2083                 rdesc = rdata->rdesc;
2084                 pr_alert("TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
2085                          (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
2086                          le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
2087                          le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
2088                 idx++;
2089         }
2090 }
2091
2092 void xgbe_dump_rx_desc(struct xgbe_ring *ring, struct xgbe_ring_desc *desc,
2093                        unsigned int idx)
2094 {
2095         pr_alert("RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", idx,
2096                  le32_to_cpu(desc->desc0), le32_to_cpu(desc->desc1),
2097                  le32_to_cpu(desc->desc2), le32_to_cpu(desc->desc3));
2098 }
2099
2100 void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
2101 {
2102         struct ethhdr *eth = (struct ethhdr *)skb->data;
2103         unsigned char *buf = skb->data;
2104         unsigned char buffer[128];
2105         unsigned int i, j;
2106
2107         netdev_alert(netdev, "\n************** SKB dump ****************\n");
2108
2109         netdev_alert(netdev, "%s packet of %d bytes\n",
2110                      (tx_rx ? "TX" : "RX"), skb->len);
2111
2112         netdev_alert(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
2113         netdev_alert(netdev, "Src MAC addr: %pM\n", eth->h_source);
2114         netdev_alert(netdev, "Protocol: 0x%04hx\n", ntohs(eth->h_proto));
2115
2116         for (i = 0, j = 0; i < skb->len;) {
2117                 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
2118                               buf[i++]);
2119
2120                 if ((i % 32) == 0) {
2121                         netdev_alert(netdev, "  0x%04x: %s\n", i - 32, buffer);
2122                         j = 0;
2123                 } else if ((i % 16) == 0) {
2124                         buffer[j++] = ' ';
2125                         buffer[j++] = ' ';
2126                 } else if ((i % 4) == 0) {
2127                         buffer[j++] = ' ';
2128                 }
2129         }
2130         if (i % 32)
2131                 netdev_alert(netdev, "  0x%04x: %s\n", i - (i % 32), buffer);
2132
2133         netdev_alert(netdev, "\n************** SKB dump ****************\n");
2134 }