drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sizes.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/timer.h>
  30 #include <linux/clk.h>
  31 #include <linux/of.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/of_device.h>
  34 #include <linux/omap-dma.h>
  35 #include <linux/mmc/host.h>
  36 #include <linux/mmc/core.h>
  37 #include <linux/mmc/mmc.h>
  38 #include <linux/io.h>
  39 #include <linux/gpio.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/pinctrl/consumer.h>
  42 #include <linux/pm_runtime.h>
  43 #include <linux/platform_data/mmc-omap.h>
  44
  45 /* OMAP HSMMC Host Controller Registers */
  46 #define OMAP_HSMMC_SYSSTATUS    0x0014
  47 #define OMAP_HSMMC_CON          0x002C
  48 #define OMAP_HSMMC_BLK          0x0104
  49 #define OMAP_HSMMC_ARG          0x0108
  50 #define OMAP_HSMMC_CMD          0x010C
  51 #define OMAP_HSMMC_RSP10        0x0110
  52 #define OMAP_HSMMC_RSP32        0x0114
  53 #define OMAP_HSMMC_RSP54        0x0118
  54 #define OMAP_HSMMC_RSP76        0x011C
  55 #define OMAP_HSMMC_DATA         0x0120
  56 #define OMAP_HSMMC_HCTL         0x0128
  57 #define OMAP_HSMMC_SYSCTL       0x012C
  58 #define OMAP_HSMMC_STAT         0x0130
  59 #define OMAP_HSMMC_IE           0x0134
  60 #define OMAP_HSMMC_ISE          0x0138
  61 #define OMAP_HSMMC_CAPA         0x0140
  62
  63 #define VS18                    (1 << 26)
  64 #define VS30                    (1 << 25)
  65 #define HSS                     (1 << 21)
  66 #define SDVS18                  (0x5 << 9)
  67 #define SDVS30                  (0x6 << 9)
  68 #define SDVS33                  (0x7 << 9)
  69 #define SDVS_MASK               0x00000E00
  70 #define SDVSCLR                 0xFFFFF1FF
  71 #define SDVSDET                 0x00000400
  72 #define AUTOIDLE                0x1
  73 #define SDBP                    (1 << 8)
  74 #define DTO                     0xe
  75 #define ICE                     0x1
  76 #define ICS                     0x2
  77 #define CEN                     (1 << 2)
  78 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
  79 #define CLKD_MASK               0x0000FFC0
  80 #define CLKD_SHIFT              6
  81 #define DTO_MASK                0x000F0000
  82 #define DTO_SHIFT               16
  83 #define INIT_STREAM             (1 << 1)
  84 #define DP_SELECT               (1 << 21)
  85 #define DDIR                    (1 << 4)
  86 #define DMAE                    0x1
  87 #define MSBS                    (1 << 5)
  88 #define BCE                     (1 << 1)
  89 #define FOUR_BIT                (1 << 1)
  90 #define HSPE                    (1 << 2)
  91 #define DDR                     (1 << 19)
  92 #define DW8                     (1 << 5)
  93 #define OD                      0x1
  94 #define STAT_CLEAR              0xFFFFFFFF
  95 #define INIT_STREAM_CMD         0x00000000
  96 #define DUAL_VOLT_OCR_BIT       7
  97 #define SRC                     (1 << 25)
  98 #define SRD                     (1 << 26)
  99 #define SOFTRESET               (1 << 1)
 100 #define RESETDONE               (1 << 0)
 101
 102 /* Interrupt masks for IE and ISE register */
 103 #define CC_EN                   (1 << 0)
 104 #define TC_EN                   (1 << 1)
 105 #define BWR_EN                  (1 << 4)
 106 #define BRR_EN                  (1 << 5)
 107 #define ERR_EN                  (1 << 15)
 108 #define CTO_EN                  (1 << 16)
 109 #define CCRC_EN                 (1 << 17)
 110 #define CEB_EN                  (1 << 18)
 111 #define CIE_EN                  (1 << 19)
 112 #define DTO_EN                  (1 << 20)
 113 #define DCRC_EN                 (1 << 21)
 114 #define DEB_EN                  (1 << 22)
 115 #define CERR_EN                 (1 << 28)
 116 #define BADA_EN                 (1 << 29)
 117
 118 #define INT_EN_MASK             (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
 119                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
 120                 BRR_EN | BWR_EN | TC_EN | CC_EN)
 121
 122 #define MMC_AUTOSUSPEND_DELAY   100
 123 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
 124 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 125 #define OMAP_MMC_MIN_CLOCK      400000
 126 #define OMAP_MMC_MAX_CLOCK      52000000
 127 #define DRIVER_NAME             "omap_hsmmc"
 128
 129 /*
 130  * One controller can have multiple slots, like on some omap boards using
 131  * omap.c controller driver. Luckily this is not currently done on any known
 132  * omap_hsmmc.c device.
 133  */
 134 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 135
 136 /*
 137  * MMC Host controller read/write API's
 138  */
 139 #define OMAP_HSMMC_READ(base, reg)      \
 140         __raw_readl((base) + OMAP_HSMMC_##reg)
 141
 142 #define OMAP_HSMMC_WRITE(base, reg, val) \
 143         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 144
 145 struct omap_hsmmc_next {
 146         unsigned int    dma_len;
 147         s32             cookie;
 148 };
 149
 150 struct omap_hsmmc_host {
 151         struct  device          *dev;
 152         struct  mmc_host        *mmc;
 153         struct  mmc_request     *mrq;
 154         struct  mmc_command     *cmd;
 155         struct  mmc_data        *data;
 156         struct  clk             *fclk;
 157         struct  clk             *dbclk;
 158         /*
 159          * vcc == configured supply
 160          * vcc_aux == optional
 161          *   -  MMC1, supply for DAT4..DAT7
 162          *   -  MMC2/MMC2, external level shifter voltage supply, for
 163          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 164          */
 165         struct  regulator       *vcc;
 166         struct  regulator       *vcc_aux;
 167         int                     pbias_disable;
 168         void    __iomem         *base;
 169         resource_size_t         mapbase;
 170         spinlock_t              irq_lock; /* Prevent races with irq handler */
 171         unsigned int            dma_len;
 172         unsigned int            dma_sg_idx;
 173         unsigned char           bus_mode;
 174         unsigned char           power_mode;
 175         int                     suspended;
 176         u32                     con;
 177         u32                     hctl;
 178         u32                     sysctl;
 179         u32                     capa;
 180         int                     irq;
 181         int                     use_dma, dma_ch;
 182         struct dma_chan         *tx_chan;
 183         struct dma_chan         *rx_chan;
 184         int                     slot_id;
 185         int                     response_busy;
 186         int                     context_loss;
 187         int                     protect_card;
 188         int                     reqs_blocked;
 189         int                     use_reg;
 190         int                     req_in_progress;
 191         struct omap_hsmmc_next  next_data;
 192         struct  omap_mmc_platform_data  *pdata;
 193 };
 194
 195 struct omap_mmc_of_data {
 196         u32 reg_offset;
 197         u8 controller_flags;
 198 };
 199
 200 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 201 {
 202         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 203         struct omap_mmc_platform_data *mmc = host->pdata;
 204
 205         /* NOTE: assumes card detect signal is active-low */
 206         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 207 }
 208
 209 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 210 {
 211         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 212         struct omap_mmc_platform_data *mmc = host->pdata;
 213
 214         /* NOTE: assumes write protect signal is active-high */
 215         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 216 }
 217
 218 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 219 {
 220         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 221         struct omap_mmc_platform_data *mmc = host->pdata;
 222
 223         /* NOTE: assumes card detect signal is active-low */
 224         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 225 }
 226
 227 #ifdef CONFIG_PM
 228
 229 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 230 {
 231         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 232         struct omap_mmc_platform_data *mmc = host->pdata;
 233
 234         disable_irq(mmc->slots[0].card_detect_irq);
 235         return 0;
 236 }
 237
 238 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 239 {
 240         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 241         struct omap_mmc_platform_data *mmc = host->pdata;
 242
 243         enable_irq(mmc->slots[0].card_detect_irq);
 244         return 0;
 245 }
 246
 247 #else
 248
 249 #define omap_hsmmc_suspend_cdirq        NULL
 250 #define omap_hsmmc_resume_cdirq         NULL
 251
 252 #endif
 253
 254 #ifdef CONFIG_REGULATOR
 255
 256 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 257                                    int vdd)
 258 {
 259         struct omap_hsmmc_host *host =
 260                 platform_get_drvdata(to_platform_device(dev));
 261         int ret = 0;
 262
 263         /*
 264          * If we don't see a Vcc regulator, assume it's a fixed
 265          * voltage always-on regulator.
 266          */
 267         if (!host->vcc)
 268                 return 0;
 269         /*
 270          * With DT, never turn OFF the regulator for MMC1. This is because
 271          * the pbias cell programming support is still missing when
 272          * booting with Device tree
 273          */
 274         if (host->pbias_disable && !vdd)
 275                 return 0;
 276
 277         if (mmc_slot(host).before_set_reg)
 278                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 279
 280         /*
 281          * Assume Vcc regulator is used only to power the card ... OMAP
 282          * VDDS is used to power the pins, optionally with a transceiver to
 283          * support cards using voltages other than VDDS (1.8V nominal).  When a
 284          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 285          *
 286          * In some cases this regulator won't support enable/disable;
 287          * e.g. it's a fixed rail for a WLAN chip.
 288          *
 289          * In other cases vcc_aux switches interface power.  Example, for
 290          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 291          * chips/cards need an interface voltage rail too.
 292          */
 293         if (power_on) {
 294                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 295                 /* Enable interface voltage rail, if needed */
 296                 if (ret == 0 && host->vcc_aux) {
 297                         ret = regulator_enable(host->vcc_aux);
 298                         if (ret < 0)
 299                                 ret = mmc_regulator_set_ocr(host->mmc,
 300                                                         host->vcc, 0);
 301                 }
 302         } else {
 303                 /* Shut down the rail */
 304                 if (host->vcc_aux)
 305                         ret = regulator_disable(host->vcc_aux);
 306                 if (!ret) {
 307                         /* Then proceed to shut down the local regulator */
 308                         ret = mmc_regulator_set_ocr(host->mmc,
 309                                                 host->vcc, 0);
 310                 }
 311         }
 312
 313         if (mmc_slot(host).after_set_reg)
 314                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 315
 316         return ret;
 317 }
 318
 319 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 320 {
 321         struct regulator *reg;
 322         int ocr_value = 0;
 323
 324         reg = regulator_get(host->dev, "vmmc");
 325         if (IS_ERR(reg)) {
 326                 dev_err(host->dev, "vmmc regulator missing\n");
 327                 return PTR_ERR(reg);
 328         } else {
 329                 mmc_slot(host).set_power = omap_hsmmc_set_power;
 330                 host->vcc = reg;
 331                 ocr_value = mmc_regulator_get_ocrmask(reg);
 332                 if (!mmc_slot(host).ocr_mask) {
 333                         mmc_slot(host).ocr_mask = ocr_value;
 334                 } else {
 335                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 336                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 337                                         mmc_slot(host).ocr_mask);
 338                                 mmc_slot(host).ocr_mask = 0;
 339                                 return -EINVAL;
 340                         }
 341                 }
 342
 343                 /* Allow an aux regulator */
 344                 reg = regulator_get(host->dev, "vmmc_aux");
 345                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 346
 347                 /* For eMMC do not power off when not in sleep state */
 348                 if (mmc_slot(host).no_regulator_off_init)
 349                         return 0;
 350                 /*
 351                 * UGLY HACK:  workaround regulator framework bugs.
 352                 * When the bootloader leaves a supply active, it's
 353                 * initialized with zero usecount ... and we can't
 354                 * disable it without first enabling it.  Until the
 355                 * framework is fixed, we need a workaround like this
 356                 * (which is safe for MMC, but not in general).
 357                 */
 358                 if (regulator_is_enabled(host->vcc) > 0 ||
 359                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 360                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 361
 362                         mmc_slot(host).set_power(host->dev, host->slot_id,
 363                                                  1, vdd);
 364                         mmc_slot(host).set_power(host->dev, host->slot_id,
 365                                                  0, 0);
 366                 }
 367         }
 368
 369         return 0;
 370 }
 371
 372 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 373 {
 374         regulator_put(host->vcc);
 375         regulator_put(host->vcc_aux);
 376         mmc_slot(host).set_power = NULL;
 377 }
 378
 379 static inline int omap_hsmmc_have_reg(void)
 380 {
 381         return 1;
 382 }
 383
 384 #else
 385
 386 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 387 {
 388         return -EINVAL;
 389 }
 390
 391 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 392 {
 393 }
 394
 395 static inline int omap_hsmmc_have_reg(void)
 396 {
 397         return 0;
 398 }
 399
 400 #endif
 401
 402 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 403 {
 404         int ret;
 405
 406         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 407                 if (pdata->slots[0].cover)
 408                         pdata->slots[0].get_cover_state =
 409                                         omap_hsmmc_get_cover_state;
 410                 else
 411                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 412                 pdata->slots[0].card_detect_irq =
 413                                 gpio_to_irq(pdata->slots[0].switch_pin);
 414                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 415                 if (ret)
 416                         return ret;
 417                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 418                 if (ret)
 419                         goto err_free_sp;
 420         } else
 421                 pdata->slots[0].switch_pin = -EINVAL;
 422
 423         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 424                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 425                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 426                 if (ret)
 427                         goto err_free_cd;
 428                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 429                 if (ret)
 430                         goto err_free_wp;
 431         } else
 432                 pdata->slots[0].gpio_wp = -EINVAL;
 433
 434         return 0;
 435
 436 err_free_wp:
 437         gpio_free(pdata->slots[0].gpio_wp);
 438 err_free_cd:
 439         if (gpio_is_valid(pdata->slots[0].switch_pin))
 440 err_free_sp:
 441                 gpio_free(pdata->slots[0].switch_pin);
 442         return ret;
 443 }
 444
 445 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 446 {
 447         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 448                 gpio_free(pdata->slots[0].gpio_wp);
 449         if (gpio_is_valid(pdata->slots[0].switch_pin))
 450                 gpio_free(pdata->slots[0].switch_pin);
 451 }
 452
 453 /*
 454  * Start clock to the card
 455  */
 456 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 457 {
 458         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 459                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 460 }
 461
 462 /*
 463  * Stop clock to the card
 464  */
 465 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 466 {
 467         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 468                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 469         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 470                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 471 }
 472
 473 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 474                                   struct mmc_command *cmd)
 475 {
 476         unsigned int irq_mask;
 477
 478         if (host->use_dma)
 479                 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
 480         else
 481                 irq_mask = INT_EN_MASK;
 482
 483         /* Disable timeout for erases */
 484         if (cmd->opcode == MMC_ERASE)
 485                 irq_mask &= ~DTO_EN;
 486
 487         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 488         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 489         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 490 }
 491
 492 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 493 {
 494         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 495         OMAP_HSMMC_WRITE(host->base, IE, 0);
 496         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 497 }
 498
 499 /* Calculate divisor for the given clock frequency */
 500 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 501 {
 502         u16 dsor = 0;
 503
 504         if (ios->clock) {
 505                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 506                 if (dsor > CLKD_MAX)
 507                         dsor = CLKD_MAX;
 508         }
 509
 510         return dsor;
 511 }
 512
 513 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 514 {
 515         struct mmc_ios *ios = &host->mmc->ios;
 516         unsigned long regval;
 517         unsigned long timeout;
 518         unsigned long clkdiv;
 519
 520         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 521
 522         omap_hsmmc_stop_clock(host);
 523
 524         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 525         regval = regval & ~(CLKD_MASK | DTO_MASK);
 526         clkdiv = calc_divisor(host, ios);
 527         regval = regval | (clkdiv << 6) | (DTO << 16);
 528         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 529         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 530                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 531
 532         /* Wait till the ICS bit is set */
 533         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 534         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 535                 && time_before(jiffies, timeout))
 536                 cpu_relax();
 537
 538         /*
 539          * Enable High-Speed Support
 540          * Pre-Requisites
 541          *      - Controller should support High-Speed-Enable Bit
 542          *      - Controller should not be using DDR Mode
 543          *      - Controller should advertise that it supports High Speed
 544          *        in capabilities register
 545          *      - MMC/SD clock coming out of controller > 25MHz
 546          */
 547         if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
 548             (ios->timing != MMC_TIMING_UHS_DDR50) &&
 549             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 550                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 551                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 552                         regval |= HSPE;
 553                 else
 554                         regval &= ~HSPE;
 555
 556                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 557         }
 558
 559         omap_hsmmc_start_clock(host);
 560 }
 561
 562 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 563 {
 564         struct mmc_ios *ios = &host->mmc->ios;
 565         u32 con;
 566
 567         con = OMAP_HSMMC_READ(host->base, CON);
 568         if (ios->timing == MMC_TIMING_UHS_DDR50)
 569                 con |= DDR;     /* configure in DDR mode */
 570         else
 571                 con &= ~DDR;
 572         switch (ios->bus_width) {
 573         case MMC_BUS_WIDTH_8:
 574                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 575                 break;
 576         case MMC_BUS_WIDTH_4:
 577                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 578                 OMAP_HSMMC_WRITE(host->base, HCTL,
 579                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 580                 break;
 581         case MMC_BUS_WIDTH_1:
 582                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 583                 OMAP_HSMMC_WRITE(host->base, HCTL,
 584                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 585                 break;
 586         }
 587 }
 588
 589 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 590 {
 591         struct mmc_ios *ios = &host->mmc->ios;
 592         u32 con;
 593
 594         con = OMAP_HSMMC_READ(host->base, CON);
 595         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 596                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 597         else
 598                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 599 }
 600
 601 #ifdef CONFIG_PM
 602
 603 /*
 604  * Restore the MMC host context, if it was lost as result of a
 605  * power state change.
 606  */
 607 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 608 {
 609         struct mmc_ios *ios = &host->mmc->ios;
 610         u32 hctl, capa;
 611         unsigned long timeout;
 612
 613         if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
 614                 return 1;
 615
 616         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
 617             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
 618             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
 619             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
 620                 return 0;
 621
 622         host->context_loss++;
 623
 624         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 625                 if (host->power_mode != MMC_POWER_OFF &&
 626                     (1 << ios->vdd) <= MMC_VDD_23_24)
 627                         hctl = SDVS18;
 628                 else
 629                         hctl = SDVS30;
 630                 capa = VS30 | VS18;
 631         } else {
 632                 hctl = SDVS18;
 633                 capa = VS18;
 634         }
 635
 636         OMAP_HSMMC_WRITE(host->base, HCTL,
 637                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 638
 639         OMAP_HSMMC_WRITE(host->base, CAPA,
 640                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 641
 642         OMAP_HSMMC_WRITE(host->base, HCTL,
 643                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 644
 645         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 646         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 647                 && time_before(jiffies, timeout))
 648                 ;
 649
 650         omap_hsmmc_disable_irq(host);
 651
 652         /* Do not initialize card-specific things if the power is off */
 653         if (host->power_mode == MMC_POWER_OFF)
 654                 goto out;
 655
 656         omap_hsmmc_set_bus_width(host);
 657
 658         omap_hsmmc_set_clock(host);
 659
 660         omap_hsmmc_set_bus_mode(host);
 661
 662 out:
 663         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
 664                 host->context_loss);
 665         return 0;
 666 }
 667
 668 /*
 669  * Save the MMC host context (store the number of power state changes so far).
 670  */
 671 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 672 {
 673         host->con =  OMAP_HSMMC_READ(host->base, CON);
 674         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
 675         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
 676         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
 677 }
 678
 679 #else
 680
 681 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 682 {
 683         return 0;
 684 }
 685
 686 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 687 {
 688 }
 689
 690 #endif
 691
 692 /*
 693  * Send init stream sequence to card
 694  * before sending IDLE command
 695  */
 696 static void send_init_stream(struct omap_hsmmc_host *host)
 697 {
 698         int reg = 0;
 699         unsigned long timeout;
 700
 701         if (host->protect_card)
 702                 return;
 703
 704         disable_irq(host->irq);
 705
 706         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 707         OMAP_HSMMC_WRITE(host->base, CON,
 708                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 709         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 710
 711         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 712         while ((reg != CC_EN) && time_before(jiffies, timeout))
 713                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
 714
 715         OMAP_HSMMC_WRITE(host->base, CON,
 716                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 717
 718         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 719         OMAP_HSMMC_READ(host->base, STAT);
 720
 721         enable_irq(host->irq);
 722 }
 723
 724 static inline
 725 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 726 {
 727         int r = 1;
 728
 729         if (mmc_slot(host).get_cover_state)
 730                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 731         return r;
 732 }
 733
 734 static ssize_t
 735 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 736                            char *buf)
 737 {
 738         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 739         struct omap_hsmmc_host *host = mmc_priv(mmc);
 740
 741         return sprintf(buf, "%s\n",
 742                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 743 }
 744
 745 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 746
 747 static ssize_t
 748 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 749                         char *buf)
 750 {
 751         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 752         struct omap_hsmmc_host *host = mmc_priv(mmc);
 753
 754         return sprintf(buf, "%s\n", mmc_slot(host).name);
 755 }
 756
 757 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 758
 759 /*
 760  * Configure the response type and send the cmd.
 761  */
 762 static void
 763 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 764         struct mmc_data *data)
 765 {
 766         int cmdreg = 0, resptype = 0, cmdtype = 0;
 767
 768         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 769                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 770         host->cmd = cmd;
 771
 772         omap_hsmmc_enable_irq(host, cmd);
 773
 774         host->response_busy = 0;
 775         if (cmd->flags & MMC_RSP_PRESENT) {
 776                 if (cmd->flags & MMC_RSP_136)
 777                         resptype = 1;
 778                 else if (cmd->flags & MMC_RSP_BUSY) {
 779                         resptype = 3;
 780                         host->response_busy = 1;
 781                 } else
 782                         resptype = 2;
 783         }
 784
 785         /*
 786          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 787          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 788          * a val of 0x3, rest 0x0.
 789          */
 790         if (cmd == host->mrq->stop)
 791                 cmdtype = 0x3;
 792
 793         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 794
 795         if (data) {
 796                 cmdreg |= DP_SELECT | MSBS | BCE;
 797                 if (data->flags & MMC_DATA_READ)
 798                         cmdreg |= DDIR;
 799                 else
 800                         cmdreg &= ~(DDIR);
 801         }
 802
 803         if (host->use_dma)
 804                 cmdreg |= DMAE;
 805
 806         host->req_in_progress = 1;
 807
 808         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 809         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 810 }
 811
 812 static int
 813 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 814 {
 815         if (data->flags & MMC_DATA_WRITE)
 816                 return DMA_TO_DEVICE;
 817         else
 818                 return DMA_FROM_DEVICE;
 819 }
 820
 821 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 822         struct mmc_data *data)
 823 {
 824         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 825 }
 826
 827 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 828 {
 829         int dma_ch;
 830         unsigned long flags;
 831
 832         spin_lock_irqsave(&host->irq_lock, flags);
 833         host->req_in_progress = 0;
 834         dma_ch = host->dma_ch;
 835         spin_unlock_irqrestore(&host->irq_lock, flags);
 836
 837         omap_hsmmc_disable_irq(host);
 838         /* Do not complete the request if DMA is still in progress */
 839         if (mrq->data && host->use_dma && dma_ch != -1)
 840                 return;
 841         host->mrq = NULL;
 842         mmc_request_done(host->mmc, mrq);
 843 }
 844
 845 /*
 846  * Notify the transfer complete to MMC core
 847  */
 848 static void
 849 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 850 {
 851         if (!data) {
 852                 struct mmc_request *mrq = host->mrq;
 853
 854                 /* TC before CC from CMD6 - don't know why, but it happens */
 855                 if (host->cmd && host->cmd->opcode == 6 &&
 856                     host->response_busy) {
 857                         host->response_busy = 0;
 858                         return;
 859                 }
 860
 861                 omap_hsmmc_request_done(host, mrq);
 862                 return;
 863         }
 864
 865         host->data = NULL;
 866
 867         if (!data->error)
 868                 data->bytes_xfered += data->blocks * (data->blksz);
 869         else
 870                 data->bytes_xfered = 0;
 871
 872         if (!data->stop) {
 873                 omap_hsmmc_request_done(host, data->mrq);
 874                 return;
 875         }
 876         omap_hsmmc_start_command(host, data->stop, NULL);
 877 }
 878
 879 /*
 880  * Notify the core about command completion
 881  */
 882 static void
 883 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 884 {
 885         host->cmd = NULL;
 886
 887         if (cmd->flags & MMC_RSP_PRESENT) {
 888                 if (cmd->flags & MMC_RSP_136) {
 889                         /* response type 2 */
 890                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 891                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 892                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 893                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 894                 } else {
 895                         /* response types 1, 1b, 3, 4, 5, 6 */
 896                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 897                 }
 898         }
 899         if ((host->data == NULL && !host->response_busy) || cmd->error)
 900                 omap_hsmmc_request_done(host, cmd->mrq);
 901 }
 902
 903 /*
 904  * DMA clean up for command errors
 905  */
 906 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 907 {
 908         int dma_ch;
 909         unsigned long flags;
 910
 911         host->data->error = errno;
 912
 913         spin_lock_irqsave(&host->irq_lock, flags);
 914         dma_ch = host->dma_ch;
 915         host->dma_ch = -1;
 916         spin_unlock_irqrestore(&host->irq_lock, flags);
 917
 918         if (host->use_dma && dma_ch != -1) {
 919                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
 920
 921                 dmaengine_terminate_all(chan);
 922                 dma_unmap_sg(chan->device->dev,
 923                         host->data->sg, host->data->sg_len,
 924                         omap_hsmmc_get_dma_dir(host, host->data));
 925
 926                 host->data->host_cookie = 0;
 927         }
 928         host->data = NULL;
 929 }
 930
 931 /*
 932  * Readable error output
 933  */
 934 #ifdef CONFIG_MMC_DEBUG
 935 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 936 {
 937         /* --- means reserved bit without definition at documentation */
 938         static const char *omap_hsmmc_status_bits[] = {
 939                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 940                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 941                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 942                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 943         };
 944         char res[256];
 945         char *buf = res;
 946         int len, i;
 947
 948         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 949         buf += len;
 950
 951         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 952                 if (status & (1 << i)) {
 953                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 954                         buf += len;
 955                 }
 956
 957         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
 958 }
 959 #else
 960 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 961                                              u32 status)
 962 {
 963 }
 964 #endif  /* CONFIG_MMC_DEBUG */
 965
 966 /*
 967  * MMC controller internal state machines reset
 968  *
 969  * Used to reset command or data internal state machines, using respectively
 970  *  SRC or SRD bit of SYSCTL register
 971  * Can be called from interrupt context
 972  */
 973 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 974                                                    unsigned long bit)
 975 {
 976         unsigned long i = 0;
 977         unsigned long limit = MMC_TIMEOUT_US;
 978
 979         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 980                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 981
 982         /*
 983          * OMAP4 ES2 and greater has an updated reset logic.
 984          * Monitor a 0->1 transition first
 985          */
 986         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 987                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 988                                         && (i++ < limit))
 989                         udelay(1);
 990         }
 991         i = 0;
 992
 993         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 994                 (i++ < limit))
 995                 udelay(1);
 996
 997         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 998                 dev_err(mmc_dev(host->mmc),
 999                         "Timeout waiting on controller reset in %s\n",
1000                         __func__);
1001 }
1002
1003 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1004                                         int err, int end_cmd)
1005 {
1006         if (end_cmd) {
1007                 omap_hsmmc_reset_controller_fsm(host, SRC);
1008                 if (host->cmd)
1009                         host->cmd->error = err;
1010         }
1011
1012         if (host->data) {
1013                 omap_hsmmc_reset_controller_fsm(host, SRD);
1014                 omap_hsmmc_dma_cleanup(host, err);
1015         } else if (host->mrq && host->mrq->cmd)
1016                 host->mrq->cmd->error = err;
1017 }
1018
1019 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1020 {
1021         struct mmc_data *data;
1022         int end_cmd = 0, end_trans = 0;
1023
1024         data = host->data;
1025         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1026
1027         if (status & ERR_EN) {
1028                 omap_hsmmc_dbg_report_irq(host, status);
1029
1030                 if (status & (CTO_EN | CCRC_EN))
1031                         end_cmd = 1;
1032                 if (status & (CTO_EN | DTO_EN))
1033                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1034                 else if (status & (CCRC_EN | DCRC_EN))
1035                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1036
1037                 if (host->data || host->response_busy) {
1038                         end_trans = !end_cmd;
1039                         host->response_busy = 0;
1040                 }
1041         }
1042
1043         OMAP_HSMMC_WRITE(host->base, STAT, status);
1044         if (end_cmd || ((status & CC_EN) && host->cmd))
1045                 omap_hsmmc_cmd_done(host, host->cmd);
1046         if ((end_trans || (status & TC_EN)) && host->mrq)
1047                 omap_hsmmc_xfer_done(host, data);
1048 }
1049
1050 /*
1051  * MMC controller IRQ handler
1052  */
1053 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1054 {
1055         struct omap_hsmmc_host *host = dev_id;
1056         int status;
1057
1058         status = OMAP_HSMMC_READ(host->base, STAT);
1059         while (status & INT_EN_MASK && host->req_in_progress) {
1060                 omap_hsmmc_do_irq(host, status);
1061
1062                 /* Flush posted write */
1063                 status = OMAP_HSMMC_READ(host->base, STAT);
1064         }
1065
1066         return IRQ_HANDLED;
1067 }
1068
1069 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1070 {
1071         unsigned long i;
1072
1073         OMAP_HSMMC_WRITE(host->base, HCTL,
1074                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1075         for (i = 0; i < loops_per_jiffy; i++) {
1076                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1077                         break;
1078                 cpu_relax();
1079         }
1080 }
1081
1082 /*
1083  * Switch MMC interface voltage ... only relevant for MMC1.
1084  *
1085  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1086  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1087  * Some chips, like eMMC ones, use internal transceivers.
1088  */
1089 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1090 {
1091         u32 reg_val = 0;
1092         int ret;
1093
1094         /* Disable the clocks */
1095         pm_runtime_put_sync(host->dev);
1096         if (host->dbclk)
1097                 clk_disable_unprepare(host->dbclk);
1098
1099         /* Turn the power off */
1100         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1101
1102         /* Turn the power ON with given VDD 1.8 or 3.0v */
1103         if (!ret)
1104                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1105                                                vdd);
1106         pm_runtime_get_sync(host->dev);
1107         if (host->dbclk)
1108                 clk_prepare_enable(host->dbclk);
1109
1110         if (ret != 0)
1111                 goto err;
1112
1113         OMAP_HSMMC_WRITE(host->base, HCTL,
1114                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1115         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1116
1117         /*
1118          * If a MMC dual voltage card is detected, the set_ios fn calls
1119          * this fn with VDD bit set for 1.8V. Upon card removal from the
1120          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1121          *
1122          * Cope with a bit of slop in the range ... per data sheets:
1123          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1124          *    but recommended values are 1.71V to 1.89V
1125          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1126          *    but recommended values are 2.7V to 3.3V
1127          *
1128          * Board setup code shouldn't permit anything very out-of-range.
1129          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1130          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1131          */
1132         if ((1 << vdd) <= MMC_VDD_23_24)
1133                 reg_val |= SDVS18;
1134         else
1135                 reg_val |= SDVS30;
1136
1137         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1138         set_sd_bus_power(host);
1139
1140         return 0;
1141 err:
1142         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1143         return ret;
1144 }
1145
1146 /* Protect the card while the cover is open */
1147 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1148 {
1149         if (!mmc_slot(host).get_cover_state)
1150                 return;
1151
1152         host->reqs_blocked = 0;
1153         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1154                 if (host->protect_card) {
1155                         dev_info(host->dev, "%s: cover is closed, "
1156                                          "card is now accessible\n",
1157                                          mmc_hostname(host->mmc));
1158                         host->protect_card = 0;
1159                 }
1160         } else {
1161                 if (!host->protect_card) {
1162                         dev_info(host->dev, "%s: cover is open, "
1163                                          "card is now inaccessible\n",
1164                                          mmc_hostname(host->mmc));
1165                         host->protect_card = 1;
1166                 }
1167         }
1168 }
1169
1170 /*
1171  * irq handler to notify the core about card insertion/removal
1172  */
1173 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1174 {
1175         struct omap_hsmmc_host *host = dev_id;
1176         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1177         int carddetect;
1178
1179         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1180
1181         if (slot->card_detect)
1182                 carddetect = slot->card_detect(host->dev, host->slot_id);
1183         else {
1184                 omap_hsmmc_protect_card(host);
1185                 carddetect = -ENOSYS;
1186         }
1187
1188         if (carddetect)
1189                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1190         else
1191                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1192         return IRQ_HANDLED;
1193 }
1194
1195 static void omap_hsmmc_dma_callback(void *param)
1196 {
1197         struct omap_hsmmc_host *host = param;
1198         struct dma_chan *chan;
1199         struct mmc_data *data;
1200         int req_in_progress;
1201
1202         spin_lock_irq(&host->irq_lock);
1203         if (host->dma_ch < 0) {
1204                 spin_unlock_irq(&host->irq_lock);
1205                 return;
1206         }
1207
1208         data = host->mrq->data;
1209         chan = omap_hsmmc_get_dma_chan(host, data);
1210         if (!data->host_cookie)
1211                 dma_unmap_sg(chan->device->dev,
1212                              data->sg, data->sg_len,
1213                              omap_hsmmc_get_dma_dir(host, data));
1214
1215         req_in_progress = host->req_in_progress;
1216         host->dma_ch = -1;
1217         spin_unlock_irq(&host->irq_lock);
1218
1219         /* If DMA has finished after TC, complete the request */
1220         if (!req_in_progress) {
1221                 struct mmc_request *mrq = host->mrq;
1222
1223                 host->mrq = NULL;
1224                 mmc_request_done(host->mmc, mrq);
1225         }
1226 }
1227
1228 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1229                                        struct mmc_data *data,
1230                                        struct omap_hsmmc_next *next,
1231                                        struct dma_chan *chan)
1232 {
1233         int dma_len;
1234
1235         if (!next && data->host_cookie &&
1236             data->host_cookie != host->next_data.cookie) {
1237                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1238                        " host->next_data.cookie %d\n",
1239                        __func__, data->host_cookie, host->next_data.cookie);
1240                 data->host_cookie = 0;
1241         }
1242
1243         /* Check if next job is already prepared */
1244         if (next || data->host_cookie != host->next_data.cookie) {
1245                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1246                                      omap_hsmmc_get_dma_dir(host, data));
1247
1248         } else {
1249                 dma_len = host->next_data.dma_len;
1250                 host->next_data.dma_len = 0;
1251         }
1252
1253
1254         if (dma_len == 0)
1255                 return -EINVAL;
1256
1257         if (next) {
1258                 next->dma_len = dma_len;
1259                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1260         } else
1261                 host->dma_len = dma_len;
1262
1263         return 0;
1264 }
1265
1266 /*
1267  * Routine to configure and start DMA for the MMC card
1268  */
1269 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1270                                         struct mmc_request *req)
1271 {
1272         struct dma_slave_config cfg;
1273         struct dma_async_tx_descriptor *tx;
1274         int ret = 0, i;
1275         struct mmc_data *data = req->data;
1276         struct dma_chan *chan;
1277
1278         /* Sanity check: all the SG entries must be aligned by block size. */
1279         for (i = 0; i < data->sg_len; i++) {
1280                 struct scatterlist *sgl;
1281
1282                 sgl = data->sg + i;
1283                 if (sgl->length % data->blksz)
1284                         return -EINVAL;
1285         }
1286         if ((data->blksz % 4) != 0)
1287                 /* REVISIT: The MMC buffer increments only when MSB is written.
1288                  * Return error for blksz which is non multiple of four.
1289                  */
1290                 return -EINVAL;
1291
1292         BUG_ON(host->dma_ch != -1);
1293
1294         chan = omap_hsmmc_get_dma_chan(host, data);
1295
1296         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1297         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1298         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1299         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1300         cfg.src_maxburst = data->blksz / 4;
1301         cfg.dst_maxburst = data->blksz / 4;
1302
1303         ret = dmaengine_slave_config(chan, &cfg);
1304         if (ret)
1305                 return ret;
1306
1307         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1308         if (ret)
1309                 return ret;
1310
1311         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1312                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1313                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1314         if (!tx) {
1315                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1316                 /* FIXME: cleanup */
1317                 return -1;
1318         }
1319
1320         tx->callback = omap_hsmmc_dma_callback;
1321         tx->callback_param = host;
1322
1323         /* Does not fail */
1324         dmaengine_submit(tx);
1325
1326         host->dma_ch = 1;
1327
1328         dma_async_issue_pending(chan);
1329
1330         return 0;
1331 }
1332
1333 static void set_data_timeout(struct omap_hsmmc_host *host,
1334                              unsigned int timeout_ns,
1335                              unsigned int timeout_clks)
1336 {
1337         unsigned int timeout, cycle_ns;
1338         uint32_t reg, clkd, dto = 0;
1339
1340         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1341         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1342         if (clkd == 0)
1343                 clkd = 1;
1344
1345         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1346         timeout = timeout_ns / cycle_ns;
1347         timeout += timeout_clks;
1348         if (timeout) {
1349                 while ((timeout & 0x80000000) == 0) {
1350                         dto += 1;
1351                         timeout <<= 1;
1352                 }
1353                 dto = 31 - dto;
1354                 timeout <<= 1;
1355                 if (timeout && dto)
1356                         dto += 1;
1357                 if (dto >= 13)
1358                         dto -= 13;
1359                 else
1360                         dto = 0;
1361                 if (dto > 14)
1362                         dto = 14;
1363         }
1364
1365         reg &= ~DTO_MASK;
1366         reg |= dto << DTO_SHIFT;
1367         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1368 }
1369
1370 /*
1371  * Configure block length for MMC/SD cards and initiate the transfer.
1372  */
1373 static int
1374 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1375 {
1376         int ret;
1377         host->data = req->data;
1378
1379         if (req->data == NULL) {
1380                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1381                 /*
1382                  * Set an arbitrary 100ms data timeout for commands with
1383                  * busy signal.
1384                  */
1385                 if (req->cmd->flags & MMC_RSP_BUSY)
1386                         set_data_timeout(host, 100000000U, 0);
1387                 return 0;
1388         }
1389
1390         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1391                                         | (req->data->blocks << 16));
1392         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1393
1394         if (host->use_dma) {
1395                 ret = omap_hsmmc_start_dma_transfer(host, req);
1396                 if (ret != 0) {
1397                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1398                         return ret;
1399                 }
1400         }
1401         return 0;
1402 }
1403
1404 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1405                                 int err)
1406 {
1407         struct omap_hsmmc_host *host = mmc_priv(mmc);
1408         struct mmc_data *data = mrq->data;
1409
1410         if (host->use_dma && data->host_cookie) {
1411                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1412
1413                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1414                              omap_hsmmc_get_dma_dir(host, data));
1415                 data->host_cookie = 0;
1416         }
1417 }
1418
1419 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1420                                bool is_first_req)
1421 {
1422         struct omap_hsmmc_host *host = mmc_priv(mmc);
1423
1424         if (mrq->data->host_cookie) {
1425                 mrq->data->host_cookie = 0;
1426                 return ;
1427         }
1428
1429         if (host->use_dma) {
1430                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1431
1432                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1433                                                 &host->next_data, c))
1434                         mrq->data->host_cookie = 0;
1435         }
1436 }
1437
1438 /*
1439  * Request function. for read/write operation
1440  */
1441 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1442 {
1443         struct omap_hsmmc_host *host = mmc_priv(mmc);
1444         int err;
1445
1446         BUG_ON(host->req_in_progress);
1447         BUG_ON(host->dma_ch != -1);
1448         if (host->protect_card) {
1449                 if (host->reqs_blocked < 3) {
1450                         /*
1451                          * Ensure the controller is left in a consistent
1452                          * state by resetting the command and data state
1453                          * machines.
1454                          */
1455                         omap_hsmmc_reset_controller_fsm(host, SRD);
1456                         omap_hsmmc_reset_controller_fsm(host, SRC);
1457                         host->reqs_blocked += 1;
1458                 }
1459                 req->cmd->error = -EBADF;
1460                 if (req->data)
1461                         req->data->error = -EBADF;
1462                 req->cmd->retries = 0;
1463                 mmc_request_done(mmc, req);
1464                 return;
1465         } else if (host->reqs_blocked)
1466                 host->reqs_blocked = 0;
1467         WARN_ON(host->mrq != NULL);
1468         host->mrq = req;
1469         err = omap_hsmmc_prepare_data(host, req);
1470         if (err) {
1471                 req->cmd->error = err;
1472                 if (req->data)
1473                         req->data->error = err;
1474                 host->mrq = NULL;
1475                 mmc_request_done(mmc, req);
1476                 return;
1477         }
1478
1479         omap_hsmmc_start_command(host, req->cmd, req->data);
1480 }
1481
1482 /* Routine to configure clock values. Exposed API to core */
1483 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1484 {
1485         struct omap_hsmmc_host *host = mmc_priv(mmc);
1486         int do_send_init_stream = 0;
1487
1488         pm_runtime_get_sync(host->dev);
1489
1490         if (ios->power_mode != host->power_mode) {
1491                 switch (ios->power_mode) {
1492                 case MMC_POWER_OFF:
1493                         mmc_slot(host).set_power(host->dev, host->slot_id,
1494                                                  0, 0);
1495                         break;
1496                 case MMC_POWER_UP:
1497                         mmc_slot(host).set_power(host->dev, host->slot_id,
1498                                                  1, ios->vdd);
1499                         break;
1500                 case MMC_POWER_ON:
1501                         do_send_init_stream = 1;
1502                         break;
1503                 }
1504                 host->power_mode = ios->power_mode;
1505         }
1506
1507         /* FIXME: set registers based only on changes to ios */
1508
1509         omap_hsmmc_set_bus_width(host);
1510
1511         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1512                 /* Only MMC1 can interface at 3V without some flavor
1513                  * of external transceiver; but they all handle 1.8V.
1514                  */
1515                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1516                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1517                         /*
1518                          * With pbias cell programming missing, this
1519                          * can't be allowed on MMC1 when booting with device
1520                          * tree.
1521                          */
1522                         !host->pbias_disable) {
1523                                 /*
1524                                  * The mmc_select_voltage fn of the core does
1525                                  * not seem to set the power_mode to
1526                                  * MMC_POWER_UP upon recalculating the voltage.
1527                                  * vdd 1.8v.
1528                                  */
1529                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1530                                 dev_dbg(mmc_dev(host->mmc),
1531                                                 "Switch operation failed\n");
1532                 }
1533         }
1534
1535         omap_hsmmc_set_clock(host);
1536
1537         if (do_send_init_stream)
1538                 send_init_stream(host);
1539
1540         omap_hsmmc_set_bus_mode(host);
1541
1542         pm_runtime_put_autosuspend(host->dev);
1543 }
1544
1545 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1546 {
1547         struct omap_hsmmc_host *host = mmc_priv(mmc);
1548
1549         if (!mmc_slot(host).card_detect)
1550                 return -ENOSYS;
1551         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1552 }
1553
1554 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1555 {
1556         struct omap_hsmmc_host *host = mmc_priv(mmc);
1557
1558         if (!mmc_slot(host).get_ro)
1559                 return -ENOSYS;
1560         return mmc_slot(host).get_ro(host->dev, 0);
1561 }
1562
1563 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1564 {
1565         struct omap_hsmmc_host *host = mmc_priv(mmc);
1566
1567         if (mmc_slot(host).init_card)
1568                 mmc_slot(host).init_card(card);
1569 }
1570
1571 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1572 {
1573         u32 hctl, capa, value;
1574
1575         /* Only MMC1 supports 3.0V */
1576         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1577                 hctl = SDVS30;
1578                 capa = VS30 | VS18;
1579         } else {
1580                 hctl = SDVS18;
1581                 capa = VS18;
1582         }
1583
1584         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1585         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1586
1587         value = OMAP_HSMMC_READ(host->base, CAPA);
1588         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1589
1590         /* Set SD bus power bit */
1591         set_sd_bus_power(host);
1592 }
1593
1594 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1595 {
1596         struct omap_hsmmc_host *host = mmc_priv(mmc);
1597
1598         pm_runtime_get_sync(host->dev);
1599
1600         return 0;
1601 }
1602
1603 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1604 {
1605         struct omap_hsmmc_host *host = mmc_priv(mmc);
1606
1607         pm_runtime_mark_last_busy(host->dev);
1608         pm_runtime_put_autosuspend(host->dev);
1609
1610         return 0;
1611 }
1612
1613 static const struct mmc_host_ops omap_hsmmc_ops = {
1614         .enable = omap_hsmmc_enable_fclk,
1615         .disable = omap_hsmmc_disable_fclk,
1616         .post_req = omap_hsmmc_post_req,
1617         .pre_req = omap_hsmmc_pre_req,
1618         .request = omap_hsmmc_request,
1619         .set_ios = omap_hsmmc_set_ios,
1620         .get_cd = omap_hsmmc_get_cd,
1621         .get_ro = omap_hsmmc_get_ro,
1622         .init_card = omap_hsmmc_init_card,
1623         /* NYET -- enable_sdio_irq */
1624 };
1625
1626 #ifdef CONFIG_DEBUG_FS
1627
1628 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1629 {
1630         struct mmc_host *mmc = s->private;
1631         struct omap_hsmmc_host *host = mmc_priv(mmc);
1632
1633         seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n",
1634                         mmc->index, host->context_loss);
1635
1636         pm_runtime_get_sync(host->dev);
1637
1638         seq_printf(s, "CON:\t\t0x%08x\n",
1639                         OMAP_HSMMC_READ(host->base, CON));
1640         seq_printf(s, "HCTL:\t\t0x%08x\n",
1641                         OMAP_HSMMC_READ(host->base, HCTL));
1642         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1643                         OMAP_HSMMC_READ(host->base, SYSCTL));
1644         seq_printf(s, "IE:\t\t0x%08x\n",
1645                         OMAP_HSMMC_READ(host->base, IE));
1646         seq_printf(s, "ISE:\t\t0x%08x\n",
1647                         OMAP_HSMMC_READ(host->base, ISE));
1648         seq_printf(s, "CAPA:\t\t0x%08x\n",
1649                         OMAP_HSMMC_READ(host->base, CAPA));
1650
1651         pm_runtime_mark_last_busy(host->dev);
1652         pm_runtime_put_autosuspend(host->dev);
1653
1654         return 0;
1655 }
1656
1657 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1658 {
1659         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1660 }
1661
1662 static const struct file_operations mmc_regs_fops = {
1663         .open           = omap_hsmmc_regs_open,
1664         .read           = seq_read,
1665         .llseek         = seq_lseek,
1666         .release        = single_release,
1667 };
1668
1669 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1670 {
1671         if (mmc->debugfs_root)
1672                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1673                         mmc, &mmc_regs_fops);
1674 }
1675
1676 #else
1677
1678 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1679 {
1680 }
1681
1682 #endif
1683
1684 #ifdef CONFIG_OF
1685 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1686         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1687         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1688 };
1689
1690 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1691         .reg_offset = 0x100,
1692 };
1693
1694 static const struct of_device_id omap_mmc_of_match[] = {
1695         {
1696                 .compatible = "ti,omap2-hsmmc",
1697         },
1698         {
1699                 .compatible = "ti,omap3-pre-es3-hsmmc",
1700                 .data = &omap3_pre_es3_mmc_of_data,
1701         },
1702         {
1703                 .compatible = "ti,omap3-hsmmc",
1704         },
1705         {
1706                 .compatible = "ti,omap4-hsmmc",
1707                 .data = &omap4_mmc_of_data,
1708         },
1709         {},
1710 };
1711 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1712
1713 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1714 {
1715         struct omap_mmc_platform_data *pdata;
1716         struct device_node *np = dev->of_node;
1717         u32 bus_width, max_freq;
1718         int cd_gpio, wp_gpio;
1719
1720         cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1721         wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1722         if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1723                 return ERR_PTR(-EPROBE_DEFER);
1724
1725         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1726         if (!pdata)
1727                 return NULL; /* out of memory */
1728
1729         if (of_find_property(np, "ti,dual-volt", NULL))
1730                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1731
1732         /* This driver only supports 1 slot */
1733         pdata->nr_slots = 1;
1734         pdata->slots[0].switch_pin = cd_gpio;
1735         pdata->slots[0].gpio_wp = wp_gpio;
1736
1737         if (of_find_property(np, "ti,non-removable", NULL)) {
1738                 pdata->slots[0].nonremovable = true;
1739                 pdata->slots[0].no_regulator_off_init = true;
1740         }
1741         of_property_read_u32(np, "bus-width", &bus_width);
1742         if (bus_width == 4)
1743                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1744         else if (bus_width == 8)
1745                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1746
1747         if (of_find_property(np, "ti,needs-special-reset", NULL))
1748                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1749
1750         if (!of_property_read_u32(np, "max-frequency", &max_freq))
1751                 pdata->max_freq = max_freq;
1752
1753         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1754                 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1755
1756         return pdata;
1757 }
1758 #else
1759 static inline struct omap_mmc_platform_data
1760                         *of_get_hsmmc_pdata(struct device *dev)
1761 {
1762         return NULL;
1763 }
1764 #endif
1765
1766 static int omap_hsmmc_probe(struct platform_device *pdev)
1767 {
1768         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1769         struct mmc_host *mmc;
1770         struct omap_hsmmc_host *host = NULL;
1771         struct resource *res;
1772         int ret, irq;
1773         const struct of_device_id *match;
1774         dma_cap_mask_t mask;
1775         unsigned tx_req, rx_req;
1776         struct pinctrl *pinctrl;
1777         const struct omap_mmc_of_data *data;
1778
1779         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1780         if (match) {
1781                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1782
1783                 if (IS_ERR(pdata))
1784                         return PTR_ERR(pdata);
1785
1786                 if (match->data) {
1787                         data = match->data;
1788                         pdata->reg_offset = data->reg_offset;
1789                         pdata->controller_flags |= data->controller_flags;
1790                 }
1791         }
1792
1793         if (pdata == NULL) {
1794                 dev_err(&pdev->dev, "Platform Data is missing\n");
1795                 return -ENXIO;
1796         }
1797
1798         if (pdata->nr_slots == 0) {
1799                 dev_err(&pdev->dev, "No Slots\n");
1800                 return -ENXIO;
1801         }
1802
1803         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1804         irq = platform_get_irq(pdev, 0);
1805         if (res == NULL || irq < 0)
1806                 return -ENXIO;
1807
1808         res = request_mem_region(res->start, resource_size(res), pdev->name);
1809         if (res == NULL)
1810                 return -EBUSY;
1811
1812         ret = omap_hsmmc_gpio_init(pdata);
1813         if (ret)
1814                 goto err;
1815
1816         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1817         if (!mmc) {
1818                 ret = -ENOMEM;
1819                 goto err_alloc;
1820         }
1821
1822         host            = mmc_priv(mmc);
1823         host->mmc       = mmc;
1824         host->pdata     = pdata;
1825         host->dev       = &pdev->dev;
1826         host->use_dma   = 1;
1827         host->dma_ch    = -1;
1828         host->irq       = irq;
1829         host->slot_id   = 0;
1830         host->mapbase   = res->start + pdata->reg_offset;
1831         host->base      = ioremap(host->mapbase, SZ_4K);
1832         host->power_mode = MMC_POWER_OFF;
1833         host->next_data.cookie = 1;
1834
1835         platform_set_drvdata(pdev, host);
1836
1837         mmc->ops        = &omap_hsmmc_ops;
1838
1839         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1840
1841         if (pdata->max_freq > 0)
1842                 mmc->f_max = pdata->max_freq;
1843         else
1844                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1845
1846         spin_lock_init(&host->irq_lock);
1847
1848         host->fclk = clk_get(&pdev->dev, "fck");
1849         if (IS_ERR(host->fclk)) {
1850                 ret = PTR_ERR(host->fclk);
1851                 host->fclk = NULL;
1852                 goto err1;
1853         }
1854
1855         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1856                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1857                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1858         }
1859
1860         pm_runtime_enable(host->dev);
1861         pm_runtime_get_sync(host->dev);
1862         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1863         pm_runtime_use_autosuspend(host->dev);
1864
1865         omap_hsmmc_context_save(host);
1866
1867         /* This can be removed once we support PBIAS with DT */
1868         if (host->dev->of_node && res->start == 0x4809c000)
1869                 host->pbias_disable = 1;
1870
1871         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1872         /*
1873          * MMC can still work without debounce clock.
1874          */
1875         if (IS_ERR(host->dbclk)) {
1876                 host->dbclk = NULL;
1877         } else if (clk_prepare_enable(host->dbclk) != 0) {
1878                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1879                 clk_put(host->dbclk);
1880                 host->dbclk = NULL;
1881         }
1882
1883         /* Since we do only SG emulation, we can have as many segs
1884          * as we want. */
1885         mmc->max_segs = 1024;
1886
1887         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1888         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1889         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1890         mmc->max_seg_size = mmc->max_req_size;
1891
1892         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1893                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1894
1895         mmc->caps |= mmc_slot(host).caps;
1896         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1897                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1898
1899         if (mmc_slot(host).nonremovable)
1900                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1901
1902         mmc->pm_caps = mmc_slot(host).pm_caps;
1903
1904         omap_hsmmc_conf_bus_power(host);
1905
1906         if (!pdev->dev.of_node) {
1907                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1908                 if (!res) {
1909                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1910                         ret = -ENXIO;
1911                         goto err_irq;
1912                 }
1913                 tx_req = res->start;
1914
1915                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1916                 if (!res) {
1917                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1918                         ret = -ENXIO;
1919                         goto err_irq;
1920                 }
1921                 rx_req = res->start;
1922         }
1923
1924         dma_cap_zero(mask);
1925         dma_cap_set(DMA_SLAVE, mask);
1926
1927         host->rx_chan =
1928                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1929                                                  &rx_req, &pdev->dev, "rx");
1930
1931         if (!host->rx_chan) {
1932                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1933                 ret = -ENXIO;
1934                 goto err_irq;
1935         }
1936
1937         host->tx_chan =
1938                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1939                                                  &tx_req, &pdev->dev, "tx");
1940
1941         if (!host->tx_chan) {
1942                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1943                 ret = -ENXIO;
1944                 goto err_irq;
1945         }
1946
1947         /* Request IRQ for MMC operations */
1948         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1949                         mmc_hostname(mmc), host);
1950         if (ret) {
1951                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1952                 goto err_irq;
1953         }
1954
1955         if (pdata->init != NULL) {
1956                 if (pdata->init(&pdev->dev) != 0) {
1957                         dev_err(mmc_dev(host->mmc),
1958                                 "Unable to configure MMC IRQs\n");
1959                         goto err_irq_cd_init;
1960                 }
1961         }
1962
1963         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1964                 ret = omap_hsmmc_reg_get(host);
1965                 if (ret)
1966                         goto err_reg;
1967                 host->use_reg = 1;
1968         }
1969
1970         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1971
1972         /* Request IRQ for card detect */
1973         if ((mmc_slot(host).card_detect_irq)) {
1974                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1975                                            NULL,
1976                                            omap_hsmmc_detect,
1977                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1978                                            mmc_hostname(mmc), host);
1979                 if (ret) {
1980                         dev_err(mmc_dev(host->mmc),
1981                                 "Unable to grab MMC CD IRQ\n");
1982                         goto err_irq_cd;
1983                 }
1984                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1985                 pdata->resume = omap_hsmmc_resume_cdirq;
1986         }
1987
1988         omap_hsmmc_disable_irq(host);
1989
1990         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1991         if (IS_ERR(pinctrl))
1992                 dev_warn(&pdev->dev,
1993                         "pins are not configured from the driver\n");
1994
1995         omap_hsmmc_protect_card(host);
1996
1997         mmc_add_host(mmc);
1998
1999         if (mmc_slot(host).name != NULL) {
2000                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2001                 if (ret < 0)
2002                         goto err_slot_name;
2003         }
2004         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2005                 ret = device_create_file(&mmc->class_dev,
2006                                         &dev_attr_cover_switch);
2007                 if (ret < 0)
2008                         goto err_slot_name;
2009         }
2010
2011         omap_hsmmc_debugfs(mmc);
2012         pm_runtime_mark_last_busy(host->dev);
2013         pm_runtime_put_autosuspend(host->dev);
2014
2015         return 0;
2016
2017 err_slot_name:
2018         mmc_remove_host(mmc);
2019         free_irq(mmc_slot(host).card_detect_irq, host);
2020 err_irq_cd:
2021         if (host->use_reg)
2022                 omap_hsmmc_reg_put(host);
2023 err_reg:
2024         if (host->pdata->cleanup)
2025                 host->pdata->cleanup(&pdev->dev);
2026 err_irq_cd_init:
2027         free_irq(host->irq, host);
2028 err_irq:
2029         if (host->tx_chan)
2030                 dma_release_channel(host->tx_chan);
2031         if (host->rx_chan)
2032                 dma_release_channel(host->rx_chan);
2033         pm_runtime_put_sync(host->dev);
2034         pm_runtime_disable(host->dev);
2035         clk_put(host->fclk);
2036         if (host->dbclk) {
2037                 clk_disable_unprepare(host->dbclk);
2038                 clk_put(host->dbclk);
2039         }
2040 err1:
2041         iounmap(host->base);
2042         mmc_free_host(mmc);
2043 err_alloc:
2044         omap_hsmmc_gpio_free(pdata);
2045 err:
2046         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2047         if (res)
2048                 release_mem_region(res->start, resource_size(res));
2049         return ret;
2050 }
2051
2052 static int omap_hsmmc_remove(struct platform_device *pdev)
2053 {
2054         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2055         struct resource *res;
2056
2057         pm_runtime_get_sync(host->dev);
2058         mmc_remove_host(host->mmc);
2059         if (host->use_reg)
2060                 omap_hsmmc_reg_put(host);
2061         if (host->pdata->cleanup)
2062                 host->pdata->cleanup(&pdev->dev);
2063         free_irq(host->irq, host);
2064         if (mmc_slot(host).card_detect_irq)
2065                 free_irq(mmc_slot(host).card_detect_irq, host);
2066
2067         if (host->tx_chan)
2068                 dma_release_channel(host->tx_chan);
2069         if (host->rx_chan)
2070                 dma_release_channel(host->rx_chan);
2071
2072         pm_runtime_put_sync(host->dev);
2073         pm_runtime_disable(host->dev);
2074         clk_put(host->fclk);
2075         if (host->dbclk) {
2076                 clk_disable_unprepare(host->dbclk);
2077                 clk_put(host->dbclk);
2078         }
2079
2080         omap_hsmmc_gpio_free(host->pdata);
2081         iounmap(host->base);
2082         mmc_free_host(host->mmc);
2083
2084         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2085         if (res)
2086                 release_mem_region(res->start, resource_size(res));
2087
2088         return 0;
2089 }
2090
2091 #ifdef CONFIG_PM
2092 static int omap_hsmmc_prepare(struct device *dev)
2093 {
2094         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2095
2096         if (host->pdata->suspend)
2097                 return host->pdata->suspend(dev, host->slot_id);
2098
2099         return 0;
2100 }
2101
2102 static void omap_hsmmc_complete(struct device *dev)
2103 {
2104         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2105
2106         if (host->pdata->resume)
2107                 host->pdata->resume(dev, host->slot_id);
2108
2109 }
2110
2111 static int omap_hsmmc_suspend(struct device *dev)
2112 {
2113         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2114
2115         if (!host)
2116                 return 0;
2117
2118         pm_runtime_get_sync(host->dev);
2119
2120         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2121                 omap_hsmmc_disable_irq(host);
2122                 OMAP_HSMMC_WRITE(host->base, HCTL,
2123                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2124         }
2125
2126         if (host->dbclk)
2127                 clk_disable_unprepare(host->dbclk);
2128
2129         pm_runtime_put_sync(host->dev);
2130         return 0;
2131 }
2132
2133 /* Routine to resume the MMC device */
2134 static int omap_hsmmc_resume(struct device *dev)
2135 {
2136         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2137
2138         if (!host)
2139                 return 0;
2140
2141         pm_runtime_get_sync(host->dev);
2142
2143         if (host->dbclk)
2144                 clk_prepare_enable(host->dbclk);
2145
2146         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2147                 omap_hsmmc_conf_bus_power(host);
2148
2149         omap_hsmmc_protect_card(host);
2150
2151         pm_runtime_mark_last_busy(host->dev);
2152         pm_runtime_put_autosuspend(host->dev);
2153         return 0;
2154 }
2155
2156 #else
2157 #define omap_hsmmc_prepare      NULL
2158 #define omap_hsmmc_complete     NULL
2159 #define omap_hsmmc_suspend      NULL
2160 #define omap_hsmmc_resume       NULL
2161 #endif
2162
2163 static int omap_hsmmc_runtime_suspend(struct device *dev)
2164 {
2165         struct omap_hsmmc_host *host;
2166
2167         host = platform_get_drvdata(to_platform_device(dev));
2168         omap_hsmmc_context_save(host);
2169         dev_dbg(dev, "disabled\n");
2170
2171         return 0;
2172 }
2173
2174 static int omap_hsmmc_runtime_resume(struct device *dev)
2175 {
2176         struct omap_hsmmc_host *host;
2177
2178         host = platform_get_drvdata(to_platform_device(dev));
2179         omap_hsmmc_context_restore(host);
2180         dev_dbg(dev, "enabled\n");
2181
2182         return 0;
2183 }
2184
2185 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2186         .suspend        = omap_hsmmc_suspend,
2187         .resume         = omap_hsmmc_resume,
2188         .prepare        = omap_hsmmc_prepare,
2189         .complete       = omap_hsmmc_complete,
2190         .runtime_suspend = omap_hsmmc_runtime_suspend,
2191         .runtime_resume = omap_hsmmc_runtime_resume,
2192 };
2193
2194 static struct platform_driver omap_hsmmc_driver = {
2195         .probe          = omap_hsmmc_probe,
2196         .remove         = omap_hsmmc_remove,
2197         .driver         = {
2198                 .name = DRIVER_NAME,
2199                 .owner = THIS_MODULE,
2200                 .pm = &omap_hsmmc_dev_pm_ops,
2201                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2202         },
2203 };
2204
2205 module_platform_driver(omap_hsmmc_driver);
2206 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2207 MODULE_LICENSE("GPL");
2208 MODULE_ALIAS("platform:" DRIVER_NAME);
2209 MODULE_AUTHOR("Texas Instruments Inc");